ENGR00326277-2 imx6: watchdog: use WDOG_B mode for wdog reset in ldo-bypass mode

In ldo-bypass mode, we need trigger WDOG_B pin to reset pmic in ldo-bypass mode. Signed-off-by: Robin Gong <b38343@freescale.com>

ENGR00326277-2 imx6: watchdog: use WDOG_B mode for wdog reset in ldo-bypass mode
In ldo-bypass mode, we need trigger WDOG_B pin to reset pmic in ldo-bypass mode. Signed-off-by: Robin Gong <b38343@freescale.com>
Robin Gong
1 parent 404fd02e96
Showing 7 changed files with 28 additions and 7 deletions Side-by-side Diff
arch/arm/cpu/armv7/mx6/soc.c
arch/arm/include/asm/arch-mx6/sys_proto.h
board/freescale/mx6sabresd/mx6sabresd.c
board/freescale/mx6slevk/mx6slevk.c
board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c
board/freescale/mx6sx_19x19_arm2/mx6sx_19x19_arm2.c
board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -869,14 +869,34 @@
 #endif
 }
  
-int set_anatop_bypass(void)
+int set_anatop_bypass(int wdog_reset_pin)
 {
 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	struct wdog_regs *wdog;
 	u32 reg = readl(&anatop->reg_core);
  
 	/* bypass VDDARM/VDDSOC */
 	reg = reg | (0x1F << 18) | 0x1F;
 	writel(reg, &anatop->reg_core);
+
+	if (wdog_reset_pin == 2)
+		wdog = (struct wdog_regs *) WDOG2_BASE_ADDR;
+	else if (wdog_reset_pin == 1)
+		wdog = (struct wdog_regs *) WDOG1_BASE_ADDR;
+	else
+		return arm_orig_podf;
+	/*
+	 * use WDOG_B mode to reset external pmic because it's risky for the
+	 * following watchdog reboot in case of cpu freq at lowest 400Mhz with
+	 * ldo-bypass mode. Because boot frequency maybe higher 800Mhz i.e. So
+	 * in ldo-bypass mode watchdog reset will only triger POR reset, not
+	 * WDOG reset. But below code depends on hardware design, if HW didn't
+	 * connect WDOG_B pin to external pmic such as i.mx6slevk, we can skip
+	 * these code since it assumed boot from 400Mhz always.
+	 */
+	reg = readw(&wdog->wcr);
+	reg |= 1 << 3;
+	writew(reg, &wdog->wcr);
  
 	return arm_orig_podf;
 }
@@ -26,7 +26,7 @@
 #ifdef CONFIG_LDO_BYPASS_CHECK
 int check_ldo_bypass(void);
 int check_1_2G(void);
-int set_anatop_bypass(void);
+int set_anatop_bypass(int wdog_reset_pin);
 void ldo_mode_set(int ldo_bypass);
 void prep_anatop_bypass(void);
 void finish_anatop_bypass(void);
@@ -253,6 +253,7 @@
 }
  
 #ifdef CONFIG_SYS_I2C_MXC
+
 /* set all switches APS in normal and PFM mode in standby */
 static int setup_pmic_mode(int chip)
 {
@@ -456,7 +457,7 @@
 		 * VDDARM:1.175V@800M; VDDSOC:1.175V@800M
 		 * VDDARM:1.075V@400M; VDDSOC:1.175V@400M
 		 */
-		is_400M = set_anatop_bypass();
+		is_400M = set_anatop_bypass(2);
 		if (is_400M)
 #if defined(CONFIG_MX6DL)
 			vddarm = 0x1f;
@@ -787,7 +787,7 @@
 			return;
 		}
  
-		is_400M = set_anatop_bypass();
+		is_400M = set_anatop_bypass(0);
  
 		/*
 		 * MX6SL: VDDARM:1.175V@800M; VDDSOC:1.175V@800M
@@ -737,7 +737,7 @@
 			return;
 		}
  
-		set_anatop_bypass();
+		set_anatop_bypass(1);
 		printf("switch to ldo_bypass mode!\n");
 	}
  
@@ -784,7 +784,7 @@
 			return;
 		}
  
-		set_anatop_bypass();
+		set_anatop_bypass(1);
 		printf("switch to ldo_bypass mode!\n");
 	}
  
@@ -801,7 +801,7 @@
 			return;
 		}
  
-		set_anatop_bypass();
+		set_anatop_bypass(1);
 		printf("switch to ldo_bypass mode!\n");
 	}
...	...	@@ -869,14 +869,34 @@
869	869	#endif
870	870	}
871	871
872		-int set_anatop_bypass(void)
	872	+int set_anatop_bypass(int wdog_reset_pin)
873	873	{
874	874	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
	875	+ struct wdog_regs *wdog;
875	876	u32 reg = readl(&anatop->reg_core);
876	877
877	878	/* bypass VDDARM/VDDSOC */
878	879	reg = reg \| (0x1F << 18) \| 0x1F;
879	880	writel(reg, &anatop->reg_core);
	881	+
	882	+ if (wdog_reset_pin == 2)
	883	+ wdog = (struct wdog_regs *) WDOG2_BASE_ADDR;
	884	+ else if (wdog_reset_pin == 1)
	885	+ wdog = (struct wdog_regs *) WDOG1_BASE_ADDR;
	886	+ else
	887	+ return arm_orig_podf;
	888	+ /*
	889	+ * use WDOG_B mode to reset external pmic because it's risky for the
	890	+ * following watchdog reboot in case of cpu freq at lowest 400Mhz with
	891	+ * ldo-bypass mode. Because boot frequency maybe higher 800Mhz i.e. So
	892	+ * in ldo-bypass mode watchdog reset will only triger POR reset, not
	893	+ * WDOG reset. But below code depends on hardware design, if HW didn't
	894	+ * connect WDOG_B pin to external pmic such as i.mx6slevk, we can skip
	895	+ * these code since it assumed boot from 400Mhz always.
	896	+ */
	897	+ reg = readw(&wdog->wcr);
	898	+ reg \|= 1 << 3;
	899	+ writew(reg, &wdog->wcr);
880	900
881	901	return arm_orig_podf;
882	902	}
...	...	@@ -26,7 +26,7 @@
26	26	#ifdef CONFIG_LDO_BYPASS_CHECK
27	27	int check_ldo_bypass(void);
28	28	int check_1_2G(void);
29		-int set_anatop_bypass(void);
	29	+int set_anatop_bypass(int wdog_reset_pin);
30	30	void ldo_mode_set(int ldo_bypass);
31	31	void prep_anatop_bypass(void);
32	32	void finish_anatop_bypass(void);
...	...	@@ -253,6 +253,7 @@
253	253	}
254	254
255	255	#ifdef CONFIG_SYS_I2C_MXC
	256	+
256	257	/* set all switches APS in normal and PFM mode in standby */
257	258	static int setup_pmic_mode(int chip)
258	259	{
...	...	@@ -456,7 +457,7 @@
456	457	* VDDARM:1.175V@800M; VDDSOC:1.175V@800M
457	458	* VDDARM:1.075V@400M; VDDSOC:1.175V@400M
458	459	*/
459		- is_400M = set_anatop_bypass();
	460	+ is_400M = set_anatop_bypass(2);
460	461	if (is_400M)
461	462	#if defined(CONFIG_MX6DL)
462	463	vddarm = 0x1f;
...	...	@@ -787,7 +787,7 @@
787	787	return;
788	788	}
789	789
790		- is_400M = set_anatop_bypass();
	790	+ is_400M = set_anatop_bypass(0);
791	791
792	792	/*
793	793	* MX6SL: VDDARM:1.175V@800M; VDDSOC:1.175V@800M
...	...	@@ -737,7 +737,7 @@
737	737	return;
738	738	}
739	739
740		- set_anatop_bypass();
	740	+ set_anatop_bypass(1);
741	741	printf("switch to ldo_bypass mode!\n");
742	742	}
743	743
...	...	@@ -784,7 +784,7 @@
784	784	return;
785	785	}
786	786
787		- set_anatop_bypass();
	787	+ set_anatop_bypass(1);
788	788	printf("switch to ldo_bypass mode!\n");
789	789	}
790	790
...	...	@@ -801,7 +801,7 @@
801	801	return;
802	802	}
803	803
804		- set_anatop_bypass();
	804	+ set_anatop_bypass(1);
805	805	printf("switch to ldo_bypass mode!\n");
806	806	}
807	807