Eric Lee / smarc-uboot

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Commit 128b1aaf8d0bd7bd9340cdf13fc9204c4995e774

Authored by Jacky Bai
1 parent 4c530d1979
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 4 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

MLK-21068 board: imx8mm_evk: update the lpddr4 timing config 

Update the lpddr4 timing config to align with the ddr tool

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit a1433dec3a03a6c944b61600e7b317e2a83f2981)

Showing 1 changed file with 288 additions and 414 deletions Side-by-side Diff

board/freescale/imx8mm_evk/lpddr4_timing.c
Diff comments   View file @ 128b1aa
Changes suppressed. Click to show
1 1 /*
2   - * Copyright 2018 NXP
  2 + * Copyright 2018-2019 NXP
3 3 *
4   - * SPDX-License-Identifier: GPL-2.0+
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Generated code from MX8M_DDR_tool
5 7 */
  8 +
6 9 #include <linux/kernel.h>
7   -#include <common.h>
8   -#include <asm/arch/ddr.h>
9   -#include <asm/arch/lpddr4_define.h>
10 10 #include <asm/arch/imx8m_ddr.h>
11 11  
12   -struct dram_cfg_param lpddr4_ddrc_cfg[] = {
13   - /* Start to config, default 3200mbps */
14   - { DDRC_DBG1(0), 0x00000001 },
15   - { DDRC_PWRCTL(0), 0x00000001 },
16   - { DDRC_MSTR(0), 0xa1080020 },
17   - { DDRC_RFSHTMG(0), 0x005b00d2 },
18   - { DDRC_INIT0(0), 0xC003061B },
19   - { DDRC_INIT1(0), 0x009D0000 },
20   - { DDRC_INIT3(0), 0x00D4002D },
21   - { DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
22   - { DDRC_INIT6(0), 0x0066004a },
23   - { DDRC_INIT7(0), 0x0006004a },
  12 +struct dram_cfg_param ddr_ddrc_cfg[] = {
  13 + /* Initialize DDRC registers */
  14 + { 0x3d400304, 0x1 },
  15 + { 0x3d400030, 0x1 },
  16 + { 0x3d400000, 0xa1080020 },
  17 + { 0x3d400020, 0x223 },
  18 + { 0x3d400024, 0x16e3600 },
  19 + { 0x3d400064, 0x5b00d2 },
  20 + { 0x3d4000d0, 0xc00305ba },
  21 + { 0x3d4000d4, 0x940000 },
  22 + { 0x3d4000dc, 0xd4002d },
  23 + { 0x3d4000e0, 0x310000 },
  24 + { 0x3d4000e8, 0x66004d },
  25 + { 0x3d4000ec, 0x16004d },
  26 + { 0x3d400100, 0x191e1920 },
  27 + { 0x3d400104, 0x60630 },
  28 + { 0x3d40010c, 0xb0b000 },
  29 + { 0x3d400110, 0xe04080e },
  30 + { 0x3d400114, 0x2040c0c },
  31 + { 0x3d400118, 0x1010007 },
  32 + { 0x3d40011c, 0x401 },
  33 + { 0x3d400130, 0x20600 },
  34 + { 0x3d400134, 0xc100002 },
  35 + { 0x3d400138, 0xd8 },
  36 + { 0x3d400144, 0x96004b },
  37 + { 0x3d400180, 0x2ee0017 },
  38 + { 0x3d400184, 0x2605b8e },
  39 + { 0x3d400188, 0x0 },
  40 + { 0x3d400190, 0x497820a },
  41 + { 0x3d400194, 0x80303 },
  42 + { 0x3d4001b4, 0x170a },
  43 + { 0x3d4001a0, 0xe0400018 },
  44 + { 0x3d4001a4, 0xdf00e4 },
  45 + { 0x3d4001a8, 0x80000000 },
  46 + { 0x3d4001b0, 0x11 },
  47 + { 0x3d4001c0, 0x1 },
  48 + { 0x3d4001c4, 0x0 },
  49 + { 0x3d4000f4, 0xc99 },
  50 + { 0x3d400108, 0x70e1617 },
  51 + { 0x3d400200, 0x1f },
  52 + { 0x3d40020c, 0x0 },
  53 + { 0x3d400210, 0x1f1f },
  54 + { 0x3d400204, 0x80808 },
  55 + { 0x3d400214, 0x7070707 },
  56 + { 0x3d400218, 0x7070707 },
24 57  
25   - { DDRC_DRAMTMG0(0), 0x1A201B22 },
26   - { DDRC_DRAMTMG1(0), 0x00060633 },
27   - { DDRC_DRAMTMG3(0), 0x00C0C000 },
28   - { DDRC_DRAMTMG4(0), 0x0F04080F },
29   - { DDRC_DRAMTMG5(0), 0x02040C0C },
30   - { DDRC_DRAMTMG6(0), 0x01010007 },
31   - { DDRC_DRAMTMG7(0), 0x00000401 },
32   - { DDRC_DRAMTMG12(0), 0x00020600 },
33   - { DDRC_DRAMTMG13(0), 0x0C100002 },
34   - { DDRC_DRAMTMG14(0), 0x000000E6 },
35   - { DDRC_DRAMTMG17(0), 0x00A00050 },
36   -
37   - { DDRC_ZQCTL0(0), 0x03200018 },
38   - { DDRC_ZQCTL1(0), 0x028061A8 },
39   - { DDRC_ZQCTL2(0), 0x00000000 },
40   -
41   - { DDRC_DFITMG0(0), 0x0497820A },
42   - { DDRC_DFITMG2(0), 0x0000170A },
43   - { DDRC_DRAMTMG2(0), 0x070E171a },
44   - { DDRC_DBICTL(0), 0x00000001 },
45   -
46   - { DDRC_DFITMG1(0), 0x00080303 },
47   - { DDRC_DFIUPD0(0), 0xE0400018 },
48   - { DDRC_DFIUPD1(0), 0x00DF00E4 },
49   - { DDRC_DFIUPD2(0), 0x80000000 },
50   - { DDRC_DFIMISC(0), 0x00000011 },
51   -
52   - { DDRC_DFIPHYMSTR(0), 0x00000000 },
53   - { DDRC_RANKCTL(0), 0x00000c99 },
54   -
55   - /* address mapping */
56   - { DDRC_ADDRMAP0(0), 0x0000001f },
57   - { DDRC_ADDRMAP1(0), 0x00080808 },
58   - { DDRC_ADDRMAP2(0), 0x00000000 },
59   - { DDRC_ADDRMAP3(0), 0x00000000 },
60   - { DDRC_ADDRMAP4(0), 0x00001f1f },
61   - { DDRC_ADDRMAP5(0), 0x07070707 },
62   - { DDRC_ADDRMAP6(0), 0x07070707 },
63   - { DDRC_ADDRMAP7(0), 0x00000f0f },
64   -
65 58 /* performance setting */
66   - { DDRC_SCHED(0), 0x29001701 },
67   - { DDRC_SCHED1(0), 0x0000002c },
68   - { DDRC_PERFHPR1(0), 0x04000030 },
69   - { DDRC_PERFLPR1(0), 0x900093e7 },
70   - { DDRC_PERFWR1(0), 0x20005574 },
71   - { DDRC_PCCFG(0), 0x00000111 },
72   - { DDRC_PCFGW_0(0), 0x000072ff },
73   - { DDRC_PCFGQOS0_0(0), 0x02100e07 },
74   - { DDRC_PCFGQOS1_0(0), 0x00620096 },
75   - { DDRC_PCFGWQOS0_0(0), 0x01100e07 },
76   - { DDRC_PCFGWQOS1_0(0), 0x00c8012c },
  59 + { 0x3d400250, 0x29001701 },
  60 + { 0x3d400254, 0x2c },
  61 + { 0x3d40025c, 0x4000030 },
  62 + { 0x3d400264, 0x900093e7 },
  63 + { 0x3d40026c, 0x2005574 },
  64 + { 0x3d400400, 0x111 },
  65 + { 0x3d400408, 0x72ff },
  66 + { 0x3d400494, 0x2100e07 },
  67 + { 0x3d400498, 0x620096 },
  68 + { 0x3d40049c, 0x1100e07 },
  69 + { 0x3d4004a0, 0xc8012c },
77 70  
78   - /* frequency P1&P2 */
79   - /* Frequency 1: 400mbps */
80   - { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
81   - { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
82   - { DDRC_FREQ1_DRAMTMG2(0), 0x0203090c },
83   - { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
84   - { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 },
85   - { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
86   - { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
87   - { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e },
88   - { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 },
89   - { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
90   - { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
91   - { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
92   - { DDRC_FREQ1_DFITMG0(0), 0x03818200 },
93   - { DDRC_FREQ1_DFITMG2(0), 0x00000000 },
94   - { DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
95   - { DDRC_FREQ1_INIT3(0), 0x00840000 },
96   - { DDRC_FREQ1_INIT4(0), 0x00310000 },
97   - { DDRC_FREQ1_INIT6(0), 0x0066004a },
98   - { DDRC_FREQ1_INIT7(0), 0x0006004a },
  71 + /* P1: 400mts */
  72 + { 0x3d402020, 0x21 },
  73 + { 0x3d402024, 0x30d400 },
  74 + { 0x3d402050, 0x20d040 },
  75 + { 0x3d402064, 0xc001c },
  76 + { 0x3d4020dc, 0x840000 },
  77 + { 0x3d4020e0, 0x310000 },
  78 + { 0x3d4020e8, 0x66004d },
  79 + { 0x3d4020ec, 0x16004d },
  80 + { 0x3d402100, 0xa040305 },
  81 + { 0x3d402104, 0x30407 },
  82 + { 0x3d402108, 0x203060b },
  83 + { 0x3d40210c, 0x505000 },
  84 + { 0x3d402110, 0x2040202 },
  85 + { 0x3d402114, 0x2030202 },
  86 + { 0x3d402118, 0x1010004 },
  87 + { 0x3d40211c, 0x301 },
  88 + { 0x3d402130, 0x20300 },
  89 + { 0x3d402134, 0xa100002 },
  90 + { 0x3d402138, 0x1d },
  91 + { 0x3d402144, 0x14000a },
  92 + { 0x3d402180, 0x640004 },
  93 + { 0x3d402190, 0x3818200 },
  94 + { 0x3d402194, 0x80303 },
  95 + { 0x3d4021b4, 0x100 },
99 96  
100   - /* Frequency 2: 100mbps */
101   - { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c },
102   - { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 },
103   - { DDRC_FREQ2_DRAMTMG2(0), 0x0203090c },
104   - { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
105   - { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 },
106   - { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 },
107   - { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 },
108   - { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e },
109   - { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 },
110   - { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b },
111   - { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 },
112   - { DDRC_FREQ2_DFITMG0(0), 0x03818200 },
113   - { DDRC_FREQ2_DFITMG2(0), 0x00000000 },
114   - { DDRC_FREQ2_RFSHTMG(0), 0x0003800c },
115   - { DDRC_FREQ2_RFSHTMG(0), 0x00030007 },
116   - { DDRC_FREQ2_INIT3(0), 0x00840000 },
117   - { DDRC_FREQ2_INIT4(0), 0x00310008 },
118   - { DDRC_FREQ2_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
119   - { DDRC_FREQ2_INIT6(0), 0x0066004a },
120   - { DDRC_FREQ2_INIT7(0), 0x0006004a },
  97 + /* p2: 100mts */
  98 + { 0x3d403020, 0x21 },
  99 + { 0x3d403024, 0xc3500 },
  100 + { 0x3d403050, 0x20d040 },
  101 + { 0x3d403064, 0x30007 },
  102 + { 0x3d4030dc, 0x840000 },
  103 + { 0x3d4030e0, 0x310000 },
  104 + { 0x3d4030e8, 0x66004d },
  105 + { 0x3d4030ec, 0x16004d },
  106 + { 0x3d403100, 0xa010102 },
  107 + { 0x3d403104, 0x30404 },
  108 + { 0x3d403108, 0x203060b },
  109 + { 0x3d40310c, 0x505000 },
  110 + { 0x3d403110, 0x2040202 },
  111 + { 0x3d403114, 0x2030202 },
  112 + { 0x3d403118, 0x1010004 },
  113 + { 0x3d40311c, 0x301 },
  114 + { 0x3d403130, 0x20300 },
  115 + { 0x3d403134, 0xa100002 },
  116 + { 0x3d403138, 0x8 },
  117 + { 0x3d403144, 0x50003 },
  118 + { 0x3d403180, 0x190004 },
  119 + { 0x3d403190, 0x3818200 },
  120 + { 0x3d403194, 0x80303 },
  121 + { 0x3d4031b4, 0x100 },
121 122  
122   - /* boot start point */
123   - { DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2
  123 + /* default boot point */
  124 + { 0x3d400028, 0x0 },
124 125 };
125 126  
126 127 /* PHY Initialize Configuration */
127   -struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
  128 +struct dram_cfg_param ddr_ddrphy_cfg[] = {
  129 + { 0x100a0, 0x0 },
  130 + { 0x100a1, 0x1 },
  131 + { 0x100a2, 0x2 },
  132 + { 0x100a3, 0x3 },
  133 + { 0x100a4, 0x4 },
  134 + { 0x100a5, 0x5 },
  135 + { 0x100a6, 0x6 },
  136 + { 0x100a7, 0x7 },
  137 + { 0x110a0, 0x0 },
  138 + { 0x110a1, 0x1 },
  139 + { 0x110a2, 0x3 },
  140 + { 0x110a3, 0x4 },
  141 + { 0x110a4, 0x5 },
  142 + { 0x110a5, 0x2 },
  143 + { 0x110a6, 0x7 },
  144 + { 0x110a7, 0x6 },
  145 + { 0x120a0, 0x0 },
  146 + { 0x120a1, 0x1 },
  147 + { 0x120a2, 0x3 },
  148 + { 0x120a3, 0x2 },
  149 + { 0x120a4, 0x5 },
  150 + { 0x120a5, 0x4 },
  151 + { 0x120a6, 0x7 },
  152 + { 0x120a7, 0x6 },
  153 + { 0x130a0, 0x0 },
  154 + { 0x130a1, 0x1 },
  155 + { 0x130a2, 0x2 },
  156 + { 0x130a3, 0x3 },
  157 + { 0x130a4, 0x4 },
  158 + { 0x130a5, 0x5 },
  159 + { 0x130a6, 0x6 },
  160 + { 0x130a7, 0x7 },
128 161 { 0x1005f, 0x1ff },
129 162 { 0x1015f, 0x1ff },
130 163 { 0x1105f, 0x1ff },
... ... @@ -133,7 +166,6 @@
133 166 { 0x1215f, 0x1ff },
134 167 { 0x1305f, 0x1ff },
135 168 { 0x1315f, 0x1ff },
136   -
137 169 { 0x11005f, 0x1ff },
138 170 { 0x11015f, 0x1ff },
139 171 { 0x11105f, 0x1ff },
... ... @@ -142,7 +174,6 @@
142 174 { 0x11215f, 0x1ff },
143 175 { 0x11305f, 0x1ff },
144 176 { 0x11315f, 0x1ff },
145   -
146 177 { 0x21005f, 0x1ff },
147 178 { 0x21015f, 0x1ff },
148 179 { 0x21105f, 0x1ff },
... ... @@ -151,7 +182,6 @@
151 182 { 0x21215f, 0x1ff },
152 183 { 0x21305f, 0x1ff },
153 184 { 0x21315f, 0x1ff },
154   -
155 185 { 0x55, 0x1ff },
156 186 { 0x1055, 0x1ff },
157 187 { 0x2055, 0x1ff },
158 188  
159 189  
160 190  
161 191  
162 192  
163 193  
164 194  
... ... @@ -162,32 +192,24 @@
162 192 { 0x7055, 0x1ff },
163 193 { 0x8055, 0x1ff },
164 194 { 0x9055, 0x1ff },
165   -
166 195 { 0x200c5, 0x19 },
167 196 { 0x1200c5, 0x7 },
168 197 { 0x2200c5, 0x7 },
169   -
170 198 { 0x2002e, 0x2 },
171 199 { 0x12002e, 0x2 },
172 200 { 0x22002e, 0x2 },
173   -
174 201 { 0x90204, 0x0 },
175 202 { 0x190204, 0x0 },
176 203 { 0x290204, 0x0 },
177   -
178   - { 0x20024, 0xab },
  204 + { 0x20024, 0x1ab },
179 205 { 0x2003a, 0x0 },
180   -
181   - { 0x120024, 0xab },
  206 + { 0x120024, 0x1ab },
182 207 { 0x2003a, 0x0 },
183   -
184   - { 0x220024, 0xab },
  208 + { 0x220024, 0x1ab },
185 209 { 0x2003a, 0x0 },
186   -
187 210 { 0x20056, 0x3 },
188 211 { 0x120056, 0xa },
189 212 { 0x220056, 0xa },
190   -
191 213 { 0x1004d, 0xe00 },
192 214 { 0x1014d, 0xe00 },
193 215 { 0x1104d, 0xe00 },
... ... @@ -196,7 +218,6 @@
196 218 { 0x1214d, 0xe00 },
197 219 { 0x1304d, 0xe00 },
198 220 { 0x1314d, 0xe00 },
199   -
200 221 { 0x11004d, 0xe00 },
201 222 { 0x11014d, 0xe00 },
202 223 { 0x11104d, 0xe00 },
... ... @@ -205,7 +226,6 @@
205 226 { 0x11214d, 0xe00 },
206 227 { 0x11304d, 0xe00 },
207 228 { 0x11314d, 0xe00 },
208   -
209 229 { 0x21004d, 0xe00 },
210 230 { 0x21014d, 0xe00 },
211 231 { 0x21104d, 0xe00 },
... ... @@ -214,34 +234,30 @@
214 234 { 0x21214d, 0xe00 },
215 235 { 0x21304d, 0xe00 },
216 236 { 0x21314d, 0xe00 },
217   -
218   - { 0x10049, 0xfbe },
219   - { 0x10149, 0xfbe },
220   - { 0x11049, 0xfbe },
221   - { 0x11149, 0xfbe },
222   - { 0x12049, 0xfbe },
223   - { 0x12149, 0xfbe },
224   - { 0x13049, 0xfbe },
225   - { 0x13149, 0xfbe },
226   -
227   - { 0x110049, 0xfbe },
228   - { 0x110149, 0xfbe },
229   - { 0x111049, 0xfbe },
230   - { 0x111149, 0xfbe },
231   - { 0x112049, 0xfbe },
232   - { 0x112149, 0xfbe },
233   - { 0x113049, 0xfbe },
234   - { 0x113149, 0xfbe },
235   -
236   - { 0x210049, 0xfbe },
237   - { 0x210149, 0xfbe },
238   - { 0x211049, 0xfbe },
239   - { 0x211149, 0xfbe },
240   - { 0x212049, 0xfbe },
241   - { 0x212149, 0xfbe },
242   - { 0x213049, 0xfbe },
243   - { 0x213149, 0xfbe },
244   -
  237 + { 0x10049, 0xeba },
  238 + { 0x10149, 0xeba },
  239 + { 0x11049, 0xeba },
  240 + { 0x11149, 0xeba },
  241 + { 0x12049, 0xeba },
  242 + { 0x12149, 0xeba },
  243 + { 0x13049, 0xeba },
  244 + { 0x13149, 0xeba },
  245 + { 0x110049, 0xeba },
  246 + { 0x110149, 0xeba },
  247 + { 0x111049, 0xeba },
  248 + { 0x111149, 0xeba },
  249 + { 0x112049, 0xeba },
  250 + { 0x112149, 0xeba },
  251 + { 0x113049, 0xeba },
  252 + { 0x113149, 0xeba },
  253 + { 0x210049, 0xeba },
  254 + { 0x210149, 0xeba },
  255 + { 0x211049, 0xeba },
  256 + { 0x211149, 0xeba },
  257 + { 0x212049, 0xeba },
  258 + { 0x212149, 0xeba },
  259 + { 0x213049, 0xeba },
  260 + { 0x213149, 0xeba },
245 261 { 0x43, 0x63 },
246 262 { 0x1043, 0x63 },
247 263 { 0x2043, 0x63 },
... ... @@ -252,7 +268,6 @@
252 268 { 0x7043, 0x63 },
253 269 { 0x8043, 0x63 },
254 270 { 0x9043, 0x63 },
255   -
256 271 { 0x20018, 0x3 },
257 272 { 0x20075, 0x4 },
258 273 { 0x20050, 0x0 },
... ... @@ -260,8 +275,7 @@
260 275 { 0x120008, 0x64 },
261 276 { 0x220008, 0x19 },
262 277 { 0x20088, 0x9 },
263   -
264   - { 0x200b2, 0x1d4 },
  278 + { 0x200b2, 0xdc },
265 279 { 0x10043, 0x5a1 },
266 280 { 0x10143, 0x5a1 },
267 281 { 0x11043, 0x5a1 },
... ... @@ -270,7 +284,6 @@
270 284 { 0x12143, 0x5a1 },
271 285 { 0x13043, 0x5a1 },
272 286 { 0x13143, 0x5a1 },
273   -
274 287 { 0x1200b2, 0xdc },
275 288 { 0x110043, 0x5a1 },
276 289 { 0x110143, 0x5a1 },
... ... @@ -280,7 +293,6 @@
280 293 { 0x112143, 0x5a1 },
281 294 { 0x113043, 0x5a1 },
282 295 { 0x113143, 0x5a1 },
283   -
284 296 { 0x2200b2, 0xdc },
285 297 { 0x210043, 0x5a1 },
286 298 { 0x210143, 0x5a1 },
287 299  
288 300  
... ... @@ -290,15 +302,12 @@
290 302 { 0x212143, 0x5a1 },
291 303 { 0x213043, 0x5a1 },
292 304 { 0x213143, 0x5a1 },
293   -
294 305 { 0x200fa, 0x1 },
295 306 { 0x1200fa, 0x1 },
296 307 { 0x2200fa, 0x1 },
297   -
298 308 { 0x20019, 0x1 },
299 309 { 0x120019, 0x1 },
300 310 { 0x220019, 0x1 },
301   -
302 311 { 0x200f0, 0x660 },
303 312 { 0x200f1, 0x0 },
304 313 { 0x200f2, 0x4444 },
305 314  
306 315  
307 316  
308 317  
309 318  
... ... @@ -307,21 +316,20 @@
307 316 { 0x200f5, 0x0 },
308 317 { 0x200f6, 0x0 },
309 318 { 0x200f7, 0xf000 },
310   -
311 319 { 0x20025, 0x0 },
312   - { 0x2002d, LPDDR4_PHY_DMIPinPresent },
313   - { 0x12002d, LPDDR4_PHY_DMIPinPresent },
314   - { 0x22002d, LPDDR4_PHY_DMIPinPresent },
  320 + { 0x2002d, 0x0 },
  321 + { 0x12002d, 0x0 },
  322 + { 0x22002d, 0x0 },
315 323 { 0x200c7, 0x21 },
316   - { 0x200ca, 0x24 },
317 324 { 0x1200c7, 0x21 },
318   - { 0x1200ca, 0x24 },
319 325 { 0x2200c7, 0x21 },
  326 + { 0x200ca, 0x24 },
  327 + { 0x1200ca, 0x24 },
320 328 { 0x2200ca, 0x24 },
321 329 };
322 330  
323 331 /* ddr phy trained csr */
324   -struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
  332 +struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
325 333 { 0x200b2, 0x0 },
326 334 { 0x1200b2, 0x0 },
327 335 { 0x2200b2, 0x0 },
328 336  
329 337  
330 338  
331 339  
332 340  
333 341  
334 342  
335 343  
336 344  
337 345  
338 346  
339 347  
340 348  
341 349  
342 350  
343 351  
344 352  
345 353  
346 354  
347 355  
348 356  
349 357  
350 358  
351 359  
352 360  
353 361  
354 362  
355 363  
356 364  
357 365  
358 366  
359 367  
360 368  
361 369  
362 370  
363 371  
364 372  
365 373  
366 374  
367 375  
368 376  
369 377  
370 378  
371 379  
372 380  
373 381  
374 382  
375 383  
376 384  
377 385  
378 386  
379 387  
380 388  
381 389  
382 390  
383 391  
384 392  
385 393  
386 394  
387 395  
388 396  
389 397  
390 398  
391 399  
392 400  
393 401  
394 402  
395 403  
... ... @@ -1042,309 +1050,170 @@
1042 1050 { 0x13730, 0x0 },
1043 1051 { 0x13830, 0x0 },
1044 1052 };
1045   -
1046 1053 /* P0 message block paremeter for training firmware */
1047   -struct dram_cfg_param lpddr4_fsp0_cfg[] = {
  1054 +struct dram_cfg_param ddr_fsp0_cfg[] = {
1048 1055 { 0xd0000, 0x0 },
1049   - { 0x54000, 0x0 },
1050   - { 0x54001, 0x0 },
1051   - { 0x54002, 0x0 },
1052 1056 { 0x54003, 0xbb8 },
1053 1057 { 0x54004, 0x2 },
1054   - { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
1055   - { 0x54006, LPDDR4_PHY_VREF_VALUE },
1056   - { 0x54007, 0x0 },
  1058 + { 0x54005, 0x2228 },
  1059 + { 0x54006, 0x11 },
1057 1060 { 0x54008, 0x131f },
1058 1061 { 0x54009, 0xc8 },
1059   - { 0x5400a, 0x0 },
1060 1062 { 0x5400b, 0x2 },
1061   - { 0x5400c, 0x0 },
1062   - { 0x5400d, 0x0 },
1063   - { 0x5400e, 0x0 },
1064   - { 0x5400f, 0x0 },
1065   - { 0x54010, 0x0 },
1066   - { 0x54011, 0x0 },
1067   - { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
1068   - { 0x54013, 0x0 },
1069   - { 0x54014, 0x0 },
1070   - { 0x54015, 0x0 },
1071   - { 0x54016, 0x0 },
1072   - { 0x54017, 0x0 },
1073   - { 0x54018, 0x0 },
  1063 + { 0x5400d, 0x100 },
  1064 + { 0x54012, 0x110 },
1074 1065 { 0x54019, 0x2dd4 },
1075   - { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
  1066 + { 0x5401a, 0x31 },
1076 1067 { 0x5401b, 0x4d66 },
1077   - { 0x5401c, 0x4d08 },
1078   - { 0x5401d, 0x0 },
1079   - { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
  1068 + { 0x5401c, 0x4d00 },
  1069 + { 0x5401e, 0x16 },
1080 1070 { 0x5401f, 0x2dd4 },
1081   - { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
  1071 + { 0x54020, 0x31 },
1082 1072 { 0x54021, 0x4d66 },
1083   - { 0x54022, 0x4d08 },
1084   - { 0x54023, 0x0 },
1085   - { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
1086   - { 0x54025, 0x0 },
1087   - { 0x54026, 0x0 },
1088   - { 0x54027, 0x0 },
1089   - { 0x54028, 0x0 },
1090   - { 0x54029, 0x0 },
1091   - { 0x5402a, 0x0 },
  1073 + { 0x54022, 0x4d00 },
  1074 + { 0x54024, 0x16 },
1092 1075 { 0x5402b, 0x1000 },
1093   - { 0x5402c, LPDDR4_CS },
1094   - { 0x5402d, 0x0 },
1095   - { 0x5402e, 0x0 },
1096   - { 0x5402f, 0x0 },
1097   - { 0x54030, 0x0 },
1098   - { 0x54031, 0x0 },
  1076 + { 0x5402c, 0x1 },
1099 1077 { 0x54032, 0xd400 },
1100   - { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
  1078 + { 0x54033, 0x312d },
1101 1079 { 0x54034, 0x6600 },
1102   - { 0x54035, 0x84d },
  1080 + { 0x54035, 0x4d },
1103 1081 { 0x54036, 0x4d },
1104   - { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
  1082 + { 0x54037, 0x1600 },
1105 1083 { 0x54038, 0xd400 },
1106   - { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
  1084 + { 0x54039, 0x312d },
1107 1085 { 0x5403a, 0x6600 },
1108   - { 0x5403b, 0x84d },
  1086 + { 0x5403b, 0x4d },
1109 1087 { 0x5403c, 0x4d },
1110   - { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
1111   - { 0x5403e, 0x0 },
1112   - { 0x5403f, 0x0 },
1113   - { 0x54040, 0x0 },
1114   - { 0x54041, 0x0 },
1115   - { 0x54042, 0x0 },
1116   - { 0x54043, 0x0 },
1117   - { 0x54044, 0x0 },
  1088 + { 0x5403d, 0x1600 },
1118 1089 { 0xd0000, 0x1 },
1119 1090 };
1120 1091  
  1092 +
1121 1093 /* P1 message block paremeter for training firmware */
1122   -struct dram_cfg_param lpddr4_fsp1_cfg[] = {
  1094 +struct dram_cfg_param ddr_fsp1_cfg[] = {
1123 1095 { 0xd0000, 0x0 },
1124   - { 0x54000, 0x0 },
1125   - { 0x54001, 0x0 },
1126 1096 { 0x54002, 0x101 },
1127 1097 { 0x54003, 0x190 },
1128 1098 { 0x54004, 0x2 },
1129   - { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
1130   - { 0x54006, LPDDR4_PHY_VREF_VALUE },
1131   - { 0x54007, 0x0 },
  1099 + { 0x54005, 0x2228 },
  1100 + { 0x54006, 0x11 },
1132 1101 { 0x54008, 0x121f },
1133 1102 { 0x54009, 0xc8 },
1134   - { 0x5400a, 0x0 },
1135 1103 { 0x5400b, 0x2 },
1136   - { 0x5400c, 0x0 },
1137   - { 0x5400d, 0x0 },
1138   - { 0x5400e, 0x0 },
1139   - { 0x5400f, 0x0 },
1140   - { 0x54010, 0x0 },
1141   - { 0x54011, 0x0 },
1142   - { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
1143   - { 0x54013, 0x0 },
1144   - { 0x54014, 0x0 },
1145   - { 0x54015, 0x0 },
1146   - { 0x54016, 0x0 },
1147   - { 0x54017, 0x0 },
1148   - { 0x54018, 0x0 },
  1104 + { 0x5400d, 0x100 },
  1105 + { 0x54012, 0x110 },
1149 1106 { 0x54019, 0x84 },
1150   - { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
  1107 + { 0x5401a, 0x31 },
1151 1108 { 0x5401b, 0x4d66 },
1152   - { 0x5401c, 0x4d08 },
1153   - { 0x5401d, 0x0 },
1154   - { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
  1109 + { 0x5401c, 0x4d00 },
  1110 + { 0x5401e, 0x16 },
1155 1111 { 0x5401f, 0x84 },
1156   - { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
  1112 + { 0x54020, 0x31 },
1157 1113 { 0x54021, 0x4d66 },
1158   - { 0x54022, 0x4d08 },
1159   - { 0x54023, 0x0 },
1160   - { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
1161   - { 0x54025, 0x0 },
1162   - { 0x54026, 0x0 },
1163   - { 0x54027, 0x0 },
1164   - { 0x54028, 0x0 },
1165   - { 0x54029, 0x0 },
1166   - { 0x5402a, 0x0 },
  1114 + { 0x54022, 0x4d00 },
  1115 + { 0x54024, 0x16 },
1167 1116 { 0x5402b, 0x1000 },
1168   - { 0x5402c, LPDDR4_CS },
1169   - { 0x5402d, 0x0 },
1170   - { 0x5402e, 0x0 },
1171   - { 0x5402f, 0x0 },
1172   - { 0x54030, 0x0 },
1173   - { 0x54031, 0x0 },
  1117 + { 0x5402c, 0x1 },
1174 1118 { 0x54032, 0x8400 },
1175   - { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
  1119 + { 0x54033, 0x3100 },
1176 1120 { 0x54034, 0x6600 },
1177   - { 0x54035, 0x84d },
  1121 + { 0x54035, 0x4d },
1178 1122 { 0x54036, 0x4d },
1179   - { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
  1123 + { 0x54037, 0x1600 },
1180 1124 { 0x54038, 0x8400 },
1181   - { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
  1125 + { 0x54039, 0x3100 },
1182 1126 { 0x5403a, 0x6600 },
1183   - { 0x5403b, 0x84d },
  1127 + { 0x5403b, 0x4d },
1184 1128 { 0x5403c, 0x4d },
1185   - { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
1186   - { 0x5403e, 0x0 },
1187   - { 0x5403f, 0x0 },
1188   - { 0x54040, 0x0 },
1189   - { 0x54041, 0x0 },
1190   - { 0x54042, 0x0 },
1191   - { 0x54043, 0x0 },
1192   - { 0x54044, 0x0 },
  1129 + { 0x5403d, 0x1600 },
1193 1130 { 0xd0000, 0x1 },
1194 1131 };
1195 1132  
1196   -/* P1 message block paremeter for training firmware */
1197   -struct dram_cfg_param lpddr4_fsp2_cfg[] = {
  1133 +
  1134 +/* P2 message block paremeter for training firmware */
  1135 +struct dram_cfg_param ddr_fsp2_cfg[] = {
1198 1136 { 0xd0000, 0x0 },
1199   - { 0x54000, 0x0 },
1200   - { 0x54001, 0x0 },
1201 1137 { 0x54002, 0x102 },
1202 1138 { 0x54003, 0x64 },
1203 1139 { 0x54004, 0x2 },
1204   - { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
1205   - { 0x54006, LPDDR4_PHY_VREF_VALUE },
1206   - { 0x54007, 0x0 },
  1140 + { 0x54005, 0x2228 },
  1141 + { 0x54006, 0x11 },
1207 1142 { 0x54008, 0x121f },
1208 1143 { 0x54009, 0xc8 },
1209   - { 0x5400a, 0x0 },
1210 1144 { 0x5400b, 0x2 },
1211   - { 0x5400c, 0x0 },
1212   - { 0x5400d, 0x0 },
1213   - { 0x5400e, 0x0 },
1214   - { 0x5400f, 0x0 },
1215   - { 0x54010, 0x0 },
1216   - { 0x54011, 0x0 },
1217   - { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
1218   - { 0x54013, 0x0 },
1219   - { 0x54014, 0x0 },
1220   - { 0x54015, 0x0 },
1221   - { 0x54016, 0x0 },
1222   - { 0x54017, 0x0 },
1223   - { 0x54018, 0x0 },
  1145 + { 0x5400d, 0x100 },
  1146 + { 0x54012, 0x110 },
1224 1147 { 0x54019, 0x84 },
1225   - { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
  1148 + { 0x5401a, 0x31 },
1226 1149 { 0x5401b, 0x4d66 },
1227   - { 0x5401c, 0x4d08 },
1228   - { 0x5401d, 0x0 },
1229   - { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
  1150 + { 0x5401c, 0x4d00 },
  1151 + { 0x5401e, 0x16 },
1230 1152 { 0x5401f, 0x84 },
1231   - { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
  1153 + { 0x54020, 0x31 },
1232 1154 { 0x54021, 0x4d66 },
1233   - { 0x54022, 0x4d08 },
1234   - { 0x54023, 0x0 },
1235   - { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
1236   - { 0x54025, 0x0 },
1237   - { 0x54026, 0x0 },
1238   - { 0x54027, 0x0 },
1239   - { 0x54028, 0x0 },
1240   - { 0x54029, 0x0 },
1241   - { 0x5402a, 0x0 },
  1155 + { 0x54022, 0x4d00 },
  1156 + { 0x54024, 0x16 },
1242 1157 { 0x5402b, 0x1000 },
1243   - { 0x5402c, LPDDR4_CS },
1244   - { 0x5402d, 0x0 },
1245   - { 0x5402e, 0x0 },
1246   - { 0x5402f, 0x0 },
1247   - { 0x54030, 0x0 },
1248   - { 0x54031, 0x0 },
  1158 + { 0x5402c, 0x1 },
1249 1159 { 0x54032, 0x8400 },
1250   - { 0x54033, (LPDDR4_MR3 << 8) | (0x3100&0xff) },
  1160 + { 0x54033, 0x3100 },
1251 1161 { 0x54034, 0x6600 },
1252   - { 0x54035, 0x84d },
  1162 + { 0x54035, 0x4d },
1253 1163 { 0x54036, 0x4d },
1254   - { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
  1164 + { 0x54037, 0x1600 },
1255 1165 { 0x54038, 0x8400 },
1256   - { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
  1166 + { 0x54039, 0x3100 },
1257 1167 { 0x5403a, 0x6600 },
1258   - { 0x5403b, 0x84d },
  1168 + { 0x5403b, 0x4d },
1259 1169 { 0x5403c, 0x4d },
1260   - { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
1261   - { 0x5403e, 0x0 },
1262   - { 0x5403f, 0x0 },
1263   - { 0x54040, 0x0 },
1264   - { 0x54041, 0x0 },
1265   - { 0x54042, 0x0 },
1266   - { 0x54043, 0x0 },
1267   - { 0x54044, 0x0 },
  1170 + { 0x5403d, 0x1600 },
1268 1171 { 0xd0000, 0x1 },
1269 1172 };
1270 1173  
  1174 +
1271 1175 /* P0 2D message block paremeter for training firmware */
1272   -struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
  1176 +struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
1273 1177 { 0xd0000, 0x0 },
1274   - { 0x54000, 0x0 },
1275   - { 0x54001, 0x0 },
1276   - { 0x54002, 0x0 },
1277 1178 { 0x54003, 0xbb8 },
1278 1179 { 0x54004, 0x2 },
1279   - { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
1280   - { 0x54006, LPDDR4_PHY_VREF_VALUE },
1281   - { 0x54007, 0x0 },
  1180 + { 0x54005, 0x2228 },
  1181 + { 0x54006, 0x11 },
1282 1182 { 0x54008, 0x61 },
1283 1183 { 0x54009, 0xc8 },
1284   - { 0x5400a, 0x0 },
1285 1184 { 0x5400b, 0x2 },
1286   - { 0x5400c, 0x0 },
1287   - { 0x5400d, 0x0 },
1288   - { 0x5400e, 0x0 },
1289 1185 { 0x5400f, 0x100 },
1290 1186 { 0x54010, 0x1f7f },
1291   - { 0x54011, 0x0 },
1292   - { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
1293   - { 0x54013, 0x0 },
1294   - { 0x54014, 0x0 },
1295   - { 0x54015, 0x0 },
1296   - { 0x54016, 0x0 },
1297   - { 0x54017, 0x0 },
1298   - { 0x54018, 0x0 },
  1187 + { 0x54012, 0x110 },
1299 1188 { 0x54019, 0x2dd4 },
1300   - { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
  1189 + { 0x5401a, 0x31 },
1301 1190 { 0x5401b, 0x4d66 },
1302   - { 0x5401c, 0x4d08 },
1303   - { 0x5401d, 0x0 },
1304   - { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
  1191 + { 0x5401c, 0x4d00 },
  1192 + { 0x5401e, 0x16 },
1305 1193 { 0x5401f, 0x2dd4 },
1306   - { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
  1194 + { 0x54020, 0x31 },
1307 1195 { 0x54021, 0x4d66 },
1308   - { 0x54022, 0x4d08 },
1309   - { 0x54023, 0x0 },
1310   - { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
1311   - { 0x54025, 0x0 },
1312   - { 0x54026, 0x0 },
1313   - { 0x54027, 0x0 },
1314   - { 0x54028, 0x0 },
1315   - { 0x54029, 0x0 },
1316   - { 0x5402a, 0x0 },
  1196 + { 0x54022, 0x4d00 },
  1197 + { 0x54024, 0x16 },
1317 1198 { 0x5402b, 0x1000 },
1318   - { 0x5402c, LPDDR4_CS },
1319   - { 0x5402d, 0x0 },
1320   - { 0x5402e, 0x0 },
1321   - { 0x5402f, 0x0 },
1322   - { 0x54030, 0x0 },
1323   - { 0x54031, 0x0 },
  1199 + { 0x5402c, 0x1 },
1324 1200 { 0x54032, 0xd400 },
1325   - { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
  1201 + { 0x54033, 0x312d },
1326 1202 { 0x54034, 0x6600 },
1327   - { 0x54035, 0x84d },
  1203 + { 0x54035, 0x4d },
1328 1204 { 0x54036, 0x4d },
1329   - { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
  1205 + { 0x54037, 0x1600 },
1330 1206 { 0x54038, 0xd400 },
1331   - { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
  1207 + { 0x54039, 0x312d },
1332 1208 { 0x5403a, 0x6600 },
1333   - { 0x5403b, 0x84d },
  1209 + { 0x5403b, 0x4d },
1334 1210 { 0x5403c, 0x4d },
1335   - { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
1336   - { 0x5403e, 0x0 },
1337   - { 0x5403f, 0x0 },
1338   - { 0x54040, 0x0 },
1339   - { 0x54041, 0x0 },
1340   - { 0x54042, 0x0 },
1341   - { 0x54043, 0x0 },
1342   - { 0x54044, 0x0 },
  1211 + { 0x5403d, 0x1600 },
1343 1212 { 0xd0000, 0x1 },
1344 1213 };
1345 1214  
1346 1215 /* DRAM PHY init engine image */
1347   -struct dram_cfg_param lpddr4_phy_pie[] = {
  1216 +struct dram_cfg_param ddr_phy_pie[] = {
1348 1217 { 0xd0000, 0x0 },
1349 1218 { 0x90000, 0x10 },
1350 1219 { 0x90001, 0x400 },
... ... @@ -1855,6 +1724,10 @@
1855 1724 { 0x90013, 0x6152 },
1856 1725 { 0x20010, 0x5a },
1857 1726 { 0x20011, 0x3 },
  1727 + { 0x120010, 0x5a },
  1728 + { 0x120011, 0x3 },
  1729 + { 0x220010, 0x5a },
  1730 + { 0x220011, 0x3 },
1858 1731 { 0x40080, 0xe0 },
1859 1732 { 0x40081, 0x12 },
1860 1733 { 0x40082, 0xe0 },
1861 1734  
1862 1735  
1863 1736  
1864 1737  
1865 1738  
1866 1739  
1867 1740  
1868 1741  
1869 1742  
... ... @@ -1932,51 +1805,52 @@
1932 1805 { 0x138b4, 0x1 },
1933 1806 { 0x2003a, 0x2 },
1934 1807 { 0xc0080, 0x2 },
1935   - { 0xd0000, 0x1 },
  1808 + { 0xd0000, 0x1 }
1936 1809 };
1937 1810  
1938   -struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
  1811 +struct dram_fsp_msg ddr_dram_fsp_msg[] = {
1939 1812 {
1940 1813 /* P0 3000mts 1D */
1941 1814 .drate = 3000,
1942 1815 .fw_type = FW_1D_IMAGE,
1943   - .fsp_cfg = lpddr4_fsp0_cfg,
1944   - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
  1816 + .fsp_cfg = ddr_fsp0_cfg,
  1817 + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
1945 1818 },
1946 1819 {
1947   - /* P0 3000mts 2D */
1948   - .drate = 3000,
1949   - .fw_type = FW_2D_IMAGE,
1950   - .fsp_cfg = lpddr4_fsp0_2d_cfg,
1951   - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
1952   - },
1953   - {
1954 1820 /* P1 400mts 1D */
1955 1821 .drate = 400,
1956 1822 .fw_type = FW_1D_IMAGE,
1957   - .fsp_cfg = lpddr4_fsp1_cfg,
1958   - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
  1823 + .fsp_cfg = ddr_fsp1_cfg,
  1824 + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
1959 1825 },
1960 1826 {
1961   - /* P1 100mts 1D */
  1827 + /* P2 100mts 1D */
1962 1828 .drate = 100,
1963 1829 .fw_type = FW_1D_IMAGE,
1964   - .fsp_cfg = lpddr4_fsp2_cfg,
1965   - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
  1830 + .fsp_cfg = ddr_fsp2_cfg,
  1831 + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
1966 1832 },
  1833 + {
  1834 + /* P0 3000mts 2D */
  1835 + .drate = 3000,
  1836 + .fw_type = FW_2D_IMAGE,
  1837 + .fsp_cfg = ddr_fsp0_2d_cfg,
  1838 + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
  1839 + },
1967 1840 };
1968 1841  
1969   -/* lpddr4 timing config params on EVK board */
  1842 +/* ddr timing config params */
1970 1843 struct dram_timing_info dram_timing = {
1971   - .ddrc_cfg = lpddr4_ddrc_cfg,
1972   - .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
1973   - .ddrphy_cfg = lpddr4_ddrphy_cfg,
1974   - .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
1975   - .fsp_msg = lpddr4_dram_fsp_msg,
1976   - .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
1977   - .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr,
1978   - .ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr),
1979   - .ddrphy_pie = lpddr4_phy_pie,
1980   - .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
  1844 + .ddrc_cfg = ddr_ddrc_cfg,
  1845 + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
  1846 + .ddrphy_cfg = ddr_ddrphy_cfg,
  1847 + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
  1848 + .fsp_msg = ddr_dram_fsp_msg,
  1849 + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
  1850 + .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
  1851 + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
  1852 + .ddrphy_pie = ddr_phy_pie,
  1853 + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
  1854 + .fsp_table = { 3000, 400, 100, },
1981 1855 };