Commit 13022d852d5c233894fabb62279a2ae9e0355638
Committed by
Marek Vasut
Marek Vasut
1 parent
202936395e
Exists in
v2017.01-smarct4x
and in
25 other branches
arm: socfpga: de0-nano-soc: Adding handoff for SDRAM ctrlcfg.extratime1
Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Showing 1 changed file with 3 additions and 0 deletions Side-by-side Diff
board/terasic/de0-nano-soc/qts/sdram_config.h
| ... | ... | @@ -42,6 +42,9 @@ |
| 42 | 42 | #define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 |
| 43 | 43 | #define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 |
| 44 | 44 | #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 |
| 45 | +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 | |
| 46 | +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 | |
| 47 | +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 | |
| 45 | 48 | #define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 |
| 46 | 49 | #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 |
| 47 | 50 | #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 |