* Patch by Pierre Aubert, 26 Feb 2004

add IDE support for MPC5200 * Patch by Masami Komiya, 26 Feb 2004: add autoload via NFS * Patch by Stephen Williams Use of CONFIG_SERIAL_SOFTWARE_FIFO in board.c consistent with uses elsewhere in the source.

* Patch by Pierre Aubert, 26 Feb 2004
add IDE support for MPC5200 * Patch by Masami Komiya, 26 Feb 2004: add autoload via NFS * Patch by Stephen Williams Use of CONFIG_SERIAL_SOFTWARE_FIFO in board.c consistent with uses elsewhere in the source.
wdenk
1 parent 11dadd547c
Showing 12 changed files with 211 additions and 22 deletions Side-by-side Diff
CHANGELOG
board/ns9750dev/led.c
common/cmd_ide.c
cpu/mpc5xxx/Makefile
cpu/mpc5xxx/ide.c
include/configs/IceCube.h
include/configs/eXalion.h
include/mpc5xxx.h
lib_i386/board.c
lib_m68k/board.c
lib_ppc/board.c
net/bootp.c
@@ -2,6 +2,16 @@
 Changes for U-Boot 1.0.2:
 ======================================================================
  
+* Patch by Pierre Aubert, 26 Feb 2004
+  add IDE support for MPC5200
+
+* Patch by Masami Komiya, 26 Feb 2004:
+  add autoload via NFS
+
+* Patch by Stephen Williams
+  Use of CONFIG_SERIAL_SOFTWARE_FIFO in board.c consistent with uses
+  elsewhere in the source.
+
 * Patch by Steven Scholz, 25 Feb 2004:
   - Timeouts in FPGA code should be based on CFG_HZ
   - Minor cleanup in code for Altera FPGA ACEX1K
@@ -15,7 +25,7 @@
 * Patch by Markus Pietrek, 24 Feb 2004:
   NS9750 DevBoard added
  
-* Patch by Pierre AUBERT, 24 Feb 2004
+* Patch by Pierre Aubert, 24 Feb 2004
   add USB support for MPC5200
  
 * Patch by Steven Scholz, 24 Feb 2004:
@@ -23,7 +23,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
- *  
+ *
  ***********************************************************************/
  
 #ifdef CONFIG_STATUS_LED
@@ -37,6 +37,9 @@
 #ifdef CONFIG_8xx
 # include <mpc8xx.h>
 #endif
+#ifdef CONFIG_MPC5xxx
+#include <mpc5xxx.h>
+#endif
 #include <ide.h>
 #include <ata.h>
 #ifdef CONFIG_STATUS_LED
@@ -27,8 +27,8 @@
  
 START	= start.o
 ASOBJS	= io.o firmware_sc_task_bestcomm.impl.o firmware_sc_task.impl.o
-OBJS	= i2c.o traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o \
-	  loadtask.o fec.o pci_mpc5200.o usb_ohci.o
+OBJS	= i2c.o traps.o cpu.o cpu_init.o fec.o ide.o interrupts.o \
+	  loadtask.o pci_mpc5200.o serial.o speed.o usb_ohci.o
  
 all:	.depend $(START) $(ASOBJS) $(LIB)
  
+/*
+ * (C) Copyright 2004
+ * Pierre AUBERT, Staubli Faverges, <p.aubert@staubli.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Init is derived from Linux code.
+ */
+#include <common.h>
+
+#ifdef CFG_CMD_IDE
+#include <mpc5xxx.h>
+
+#define CALC_TIMING(t) (t + period - 1) / period
+
+#define GPIO_PSC1_4	0x01000000ul
+
+int ide_preinit (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	long period, t0, t1, t2_8, t2_16, t4, ta;
+	vu_long reg;
+	struct mpc5xxx_sdma *psdma = (struct mpc5xxx_sdma *) MPC5XXX_SDMA;
+
+	reg = *(vu_long *) MPC5XXX_GPS_PORT_CONFIG;
+	reg = (reg & ~0x03000000ul) | 0x01000000ul;
+	*(vu_long *) MPC5XXX_GPS_PORT_CONFIG = reg;
+
+	/* All sample codes do that... */
+	*(vu_long *) MPC5XXX_ATA_SHARE_COUNT = 0;
+
+	/* Configure and reset host */
+	*(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY |
+		MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR;
+	udelay (10);
+	*(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY;
+
+	/* Disable prefetch on Commbus */
+	psdma->PtdCntrl |= 1;
+
+	/* Init timings : we use PIO mode 0 timings */
+	period = 1000000000 / gd->ipb_clk;	/* period in ns */
+
+	t0 = CALC_TIMING (600);
+	t2_8 = CALC_TIMING (290);
+	t2_16 = CALC_TIMING (165);
+	reg = (t0 << 24) | (t2_8 << 16) | (t2_16 << 8);
+	*(vu_long *) MPC5XXX_ATA_PIO1 = reg;
+
+	t4 = CALC_TIMING (30);
+	t1 = CALC_TIMING (70);
+	ta = CALC_TIMING (35);
+	reg = (t4 << 24) | (t1 << 16) | (ta << 8);
+
+	*(vu_long *) MPC5XXX_ATA_PIO2 = reg;
+
+#if defined (CONFIG_ICECUBE) && defined (CONFIG_IDE_RESET)
+	/* Configure PSC1_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+#endif /* defined (CONFIG_ICECUBE) && defined (CONFIG_IDE_RESET) */
+
+	return (0);
+}
+
+#if defined (CONFIG_ICECUBE) && defined (CONFIG_IDE_RESET)
+void ide_set_reset (int idereset)
+{
+	if (idereset) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
+	} else {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
+	}
+}
+#endif /* defined (CONFIG_ICECUBE) && defined (CONFIG_IDE_RESET) */
+#endif /* CFG_CMD_IDE */
@@ -81,6 +81,10 @@
  
 #endif
  
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
 /* USB */
 #if 1
 #define CONFIG_USB_OHCI
@@ -94,8 +98,12 @@
 /*
  * Supported commands
  */
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | ADD_PCI_CMD | \
-				 CFG_CMD_I2C | CFG_CMD_EEPROM | \
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL	| \
+				 CFG_CMD_EEPROM	| \
+				 CFG_CMD_FAT	| \
+				 CFG_CMD_I2C	| \
+				 CFG_CMD_IDE	| \
+				 ADD_PCI_CMD	| \
 				 ADD_USB_CMD)
  
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@@ -292,6 +300,38 @@
 #define CFG_CS_DEADCYCLE	0x33333333
  
 #define CFG_RESET_ADDRESS	0xff000000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+
+#define	CONFIG_IDE_RESET		/* reset for ide supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	(0x005c)
+
+/* Interval between registers                                                */
+#define CFG_ATA_STRIDE          4
  
 #endif /* __CONFIG_H */
@@ -50,13 +50,13 @@
 #error #### Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
 #endif
 /* older kernels need clock in MHz newer in Hz */
-					/* #define CONFIG_CLOCKS_IN_MHZ 1 *//* clocks passsed to Linux in MHz	    */
+					/* #define CONFIG_CLOCKS_IN_MHZ 1 */ /* clocks passsed to Linux in MHz	    */
 #undef CONFIG_CLOCKS_IN_MHZ
  
 #define CONFIG_BOOTDELAY	10
  
  
-						    /*#define CONFIG_DRAM_SPEED	      66   *//* MHz			     */
+						    /*#define CONFIG_DRAM_SPEED	      66   */ /* MHz			     */
  
 #define CONFIG_COMMANDS		(   CONFIG_CMD_DFL  | \
 				    CFG_CMD_FLASH   | \
@@ -230,7 +230,7 @@
 #define CONFIG_SYS_CLK_FREQ	33333333	/* external frequency to pll	*/
 #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  2	/* for MPC8240 only		*/
  
-				       /*#define CONFIG_133MHZ_DRAM	 1 *//* For 133 MHZ DRAM only !!!!!!!!!!!    */
+				       /*#define CONFIG_133MHZ_DRAM	 1 */ /* For 133 MHZ DRAM only !!!!!!!!!!!    */
  
 #if defined (CONFIG_MPC8245)
 /* Bit-field values for PMCR2.							*/
@@ -89,6 +89,7 @@
 #define MPC5XXX_ICTL		(CFG_MBAR + 0x0500)
 #define MPC5XXX_GPT		(CFG_MBAR + 0x0600)
 #define MPC5XXX_GPIO		(CFG_MBAR + 0x0b00)
+#define MPC5XXX_WU_GPIO         (CFG_MBAR + 0x0c00)
 #define MPC5XXX_PCI		(CFG_MBAR + 0x0d00)
 #define MPC5XXX_USB		(CFG_MBAR + 0x1000)
 #define MPC5XXX_SDMA		(CFG_MBAR + 0x1200)
@@ -108,6 +109,7 @@
 #endif
  
 #define	MPC5XXX_FEC		(CFG_MBAR + 0x3000)
+#define MPC5XXX_ATA             (CFG_MBAR + 0x3A00)
  
 #define MPC5XXX_I2C1		(CFG_MBAR + 0x3D00)
 #define MPC5XXX_I2C2		(CFG_MBAR + 0x3D40)
@@ -163,6 +165,12 @@
 /* GPIO registers */
 #define MPC5XXX_GPS_PORT_CONFIG	(MPC5XXX_GPIO + 0x0000)
  
+/* WakeUp GPIO registers */
+#define MPC5XXX_WU_GPIO_ENABLE  (MPC5XXX_WU_GPIO + 0x0000)
+#define MPC5XXX_WU_GPIO_ODE     (MPC5XXX_WU_GPIO + 0x0004)
+#define MPC5XXX_WU_GPIO_DIR     (MPC5XXX_WU_GPIO + 0x0008)
+#define MPC5XXX_WU_GPIO_DATA    (MPC5XXX_WU_GPIO + 0x000c)
+
 /* PCI registers */
 #define MPC5XXX_PCI_CMD		(MPC5XXX_PCI + 0x04)
 #define MPC5XXX_PCI_CFG		(MPC5XXX_PCI + 0x0c)
@@ -209,6 +217,12 @@
 #define MPC5XXX_GPT0_ENABLE		(MPC5XXX_GPT + 0x0)
 #define MPC5XXX_GPT0_COUNTER		(MPC5XXX_GPT + 0x4)
  
+/* ATA registers */
+#define MPC5XXX_ATA_HOST_CONFIG         (MPC5XXX_ATA + 0x0000)
+#define MPC5XXX_ATA_PIO1                (MPC5XXX_ATA + 0x0008)
+#define MPC5XXX_ATA_PIO2                (MPC5XXX_ATA + 0x000C)
+#define MPC5XXX_ATA_SHARE_COUNT         (MPC5XXX_ATA + 0x002C)
+
 /* I2Cn control register bits */
 #define I2C_EN		0x80
 #define I2C_IEN		0x40
@@ -286,6 +300,15 @@
 #define PSC_MODE_ONE_STOP_5_BITS	0x00
 #define PSC_MODE_ONE_STOP		0x07
 #define PSC_MODE_TWO_STOP		0x0f
+
+/* ATA config fields */
+#define MPC5xxx_ATA_HOSTCONF_SMR	0x80000000UL	/* State machine
+							   reset */
+#define MPC5xxx_ATA_HOSTCONF_FR		0x40000000UL	/* FIFO Reset */
+#define MPC5xxx_ATA_HOSTCONF_IE		0x02000000UL	/* Enable interrupt
+							   in PIO */
+#define MPC5xxx_ATA_HOSTCONF_IORDY	0x01000000UL	/* Drive supports
+							   IORDY protocol */
  
 #ifndef __ASSEMBLY__
 struct mpc5xxx_psc {
@@ -343,7 +343,7 @@
 	/* Must happen after interrupts are initialized since
 	 * an irq handler gets installed
 	 */
-#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
+#if CONFIG_SERIAL_SOFTWARE_FIFO
 	serial_buffered_init();
 #endif
  
@@ -577,7 +577,7 @@
 	 */
 	timer_init();
  
-#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
+#if CONFIG_SERIAL_SOFTWARE_FIFO
 	serial_buffered_init();
 #endif
  
@@ -874,7 +874,7 @@
 	/* Must happen after interrupts are initialized since
 	 * an irq handler gets installed
 	 */
-#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
+#if CONFIG_SERIAL_SOFTWARE_FIFO
 	serial_buffered_init();
 #endif
  
@@ -331,13 +331,21 @@
  
 	debug ("Got good BOOTP\n");
  
-	if (((s = getenv("autoload")) != NULL) && (*s == 'n')) {
-		/*
-		 * Just use BOOTP to configure system;
-		 * Do not use TFTP to load the bootfile.
-		 */
-		NetState = NETLOOP_SUCCESS;
-		return;
+	if ((s = getenv("autoload")) != NULL) {
+		if (*s == 'n') {
+			/*
+			 * Just use BOOTP to configure system;
+			 * Do not use TFTP to load the bootfile.
+			 */
+			NetState = NETLOOP_SUCCESS;
+			return;
+		} else if (strcmp(s, "NFS") == 0) {
+			/*
+			 * Use NFS to load the bootfile.
+			 */
+			NfsStart();
+			return;
+		}
 	}
  
 	TftpStart();
@@ -881,9 +889,21 @@
 			printf("\n");
  
 			/* Obey the 'autoload' setting */
-			if (((s = getenv("autoload")) != NULL) && (*s == 'n')) {
-				NetState = NETLOOP_SUCCESS;
-				return;
+			if ((s = getenv("autoload")) != NULL) {
+				if (*s == 'n') {
+					/*
+					 * Just use BOOTP to configure system;
+					 * Do not use TFTP to load the bootfile.
+					 */
+					NetState = NETLOOP_SUCCESS;
+					return;
+				} else if (strcmp(s, "NFS") == 0) {
+					/*
+					 * Use NFS to load the bootfile.
+					 */
+					NfsStart();
+					return;
+				}
 			}
 			TftpStart();
 			return;
...	...	@@ -2,6 +2,16 @@
2	2	Changes for U-Boot 1.0.2:
3	3	======================================================================
4	4
	5	+* Patch by Pierre Aubert, 26 Feb 2004
	6	+ add IDE support for MPC5200
	7	+
	8	+* Patch by Masami Komiya, 26 Feb 2004:
	9	+ add autoload via NFS
	10	+
	11	+* Patch by Stephen Williams
	12	+ Use of CONFIG_SERIAL_SOFTWARE_FIFO in board.c consistent with uses
	13	+ elsewhere in the source.
	14	+
5	15	* Patch by Steven Scholz, 25 Feb 2004:
6	16	- Timeouts in FPGA code should be based on CFG_HZ
7	17	- Minor cleanup in code for Altera FPGA ACEX1K
...	...	@@ -15,7 +25,7 @@
15	25	* Patch by Markus Pietrek, 24 Feb 2004:
16	26	NS9750 DevBoard added
17	27
18		-* Patch by Pierre AUBERT, 24 Feb 2004
	28	+* Patch by Pierre Aubert, 24 Feb 2004
19	29	add USB support for MPC5200
20	30
21	31	* Patch by Steven Scholz, 24 Feb 2004:
...	...	@@ -23,7 +23,7 @@
23	23	* along with this program; if not, write to the Free Software
24	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25	25	* MA 02111-1307 USA
26		- *
	26	+ *
27	27	***********************************************************************/
28	28
29	29	#ifdef CONFIG_STATUS_LED
...	...	@@ -37,6 +37,9 @@
37	37	#ifdef CONFIG_8xx
38	38	# include <mpc8xx.h>
39	39	#endif
	40	+#ifdef CONFIG_MPC5xxx
	41	+#include <mpc5xxx.h>
	42	+#endif
40	43	#include <ide.h>
41	44	#include <ata.h>
42	45	#ifdef CONFIG_STATUS_LED
...	...	@@ -27,8 +27,8 @@
27	27
28	28	START = start.o
29	29	ASOBJS = io.o firmware_sc_task_bestcomm.impl.o firmware_sc_task.impl.o
30		-OBJS = i2c.o traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o \
31		- loadtask.o fec.o pci_mpc5200.o usb_ohci.o
	30	+OBJS = i2c.o traps.o cpu.o cpu_init.o fec.o ide.o interrupts.o \
	31	+ loadtask.o pci_mpc5200.o serial.o speed.o usb_ohci.o
32	32
33	33	all: .depend $(START) $(ASOBJS) $(LIB)
34	34
	1	+/*
	2	+ * (C) Copyright 2004
	3	+ * Pierre AUBERT, Staubli Faverges, <p.aubert@staubli.com>
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ *
	23	+ * Init is derived from Linux code.
	24	+ */
	25	+#include <common.h>
	26	+
	27	+#ifdef CFG_CMD_IDE
	28	+#include <mpc5xxx.h>
	29	+
	30	+#define CALC_TIMING(t) (t + period - 1) / period
	31	+
	32	+#define GPIO_PSC1_4 0x01000000ul
	33	+
	34	+int ide_preinit (void)
	35	+{
	36	+ DECLARE_GLOBAL_DATA_PTR;
	37	+ long period, t0, t1, t2_8, t2_16, t4, ta;
	38	+ vu_long reg;
	39	+ struct mpc5xxx_sdma psdma = (struct mpc5xxx_sdma ) MPC5XXX_SDMA;
	40	+
	41	+ reg = (vu_long ) MPC5XXX_GPS_PORT_CONFIG;
	42	+ reg = (reg & ~0x03000000ul) \| 0x01000000ul;
	43	+ (vu_long ) MPC5XXX_GPS_PORT_CONFIG = reg;
	44	+
	45	+ /* All sample codes do that... */
	46	+ (vu_long ) MPC5XXX_ATA_SHARE_COUNT = 0;
	47	+
	48	+ /* Configure and reset host */
	49	+ (vu_long ) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY \|
	50	+ MPC5xxx_ATA_HOSTCONF_SMR \| MPC5xxx_ATA_HOSTCONF_FR;
	51	+ udelay (10);
	52	+ (vu_long ) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY;
	53	+
	54	+ /* Disable prefetch on Commbus */
	55	+ psdma->PtdCntrl \|= 1;
	56	+
	57	+ /* Init timings : we use PIO mode 0 timings */
	58	+ period = 1000000000 / gd->ipb_clk; /* period in ns */
	59	+
	60	+ t0 = CALC_TIMING (600);
	61	+ t2_8 = CALC_TIMING (290);
	62	+ t2_16 = CALC_TIMING (165);
	63	+ reg = (t0 << 24) \| (t2_8 << 16) \| (t2_16 << 8);
	64	+ (vu_long ) MPC5XXX_ATA_PIO1 = reg;
	65	+
	66	+ t4 = CALC_TIMING (30);
	67	+ t1 = CALC_TIMING (70);
	68	+ ta = CALC_TIMING (35);
	69	+ reg = (t4 << 24) \| (t1 << 16) \| (ta << 8);
	70	+
	71	+ (vu_long ) MPC5XXX_ATA_PIO2 = reg;
	72	+
	73	+#if defined (CONFIG_ICECUBE) && defined (CONFIG_IDE_RESET)
	74	+ /* Configure PSC1_4 as GPIO output for ATA reset */
	75	+ (vu_long ) MPC5XXX_WU_GPIO_DATA \|= GPIO_PSC1_4;
	76	+ (vu_long ) MPC5XXX_WU_GPIO_ENABLE \|= GPIO_PSC1_4;
	77	+ (vu_long ) MPC5XXX_WU_GPIO_DIR \|= GPIO_PSC1_4;
	78	+#endif /* defined (CONFIG_ICECUBE) && defined (CONFIG_IDE_RESET) */
	79	+
	80	+ return (0);
	81	+}
	82	+
	83	+#if defined (CONFIG_ICECUBE) && defined (CONFIG_IDE_RESET)
	84	+void ide_set_reset (int idereset)
	85	+{
	86	+ if (idereset) {
	87	+ (vu_long ) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
	88	+ } else {
	89	+ (vu_long ) MPC5XXX_WU_GPIO_DATA \|= GPIO_PSC1_4;
	90	+ }
	91	+}
	92	+#endif /* defined (CONFIG_ICECUBE) && defined (CONFIG_IDE_RESET) */
	93	+#endif /* CFG_CMD_IDE */
...	...	@@ -81,6 +81,10 @@
81	81
82	82	#endif
83	83
	84	+/* Partitions */
	85	+#define CONFIG_MAC_PARTITION
	86	+#define CONFIG_DOS_PARTITION
	87	+
84	88	/* USB */
85	89	#if 1
86	90	#define CONFIG_USB_OHCI
...	...	@@ -94,8 +98,12 @@
94	98	/*
95	99	* Supported commands
96	100	*/
97		-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| ADD_PCI_CMD \| \
98		- CFG_CMD_I2C \| CFG_CMD_EEPROM \| \
	101	+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
	102	+ CFG_CMD_EEPROM \| \
	103	+ CFG_CMD_FAT \| \
	104	+ CFG_CMD_I2C \| \
	105	+ CFG_CMD_IDE \| \
	106	+ ADD_PCI_CMD \| \
99	107	ADD_USB_CMD)
100	108
101	109	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
...	...	@@ -292,6 +300,38 @@
292	300	#define CFG_CS_DEADCYCLE 0x33333333
293	301
294	302	#define CFG_RESET_ADDRESS 0xff000000
	303	+
	304	+/*-----------------------------------------------------------------------
	305	+ * IDE/ATA stuff Supports IDE harddisk
	306	+ *-----------------------------------------------------------------------
	307	+ */
	308	+
	309	+#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	310	+
	311	+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	312	+#undef CONFIG_IDE_LED /* LED for ide not supported */
	313	+
	314	+#define CONFIG_IDE_RESET /* reset for ide supported */
	315	+#define CONFIG_IDE_PREINIT
	316	+
	317	+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
	318	+#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
	319	+
	320	+#define CFG_ATA_IDE0_OFFSET 0x0000
	321	+
	322	+#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
	323	+
	324	+/* Offset for data I/O */
	325	+#define CFG_ATA_DATA_OFFSET (0x0060)
	326	+
	327	+/* Offset for normal register accesses */
	328	+#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
	329	+
	330	+/* Offset for alternate registers */
	331	+#define CFG_ATA_ALT_OFFSET (0x005c)
	332	+
	333	+/* Interval between registers */
	334	+#define CFG_ATA_STRIDE 4
295	335
296	336	#endif /* __CONFIG_H */
...	...	@@ -50,13 +50,13 @@
50	50	#error #### Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
51	51	#endif
52	52	/* older kernels need clock in MHz newer in Hz */
53		- /* #define CONFIG_CLOCKS_IN_MHZ 1 // clocks passsed to Linux in MHz */
	53	+ /* #define CONFIG_CLOCKS_IN_MHZ 1 / / clocks passsed to Linux in MHz */
54	54	#undef CONFIG_CLOCKS_IN_MHZ
55	55
56	56	#define CONFIG_BOOTDELAY 10
57	57
58	58
59		- /#define CONFIG_DRAM_SPEED 66 //* MHz */
	59	+ /#define CONFIG_DRAM_SPEED 66 / /* MHz */
60	60
61	61	#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \| \
62	62	CFG_CMD_FLASH \| \
...	...	@@ -230,7 +230,7 @@
230	230	#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
231	231	#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2 /* for MPC8240 only */
232	232
233		- /#define CONFIG_133MHZ_DRAM 1 //* For 133 MHZ DRAM only !!!!!!!!!!! */
	233	+ /#define CONFIG_133MHZ_DRAM 1 / /* For 133 MHZ DRAM only !!!!!!!!!!! */
234	234
235	235	#if defined (CONFIG_MPC8245)
236	236	/* Bit-field values for PMCR2. */
...	...	@@ -89,6 +89,7 @@
89	89	#define MPC5XXX_ICTL (CFG_MBAR + 0x0500)
90	90	#define MPC5XXX_GPT (CFG_MBAR + 0x0600)
91	91	#define MPC5XXX_GPIO (CFG_MBAR + 0x0b00)
	92	+#define MPC5XXX_WU_GPIO (CFG_MBAR + 0x0c00)
92	93	#define MPC5XXX_PCI (CFG_MBAR + 0x0d00)
93	94	#define MPC5XXX_USB (CFG_MBAR + 0x1000)
94	95	#define MPC5XXX_SDMA (CFG_MBAR + 0x1200)
...	...	@@ -108,6 +109,7 @@
108	109	#endif
109	110
110	111	#define MPC5XXX_FEC (CFG_MBAR + 0x3000)
	112	+#define MPC5XXX_ATA (CFG_MBAR + 0x3A00)
111	113
112	114	#define MPC5XXX_I2C1 (CFG_MBAR + 0x3D00)
113	115	#define MPC5XXX_I2C2 (CFG_MBAR + 0x3D40)
...	...	@@ -163,6 +165,12 @@
163	165	/* GPIO registers */
164	166	#define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000)
165	167
	168	+/* WakeUp GPIO registers */
	169	+#define MPC5XXX_WU_GPIO_ENABLE (MPC5XXX_WU_GPIO + 0x0000)
	170	+#define MPC5XXX_WU_GPIO_ODE (MPC5XXX_WU_GPIO + 0x0004)
	171	+#define MPC5XXX_WU_GPIO_DIR (MPC5XXX_WU_GPIO + 0x0008)
	172	+#define MPC5XXX_WU_GPIO_DATA (MPC5XXX_WU_GPIO + 0x000c)
	173	+
166	174	/* PCI registers */
167	175	#define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04)
168	176	#define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c)
...	...	@@ -209,6 +217,12 @@
209	217	#define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0)
210	218	#define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4)
211	219
	220	+/* ATA registers */
	221	+#define MPC5XXX_ATA_HOST_CONFIG (MPC5XXX_ATA + 0x0000)
	222	+#define MPC5XXX_ATA_PIO1 (MPC5XXX_ATA + 0x0008)
	223	+#define MPC5XXX_ATA_PIO2 (MPC5XXX_ATA + 0x000C)
	224	+#define MPC5XXX_ATA_SHARE_COUNT (MPC5XXX_ATA + 0x002C)
	225	+
212	226	/* I2Cn control register bits */
213	227	#define I2C_EN 0x80
214	228	#define I2C_IEN 0x40
...	...	@@ -286,6 +300,15 @@
286	300	#define PSC_MODE_ONE_STOP_5_BITS 0x00
287	301	#define PSC_MODE_ONE_STOP 0x07
288	302	#define PSC_MODE_TWO_STOP 0x0f
	303	+
	304	+/* ATA config fields */
	305	+#define MPC5xxx_ATA_HOSTCONF_SMR 0x80000000UL /* State machine
	306	+ reset */
	307	+#define MPC5xxx_ATA_HOSTCONF_FR 0x40000000UL /* FIFO Reset */
	308	+#define MPC5xxx_ATA_HOSTCONF_IE 0x02000000UL /* Enable interrupt
	309	+ in PIO */
	310	+#define MPC5xxx_ATA_HOSTCONF_IORDY 0x01000000UL /* Drive supports
	311	+ IORDY protocol */
289	312
290	313	#ifndef __ASSEMBLY__
291	314	struct mpc5xxx_psc {
...	...	@@ -343,7 +343,7 @@
343	343	/* Must happen after interrupts are initialized since
344	344	* an irq handler gets installed
345	345	*/
346		-#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
	346	+#if CONFIG_SERIAL_SOFTWARE_FIFO
347	347	serial_buffered_init();
348	348	#endif
349	349
...	...	@@ -577,7 +577,7 @@
577	577	*/
578	578	timer_init();
579	579
580		-#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
	580	+#if CONFIG_SERIAL_SOFTWARE_FIFO
581	581	serial_buffered_init();
582	582	#endif
583	583