mmc:eSDHC: Workaround for data timeout issue on Txxx SoC

1. The Data timeout counter value in eSDHC_SYSCTL register is not working as it should be, so add quirks to enable this workaround to fix it to the max value 0xE. 2. Add CONFIG_SYS_FSL_ERRATUM_ESDHC111 to enable its workaround. * Update of patch for change mmc interface by Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>

mmc:eSDHC: Workaround for data timeout issue on Txxx SoC
1. The Data timeout counter value in eSDHC_SYSCTL register is not working as it should be, so add quirks to enable this workaround to fix it to the max value 0xE. 2. Add CONFIG_SYS_FSL_ERRATUM_ESDHC111 to enable its workaround. * Update of patch for change mmc interface by Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Haijun.Zhang · Pantelis Antoniou
1 parent 8a573022c3
Showing 2 changed files with 8 additions and 0 deletions Side-by-side Diff
arch/powerpc/include/asm/config_mpc85xx.h
drivers/mmc/fsl_esdhc.c
@@ -734,6 +734,8 @@
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
  
 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
 #define CONFIG_E6500
@@ -778,6 +780,9 @@
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 #define CONFIG_SYS_FSL_ISBC_VER		2
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+
  
 #elif defined(CONFIG_PPC_C29X)
 #define CONFIG_MAX_CPUS			1
@@ -244,6 +244,9 @@
 		timeout++;
 #endif
  
+#ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+	timeout = 0xE;
+#endif
 	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
  
 	return 0;
...	...	@@ -734,6 +734,8 @@
734	734	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
735	735	#define CONFIG_SYS_FSL_ERRATUM_A006261
736	736	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
	737	+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
	738	+#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
737	739
738	740	#elif defined(CONFIG_PPC_T2080) \|\| defined(CONFIG_PPC_T2081)
739	741	#define CONFIG_E6500
...	...	@@ -778,6 +780,9 @@
778	780	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
779	781	#define CONFIG_SYS_FSL_SFP_VER_3_0
780	782	#define CONFIG_SYS_FSL_ISBC_VER 2
	783	+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
	784	+#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
	785	+
781	786
782	787	#elif defined(CONFIG_PPC_C29X)
783	788	#define CONFIG_MAX_CPUS 1
...	...	@@ -244,6 +244,9 @@
244	244	timeout++;
245	245	#endif
246	246
	247	+#ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
	248	+ timeout = 0xE;
	249	+#endif
247	250	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
248	251
249	252	return 0;