Eric Lee / smarc-uboot

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Commit 13b36face7adebd790c0b201792ec47b77d2fb0c

Authored by Jagan Teki
1 parent 3c92cca3cd
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

ARM: dts: sun5i: Update A10s/A13/gr8/r8 dts(i) files from Linux-v4.18-rc3 

Update all A10s/A13/gr8/r8devicetree dtsi and dtsi files from
Linux-v4.18-rc3 with below commit:
commit 190e3138f9577885691540dca59c2f07540bde04
Merge: cafc87023b0d a7affb13b271
Author: Arnd Bergmann <arnd@arndb.de>
Date:   Tue Mar 27 14:58:00 2018 +0200

    Merge tag 'sunxi-h3-h5-for-4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

Showing 22 changed files with 1016 additions and 2346 deletions Side-by-side Diff

arch/arm/dts/sun5i-a10s-auxtek-t003.dts
Diff comments   View file @ 13b36fa
... ... @@ -44,7 +44,6 @@
44 44 #include "sun5i-a10s.dtsi"
45 45 #include "sunxi-common-regulators.dtsi"
46 46 #include <dt-bindings/gpio/gpio.h>
47   -#include <dt-bindings/pinctrl/sun4i-a10.h>
48 47  
49 48 / {
50 49 model = "Auxtek t003 A10s hdmi tv-stick";
... ... @@ -94,8 +93,7 @@
94 93 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_t003>;
95 94 vmmc-supply = <&reg_vcc3v3>;
96 95 bus-width = <4>;
97   - cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
98   - cd-inverted;
  96 + cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
99 97 status = "okay";
100 98 };
101 99  
102 100  
... ... @@ -109,17 +107,15 @@
109 107  
110 108 &pio {
111 109 mmc0_cd_pin_t003: mmc0_cd_pin@0 {
112   - allwinner,pins = "PG1";
113   - allwinner,function = "gpio_in";
114   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
115   - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
  110 + pins = "PG1";
  111 + function = "gpio_in";
  112 + bias-pull-up;
116 113 };
117 114  
118 115 led_pins_t003: led_pins@0 {
119   - allwinner,pins = "PB2";
120   - allwinner,function = "gpio_out";
121   - allwinner,drive = <SUN4I_PINCTRL_20_MA>;
122   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  116 + pins = "PB2";
  117 + function = "gpio_out";
  118 + drive-strength = <20>;
123 119 };
124 120 };
125 121  
... ... @@ -137,14 +133,6 @@
137 133 pinctrl-names = "default";
138 134 pinctrl-0 = <&uart0_pins_a>;
139 135 status = "okay";
140   -};
141   -
142   -&usb0_vbus_pin_a {
143   - allwinner,pins = "PG13";
144   -};
145   -
146   -&usb1_vbus_pin_a {
147   - allwinner,pins = "PB10";
148 136 };
149 137  
150 138 &usb_otg {
arch/arm/dts/sun5i-a10s-auxtek-t004.dts
Diff comments   View file @ 13b36fa
... ... @@ -44,7 +44,6 @@
44 44 #include "sun5i-a10s.dtsi"
45 45 #include "sunxi-common-regulators.dtsi"
46 46 #include <dt-bindings/gpio/gpio.h>
47   -#include <dt-bindings/pinctrl/sun4i-a10.h>
48 47  
49 48 / {
50 49 model = "Auxtek t004 A10s hdmi tv-stick";
... ... @@ -105,8 +104,7 @@
105 104 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_t004>;
106 105 vmmc-supply = <&reg_vcc3v3>;
107 106 bus-width = <4>;
108   - cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
109   - cd-inverted;
  107 + cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
110 108 status = "okay";
111 109 };
112 110  
113 111  
114 112  
115 113  
116 114  
... ... @@ -124,26 +122,32 @@
124 122 status = "okay";
125 123 };
126 124  
  125 +&otg_sram {
  126 + status = "okay";
  127 +};
  128 +
127 129 &pio {
  130 + usb0_id_detect_pin: usb0_id_detect_pin@0 {
  131 + pins = "PG12";
  132 + function = "gpio_in";
  133 + bias-pull-up;
  134 + };
  135 +
128 136 mmc0_cd_pin_t004: mmc0_cd_pin@0 {
129   - allwinner,pins = "PG1";
130   - allwinner,function = "gpio_in";
131   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
132   - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
  137 + pins = "PG1";
  138 + function = "gpio_in";
  139 + bias-pull-up;
133 140 };
134 141  
135 142 mmc1_vcc_en_pin_t004: mmc1_vcc_en_pin@0 {
136   - allwinner,pins = "PB18";
137   - allwinner,function = "gpio_out";
138   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
139   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  143 + pins = "PB18";
  144 + function = "gpio_out";
140 145 };
141 146  
142 147 led_pins_t004: led_pins@0 {
143   - allwinner,pins = "PB2";
144   - allwinner,function = "gpio_out";
145   - allwinner,drive = <SUN4I_PINCTRL_20_MA>;
146   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  148 + pins = "PB2";
  149 + function = "gpio_out";
  150 + drive-strength = <20>;
147 151 };
148 152 };
149 153  
150 154  
... ... @@ -158,11 +162,15 @@
158 162 status = "okay";
159 163 };
160 164  
161   -&usb1_vbus_pin_a {
162   - allwinner,pins = "PG13";
  165 +&usb_otg {
  166 + dr_mode = "otg";
  167 + status = "okay";
163 168 };
164 169  
165 170 &usbphy {
  171 + pinctrl-names = "default";
  172 + pinctrl-0 = <&usb0_id_detect_pin>;
  173 + usb0_id_det-gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
166 174 usb1_vbus-supply = <&reg_usb1_vbus>;
167 175 status = "okay";
168 176 };
arch/arm/dts/sun5i-a10s-mk802.dts
Diff comments   View file @ 13b36fa
... ... @@ -92,8 +92,7 @@
92 92 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_mk802>;
93 93 vmmc-supply = <&reg_vcc3v3>;
94 94 bus-width = <4>;
95   - cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
96   - cd-inverted;
  95 + cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
97 96 status = "okay";
98 97 };
99 98  
100 99  
101 100  
... ... @@ -116,24 +115,19 @@
116 115  
117 116 &pio {
118 117 led_pins_mk802: led_pins@0 {
119   - allwinner,pins = "PB2";
120   - allwinner,function = "gpio_out";
121   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
122   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  118 + pins = "PB2";
  119 + function = "gpio_out";
123 120 };
124 121  
125 122 mmc0_cd_pin_mk802: mmc0_cd_pin@0 {
126   - allwinner,pins = "PG1";
127   - allwinner,function = "gpio_in";
128   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
129   - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
  123 + pins = "PG1";
  124 + function = "gpio_in";
  125 + bias-pull-up;
130 126 };
131 127  
132 128 usb1_vbus_pin_mk802: usb1_vbus_pin@0 {
133   - allwinner,pins = "PB10";
134   - allwinner,function = "gpio_out";
135   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
136   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  129 + pins = "PB10";
  130 + function = "gpio_out";
137 131 };
138 132 };
139 133  
... ... @@ -150,7 +144,7 @@
150 144 };
151 145  
152 146 &usb_otg {
153   - dr_mode = "otg";
  147 + dr_mode = "peripheral";
154 148 status = "okay";
155 149 };
156 150  
arch/arm/dts/sun5i-a10s-olinuxino-micro.dts
Diff comments   View file @ 13b36fa
... ... @@ -48,7 +48,6 @@
48 48  
49 49 #include <dt-bindings/gpio/gpio.h>
50 50 #include <dt-bindings/input/input.h>
51   -#include <dt-bindings/pinctrl/sun4i-a10.h>
52 51  
53 52 / {
54 53 model = "Olimex A10s-Olinuxino Micro";
... ... @@ -64,6 +63,17 @@
64 63 stdout-path = "serial0:115200n8";
65 64 };
66 65  
  66 + connector {
  67 + compatible = "hdmi-connector";
  68 + type = "a";
  69 +
  70 + port {
  71 + hdmi_con_in: endpoint {
  72 + remote-endpoint = <&hdmi_out_con>;
  73 + };
  74 + };
  75 + };
  76 +
67 77 leds {
68 78 compatible = "gpio-leds";
69 79 pinctrl-names = "default";
70 80  
... ... @@ -77,13 +87,17 @@
77 87 };
78 88 };
79 89  
  90 +&be0 {
  91 + status = "okay";
  92 +};
  93 +
80 94 &ehci0 {
81 95 status = "okay";
82 96 };
83 97  
84 98 &emac {
85 99 pinctrl-names = "default";
86   - pinctrl-0 = <&emac_pins_a>;
  100 + pinctrl-0 = <&emac_pins_b>;
87 101 phy = <&phy1>;
88 102 status = "okay";
89 103 };
... ... @@ -92,6 +106,16 @@
92 106 status = "okay";
93 107 };
94 108  
  109 +&hdmi {
  110 + status = "okay";
  111 +};
  112 +
  113 +&hdmi_out {
  114 + hdmi_out_con: endpoint {
  115 + remote-endpoint = <&hdmi_con_in>;
  116 + };
  117 +};
  118 +
95 119 &i2c0 {
96 120 pinctrl-names = "default";
97 121 pinctrl-0 = <&i2c0_pins_a>;
... ... @@ -177,8 +201,7 @@
177 201 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino_micro>;
178 202 vmmc-supply = <&reg_vcc3v3>;
179 203 bus-width = <4>;
180   - cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
181   - cd-inverted;
  204 + cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
182 205 status = "okay";
183 206 };
184 207  
... ... @@ -187,8 +210,7 @@
187 210 pinctrl-0 = <&mmc1_pins_a>, <&mmc1_cd_pin_olinuxino_micro>;
188 211 vmmc-supply = <&reg_vcc3v3>;
189 212 bus-width = <4>;
190   - cd-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
191   - cd-inverted;
  213 + cd-gpios = <&pio 6 13 GPIO_ACTIVE_LOW>; /* PG13 */
192 214 status = "okay";
193 215 };
194 216  
195 217  
196 218  
197 219  
198 220  
... ... @@ -202,38 +224,32 @@
202 224  
203 225 &pio {
204 226 mmc0_cd_pin_olinuxino_micro: mmc0_cd_pin@0 {
205   - allwinner,pins = "PG1";
206   - allwinner,function = "gpio_in";
207   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
208   - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
  227 + pins = "PG1";
  228 + function = "gpio_in";
  229 + bias-pull-up;
209 230 };
210 231  
211 232 mmc1_cd_pin_olinuxino_micro: mmc1_cd_pin@0 {
212   - allwinner,pins = "PG13";
213   - allwinner,function = "gpio_in";
214   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
215   - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
  233 + pins = "PG13";
  234 + function = "gpio_in";
  235 + bias-pull-up;
216 236 };
217 237  
218 238 led_pins_olinuxino: led_pins@0 {
219   - allwinner,pins = "PE3";
220   - allwinner,function = "gpio_out";
221   - allwinner,drive = <SUN4I_PINCTRL_20_MA>;
222   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  239 + pins = "PE3";
  240 + function = "gpio_out";
  241 + drive-strength = <20>;
223 242 };
224 243  
225 244 usb1_vbus_pin_olinuxino_m: usb1_vbus_pin@0 {
226   - allwinner,pins = "PB10";
227   - allwinner,function = "gpio_out";
228   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
229   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  245 + pins = "PB10";
  246 + function = "gpio_out";
230 247 };
231 248  
232 249 usb0_id_detect_pin: usb0_id_detect_pin@0 {
233   - allwinner,pins = "PG12";
234   - allwinner,function = "gpio_in";
235   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
236   - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
  250 + pins = "PG12";
  251 + function = "gpio_in";
  252 + bias-pull-up;
237 253 };
238 254 };
239 255  
240 256  
... ... @@ -250,11 +266,15 @@
250 266  
251 267 &spi2 {
252 268 pinctrl-names = "default";
253   - pinctrl-0 = <&spi2_pins_a>,
254   - <&spi2_cs0_pins_a>;
  269 + pinctrl-0 = <&spi2_pins_b>,
  270 + <&spi2_cs0_pins_b>;
255 271 status = "okay";
256 272 };
257 273  
  274 +&tcon0 {
  275 + status = "okay";
  276 +};
  277 +
258 278 &uart0 {
259 279 pinctrl-names = "default";
260 280 pinctrl-0 = <&uart0_pins_a>;
... ... @@ -263,7 +283,7 @@
263 283  
264 284 &uart2 {
265 285 pinctrl-names = "default";
266   - pinctrl-0 = <&uart2_pins_a>;
  286 + pinctrl-0 = <&uart2_pins_b>;
267 287 status = "okay";
268 288 };
269 289  
... ... @@ -276,10 +296,6 @@
276 296 &usb_otg {
277 297 dr_mode = "otg";
278 298 status = "okay";
279   -};
280   -
281   -&usb0_vbus_pin_a {
282   - allwinner,pins = "PG11";
283 299 };
284 300  
285 301 &usbphy {
arch/arm/dts/sun5i-a10s-r7-tv-dongle.dts
Diff comments   View file @ 13b36fa
... ... @@ -45,7 +45,6 @@
45 45 #include "sunxi-common-regulators.dtsi"
46 46  
47 47 #include <dt-bindings/gpio/gpio.h>
48   -#include <dt-bindings/pinctrl/sun4i-a10.h>
49 48  
50 49 / {
51 50 model = "R7 A10s hdmi tv-stick";
... ... @@ -81,8 +80,7 @@
81 80 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_r7>;
82 81 vmmc-supply = <&reg_vcc3v3>;
83 82 bus-width = <4>;
84   - cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
85   - cd-inverted;
  83 + cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
86 84 status = "okay";
87 85 };
88 86  
89 87  
90 88  
... ... @@ -101,24 +99,20 @@
101 99  
102 100 &pio {
103 101 mmc0_cd_pin_r7: mmc0_cd_pin@0 {
104   - allwinner,pins = "PG1";
105   - allwinner,function = "gpio_in";
106   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
107   - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
  102 + pins = "PG1";
  103 + function = "gpio_in";
  104 + bias-pull-up;
108 105 };
109 106  
110 107 led_pins_r7: led_pins@0 {
111   - allwinner,pins = "PB2";
112   - allwinner,function = "gpio_out";
113   - allwinner,drive = <SUN4I_PINCTRL_20_MA>;
114   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  108 + pins = "PB2";
  109 + function = "gpio_out";
  110 + drive-strength = <20>;
115 111 };
116 112  
117 113 usb1_vbus_pin_r7: usb1_vbus_pin@0 {
118   - allwinner,pins = "PG13";
119   - allwinner,function = "gpio_out";
120   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
121   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  114 + pins = "PG13";
  115 + function = "gpio_out";
122 116 };
123 117 };
124 118  
arch/arm/dts/sun5i-a10s-wobo-i5.dts
Diff comments   View file @ 13b36fa
... ... @@ -46,7 +46,6 @@
46 46  
47 47 #include <dt-bindings/gpio/gpio.h>
48 48 #include <dt-bindings/interrupt-controller/irq.h>
49   -#include <dt-bindings/pinctrl/sun4i-a10.h>
50 49  
51 50 / {
52 51 model = "A10s-Wobo i5";
... ... @@ -95,7 +94,7 @@
95 94  
96 95 &emac {
97 96 pinctrl-names = "default";
98   - pinctrl-0 = <&emac_pins_b>;
  97 + pinctrl-0 = <&emac_pins_a>;
99 98 phy = <&phy1>;
100 99 status = "okay";
101 100 };
... ... @@ -131,8 +130,7 @@
131 130 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_wobo_i5>;
132 131 vmmc-supply = <&reg_vcc3v3>;
133 132 bus-width = <4>;
134   - cd-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
135   - cd-inverted;
  133 + cd-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 */
136 134 status = "okay";
137 135 };
138 136  
139 137  
140 138  
... ... @@ -146,24 +144,19 @@
146 144  
147 145 &pio {
148 146 led_pins_wobo_i5: led_pins@0 {
149   - allwinner,pins = "PB2";
150   - allwinner,function = "gpio_out";
151   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
152   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  147 + pins = "PB2";
  148 + function = "gpio_out";
153 149 };
154 150  
155 151 mmc0_cd_pin_wobo_i5: mmc0_cd_pin@0 {
156   - allwinner,pins = "PB3";
157   - allwinner,function = "gpio_in";
158   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
159   - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
  152 + pins = "PB3";
  153 + function = "gpio_in";
  154 + bias-pull-up;
160 155 };
161 156  
162 157 emac_power_pin_wobo: emac_power_pin@0 {
163   - allwinner,pins = "PA02";
164   - allwinner,function = "gpio_out";
165   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
166   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  158 + pins = "PA02";
  159 + function = "gpio_out";
167 160 };
168 161 };
169 162  
... ... @@ -220,10 +213,6 @@
220 213 &usb_otg {
221 214 dr_mode = "host";
222 215 status = "okay";
223   -};
224   -
225   -&usb1_vbus_pin_a {
226   - allwinner,pins = "PG12";
227 216 };
228 217  
229 218 &usbphy {
arch/arm/dts/sun5i-a10s.dtsi
Diff comments   View file @ 13b36fa
... ... @@ -47,7 +47,6 @@
47 47 #include "sun5i.dtsi"
48 48  
49 49 #include <dt-bindings/dma/sun4i-a10.h>
50   -#include <dt-bindings/pinctrl/sun4i-a10.h>
51 50  
52 51 / {
53 52 interrupt-parent = <&intc>;
54 53  
55 54  
56 55  
57 56  
58 57  
59 58  
60 59  
61 60  
62 61  
63 62  
64 63  
65 64  
66 65  
67 66  
68 67  
69 68  
70 69  
71 70  
72 71  
73 72  
74 73  
75 74  
76 75  
... ... @@ -61,208 +60,119 @@
61 60 #size-cells = <1>;
62 61 ranges;
63 62  
64   - framebuffer@0 {
  63 + framebuffer@2 {
65 64 compatible = "allwinner,simple-framebuffer",
66 65 "simple-framebuffer";
67 66 allwinner,pipeline = "de_be0-lcd0-hdmi";
68   - clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
69   - <&ahb_gates 43>, <&ahb_gates 44>;
  67 + clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_HDMI>,
  68 + <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DRAM_DE_BE>,
  69 + <&ccu CLK_DE_BE>, <&ccu CLK_HDMI>;
70 70 status = "disabled";
71 71 };
  72 + };
72 73  
73   - framebuffer@1 {
74   - compatible = "allwinner,simple-framebuffer",
75   - "simple-framebuffer";
76   - allwinner,pipeline = "de_be0-lcd0";
77   - clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
78   - <&ahb_gates 44>;
79   - status = "disabled";
80   - };
  74 + display-engine {
  75 + compatible = "allwinner,sun5i-a10s-display-engine";
  76 + allwinner,pipelines = <&fe0>;
  77 + };
81 78  
82   - framebuffer@2 {
83   - compatible = "allwinner,simple-framebuffer",
84   - "simple-framebuffer";
85   - allwinner,pipeline = "de_be0-lcd0-tve0";
86   - clocks = <&pll3>, <&pll5 1>, <&ahb_gates 34>,
87   - <&ahb_gates 36>, <&ahb_gates 44>;
  79 + soc@1c00000 {
  80 + hdmi: hdmi@1c16000 {
  81 + compatible = "allwinner,sun5i-a10s-hdmi";
  82 + reg = <0x01c16000 0x1000>;
  83 + interrupts = <58>;
  84 + clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>,
  85 + <&ccu CLK_PLL_VIDEO0_2X>,
  86 + <&ccu CLK_PLL_VIDEO1_2X>;
  87 + clock-names = "ahb", "mod", "pll-0", "pll-1";
  88 + dmas = <&dma SUN4I_DMA_NORMAL 16>,
  89 + <&dma SUN4I_DMA_NORMAL 16>,
  90 + <&dma SUN4I_DMA_DEDICATED 24>;
  91 + dma-names = "ddc-tx", "ddc-rx", "audio-tx";
88 92 status = "disabled";
89   - };
90   - };
91 93  
92   - clocks {
93   - ahb_gates: clk@01c20060 {
94   - #clock-cells = <1>;
95   - compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
96   - reg = <0x01c20060 0x8>;
97   - clocks = <&ahb>;
98   - clock-indices = <0>, <1>,
99   - <2>, <5>, <6>,
100   - <7>, <8>, <9>,
101   - <10>, <13>,
102   - <14>, <17>, <18>,
103   - <20>, <21>, <22>,
104   - <26>, <28>, <32>,
105   - <34>, <36>, <40>,
106   - <43>, <44>,
107   - <46>, <51>,
108   - <52>;
109   - clock-output-names = "ahb_usbotg", "ahb_ehci",
110   - "ahb_ohci", "ahb_ss", "ahb_dma",
111   - "ahb_bist", "ahb_mmc0", "ahb_mmc1",
112   - "ahb_mmc2", "ahb_nand",
113   - "ahb_sdram", "ahb_emac", "ahb_ts",
114   - "ahb_spi0", "ahb_spi1", "ahb_spi2",
115   - "ahb_gps", "ahb_stimer", "ahb_ve",
116   - "ahb_tve", "ahb_lcd", "ahb_csi",
117   - "ahb_hdmi", "ahb_de_be",
118   - "ahb_de_fe", "ahb_iep",
119   - "ahb_mali400";
120   - };
  94 + ports {
  95 + #address-cells = <1>;
  96 + #size-cells = <0>;
121 97  
122   - apb0_gates: clk@01c20068 {
123   - #clock-cells = <1>;
124   - compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
125   - reg = <0x01c20068 0x4>;
126   - clocks = <&apb0>;
127   - clock-indices = <0>, <3>,
128   - <5>, <6>,
129   - <10>;
130   - clock-output-names = "apb0_codec", "apb0_iis",
131   - "apb0_pio", "apb0_ir",
132   - "apb0_keypad";
133   - };
  98 + hdmi_in: port@0 {
  99 + reg = <0>;
134 100  
135   - apb1_gates: clk@01c2006c {
136   - #clock-cells = <1>;
137   - compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
138   - reg = <0x01c2006c 0x4>;
139   - clocks = <&apb1>;
140   - clock-indices = <0>, <1>,
141   - <2>, <16>,
142   - <17>, <18>,
143   - <19>;
144   - clock-output-names = "apb1_i2c0", "apb1_i2c1",
145   - "apb1_i2c2", "apb1_uart0",
146   - "apb1_uart1", "apb1_uart2",
147   - "apb1_uart3";
148   - };
149   - };
  101 + hdmi_in_tcon0: endpoint {
  102 + remote-endpoint = <&tcon0_out_hdmi>;
  103 + };
  104 + };
150 105  
151   - soc@01c00000 {
152   - emac: ethernet@01c0b000 {
153   - compatible = "allwinner,sun4i-a10-emac";
154   - reg = <0x01c0b000 0x1000>;
155   - interrupts = <55>;
156   - clocks = <&ahb_gates 17>;
157   - allwinner,sram = <&emac_sram 1>;
158   - status = "disabled";
  106 + hdmi_out: port@1 {
  107 + #address-cells = <1>;
  108 + #size-cells = <0>;
  109 + reg = <1>;
  110 + };
  111 + };
159 112 };
160 113  
161   - mdio: mdio@01c0b080 {
162   - compatible = "allwinner,sun4i-a10-mdio";
163   - reg = <0x01c0b080 0x14>;
164   - status = "disabled";
165   - #address-cells = <1>;
166   - #size-cells = <0>;
167   - };
168   -
169   - pwm: pwm@01c20e00 {
  114 + pwm: pwm@1c20e00 {
170 115 compatible = "allwinner,sun5i-a10s-pwm";
171 116 reg = <0x01c20e00 0xc>;
172   - clocks = <&osc24M>;
  117 + clocks = <&ccu CLK_HOSC>;
173 118 #pwm-cells = <3>;
174 119 status = "disabled";
175 120 };
176   -
177   - uart0: serial@01c28000 {
178   - compatible = "snps,dw-apb-uart";
179   - reg = <0x01c28000 0x400>;
180   - interrupts = <1>;
181   - reg-shift = <2>;
182   - reg-io-width = <4>;
183   - clocks = <&apb1_gates 16>;
184   - status = "disabled";
185   - };
186   -
187   - uart2: serial@01c28800 {
188   - compatible = "snps,dw-apb-uart";
189   - reg = <0x01c28800 0x400>;
190   - interrupts = <3>;
191   - reg-shift = <2>;
192   - reg-io-width = <4>;
193   - clocks = <&apb1_gates 18>;
194   - status = "disabled";
195   - };
196 121 };
197 122 };
198 123  
  124 +&ccu {
  125 + compatible = "allwinner,sun5i-a10s-ccu";
  126 +};
  127 +
199 128 &pio {
200 129 compatible = "allwinner,sun5i-a10s-pinctrl";
201 130  
202 131 uart0_pins_a: uart0@0 {
203   - allwinner,pins = "PB19", "PB20";
204   - allwinner,function = "uart0";
205   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
206   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  132 + pins = "PB19", "PB20";
  133 + function = "uart0";
207 134 };
208 135  
209   - uart2_pins_a: uart2@0 {
210   - allwinner,pins = "PC18", "PC19";
211   - allwinner,function = "uart2";
212   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
213   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  136 + uart2_pins_b: uart2@1 {
  137 + pins = "PC18", "PC19";
  138 + function = "uart2";
214 139 };
215 140  
216   - emac_pins_a: emac0@0 {
217   - allwinner,pins = "PA0", "PA1", "PA2",
  141 + emac_pins_b: emac0@1 {
  142 + pins = "PA0", "PA1", "PA2",
218 143 "PA3", "PA4", "PA5", "PA6",
219 144 "PA7", "PA8", "PA9", "PA10",
220 145 "PA11", "PA12", "PA13", "PA14",
221 146 "PA15", "PA16";
222   - allwinner,function = "emac";
223   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
224   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  147 + function = "emac";
225 148 };
226 149  
227   - emac_pins_b: emac0@1 {
228   - allwinner,pins = "PD6", "PD7", "PD10",
229   - "PD11", "PD12", "PD13", "PD14",
230   - "PD15", "PD18", "PD19", "PD20",
231   - "PD21", "PD22", "PD23", "PD24",
232   - "PD25", "PD26", "PD27";
233   - allwinner,function = "emac";
234   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
235   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
236   - };
237   -
238 150 mmc1_pins_a: mmc1@0 {
239   - allwinner,pins = "PG3", "PG4", "PG5",
  151 + pins = "PG3", "PG4", "PG5",
240 152 "PG6", "PG7", "PG8";
241   - allwinner,function = "mmc1";
242   - allwinner,drive = <SUN4I_PINCTRL_30_MA>;
243   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  153 + function = "mmc1";
  154 + drive-strength = <30>;
244 155 };
245 156  
246   - spi2_pins_a: spi2@0 {
247   - allwinner,pins = "PB12", "PB13", "PB14";
248   - allwinner,function = "spi2";
249   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
250   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  157 + spi2_pins_b: spi2@1 {
  158 + pins = "PB12", "PB13", "PB14";
  159 + function = "spi2";
251 160 };
252 161  
253   - spi2_cs0_pins_a: spi2_cs0@0 {
254   - allwinner,pins = "PB11";
255   - allwinner,function = "spi2";
256   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
257   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  162 + spi2_cs0_pins_b: spi2_cs0@1 {
  163 + pins = "PB11";
  164 + function = "spi2";
258 165 };
259 166 };
260 167  
261 168 &sram_a {
262   - emac_sram: sram-section@8000 {
263   - compatible = "allwinner,sun4i-a10-sram-a3-a4";
264   - reg = <0x8000 0x4000>;
265   - status = "disabled";
  169 +};
  170 +
  171 +&tcon0_out {
  172 + tcon0_out_hdmi: endpoint@2 {
  173 + reg = <2>;
  174 + remote-endpoint = <&hdmi_in_tcon0>;
  175 + allwinner,tcon-channel = <1>;
266 176 };
267 177 };
arch/arm/dts/sun5i-a13-empire-electronix-d709.dts
Diff comments   View file @ 13b36fa
... ... @@ -46,7 +46,6 @@
46 46 #include <dt-bindings/gpio/gpio.h>
47 47 #include <dt-bindings/input/input.h>
48 48 #include <dt-bindings/interrupt-controller/irq.h>
49   -#include <dt-bindings/pinctrl/sun4i-a10.h>
50 49 #include <dt-bindings/pwm/pwm.h>
51 50  
52 51 / {
... ... @@ -126,8 +125,7 @@
126 125 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_d709>;
127 126 vmmc-supply = <&reg_vcc3v3>;
128 127 bus-width = <4>;
129   - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
130   - cd-inverted;
  128 + cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
131 129 status = "okay";
132 130 };
133 131  
134 132  
135 133  
... ... @@ -137,24 +135,21 @@
137 135  
138 136 &pio {
139 137 mmc0_cd_pin_d709: mmc0_cd_pin@0 {
140   - allwinner,pins = "PG0";
141   - allwinner,function = "gpio_in";
142   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
143   - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
  138 + pins = "PG0";
  139 + function = "gpio_in";
  140 + bias-pull-up;
144 141 };
145 142  
146 143 usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
147   - allwinner,pins = "PG1";
148   - allwinner,function = "gpio_in";
149   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
150   - allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
  144 + pins = "PG1";
  145 + function = "gpio_in";
  146 + bias-pull-down;
151 147 };
152 148  
153 149 usb0_id_detect_pin: usb0_id_detect_pin@0 {
154   - allwinner,pins = "PG2";
155   - allwinner,function = "gpio_in";
156   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
157   - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
  150 + pins = "PG2";
  151 + function = "gpio_in";
  152 + bias-pull-up;
158 153 };
159 154 };
160 155  
... ... @@ -209,10 +204,6 @@
209 204 &usb_otg {
210 205 dr_mode = "otg";
211 206 status = "okay";
212   -};
213   -
214   -&usb0_vbus_pin_a {
215   - allwinner,pins = "PG12";
216 207 };
217 208  
218 209 &usbphy {
arch/arm/dts/sun5i-a13-hsg-h702.dts
Diff comments   View file @ 13b36fa
... ... @@ -46,7 +46,6 @@
46 46  
47 47 #include <dt-bindings/gpio/gpio.h>
48 48 #include <dt-bindings/input/input.h>
49   -#include <dt-bindings/pinctrl/sun4i-a10.h>
50 49  
51 50 / {
52 51 model = "HSG H702";
... ... @@ -121,8 +120,7 @@
121 120 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_h702>;
122 121 vmmc-supply = <&reg_vcc3v3>;
123 122 bus-width = <4>;
124   - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
125   - cd-inverted;
  123 + cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
126 124 status = "okay";
127 125 };
128 126  
129 127  
130 128  
... ... @@ -136,24 +134,20 @@
136 134  
137 135 &pio {
138 136 mmc0_cd_pin_h702: mmc0_cd_pin@0 {
139   - allwinner,pins = "PG0";
140   - allwinner,function = "gpio_in";
141   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
142   - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
  137 + pins = "PG0";
  138 + function = "gpio_in";
  139 + bias-pull-up;
143 140 };
144 141  
145 142 usb0_id_detect_pin: usb0_id_detect_pin@0 {
146   - allwinner,pins = "PG2";
147   - allwinner,function = "gpio_in";
148   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
149   - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
  143 + pins = "PG2";
  144 + function = "gpio_in";
  145 + bias-pull-up;
150 146 };
151 147  
152 148 usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
153   - allwinner,pins = "PG1";
154   - allwinner,function = "gpio_in";
155   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
156   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  149 + pins = "PG1";
  150 + function = "gpio_in";
157 151 };
158 152 };
159 153  
... ... @@ -191,7 +185,6 @@
191 185 };
192 186  
193 187 &reg_usb0_vbus {
194   - pinctrl-0 = <&usb0_vbus_pin_a>;
195 188 gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
196 189 status = "okay";
197 190 };
... ... @@ -205,10 +198,6 @@
205 198 &usb_otg {
206 199 dr_mode = "otg";
207 200 status = "okay";
208   -};
209   -
210   -&usb0_vbus_pin_a {
211   - allwinner,pins = "PG12";
212 201 };
213 202  
214 203 &usbphy {
arch/arm/dts/sun5i-a13-inet-98v-rev2.dts
Diff comments   View file @ 13b36fa
... ... @@ -42,172 +42,10 @@
42 42  
43 43 /dts-v1/;
44 44 #include "sun5i-a13.dtsi"
45   -#include "sunxi-common-regulators.dtsi"
46   -#include <dt-bindings/gpio/gpio.h>
47   -#include <dt-bindings/input/input.h>
48   -#include <dt-bindings/interrupt-controller/irq.h>
49   -#include <dt-bindings/pinctrl/sun4i-a10.h>
  45 +#include "sun5i-reference-design-tablet.dtsi"
50 46  
51 47 / {
52 48 model = "INet-98V Rev 02";
53 49 compatible = "primux,inet98v-rev2", "allwinner,sun5i-a13";
54   -
55   - aliases {
56   - serial0 = &uart1;
57   - };
58   -
59   - chosen {
60   - stdout-path = "serial0:115200n8";
61   - };
62   -
63   -};
64   -
65   -&cpu0 {
66   - cpu-supply = <&reg_dcdc2>;
67   -};
68   -
69   -&ehci0 {
70   - status = "okay";
71   -};
72   -
73   -&i2c0 {
74   - pinctrl-names = "default";
75   - pinctrl-0 = <&i2c0_pins_a>;
76   - status = "okay";
77   -
78   - axp209: pmic@34 {
79   - reg = <0x34>;
80   - interrupts = <0>;
81   - };
82   -};
83   -
84   -#include "axp209.dtsi"
85   -
86   -&i2c1 {
87   - pinctrl-names = "default";
88   - pinctrl-0 = <&i2c1_pins_a>;
89   - status = "okay";
90   -
91   - pcf8563: rtc@51 {
92   - compatible = "nxp,pcf8563";
93   - reg = <0x51>;
94   - };
95   -};
96   -
97   -&lradc {
98   - vref-supply = <&reg_ldo2>;
99   - status = "okay";
100   -
101   - button@200 {
102   - label = "Volume Up";
103   - linux,code = <KEY_VOLUMEUP>;
104   - channel = <0>;
105   - voltage = <200000>;
106   - };
107   -
108   - button@400 {
109   - label = "Volume Down";
110   - linux,code = <KEY_VOLUMEDOWN>;
111   - channel = <0>;
112   - voltage = <400000>;
113   - };
114   -};
115   -
116   -&mmc0 {
117   - pinctrl-names = "default";
118   - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_inet98fv2>;
119   - vmmc-supply = <&reg_vcc3v3>;
120   - bus-width = <4>;
121   - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
122   - cd-inverted;
123   - status = "okay";
124   -};
125   -
126   -&otg_sram {
127   - status = "okay";
128   -};
129   -
130   -&pio {
131   - mmc0_cd_pin_inet98fv2: mmc0_cd_pin@0 {
132   - allwinner,pins = "PG0";
133   - allwinner,function = "gpio_in";
134   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
135   - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
136   - };
137   -
138   - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
139   - allwinner,pins = "PG1";
140   - allwinner,function = "gpio_in";
141   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
142   - allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
143   - };
144   -
145   - usb0_id_detect_pin: usb0_id_detect_pin@0 {
146   - allwinner,pins = "PG2";
147   - allwinner,function = "gpio_in";
148   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
149   - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
150   - };
151   -};
152   -
153   -&reg_dcdc2 {
154   - regulator-always-on;
155   - regulator-min-microvolt = <1000000>;
156   - regulator-max-microvolt = <1400000>;
157   - regulator-name = "vdd-cpu";
158   -};
159   -
160   -&reg_dcdc3 {
161   - regulator-always-on;
162   - regulator-min-microvolt = <1250000>;
163   - regulator-max-microvolt = <1250000>;
164   - regulator-name = "vdd-int-pll";
165   -};
166   -
167   -&reg_ldo1 {
168   - regulator-name = "vdd-rtc";
169   -};
170   -
171   -&reg_ldo2 {
172   - regulator-always-on;
173   - regulator-min-microvolt = <3000000>;
174   - regulator-max-microvolt = <3000000>;
175   - regulator-name = "avcc";
176   -};
177   -
178   -&reg_ldo3 {
179   - regulator-min-microvolt = <3300000>;
180   - regulator-max-microvolt = <3300000>;
181   - regulator-name = "vcc-wifi";
182   -};
183   -
184   -&reg_usb0_vbus {
185   - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
186   - status = "okay";
187   -};
188   -
189   -&uart1 {
190   - pinctrl-names = "default";
191   - pinctrl-0 = <&uart1_pins_b>;
192   - status = "okay";
193   -};
194   -
195   -&usb_otg {
196   - dr_mode = "otg";
197   - status = "okay";
198   -};
199   -
200   -&usb0_vbus_pin_a {
201   - allwinner,pins = "PG12";
202   -};
203   -
204   -&usbphy {
205   - pinctrl-names = "default";
206   - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
207   - usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
208   - usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
209   - usb0_vbus-supply = <&reg_usb0_vbus>;
210   - usb1_vbus-supply = <&reg_ldo3>;
211   - status = "okay";
212 50 };
arch/arm/dts/sun5i-a13-olinuxino-micro.dts
Diff comments   View file @ 13b36fa
... ... @@ -46,7 +46,6 @@
46 46 #include "sunxi-common-regulators.dtsi"
47 47  
48 48 #include <dt-bindings/gpio/gpio.h>
49   -#include <dt-bindings/pinctrl/sun4i-a10.h>
50 49  
51 50 / {
52 51 model = "Olimex A13-Olinuxino Micro";
... ... @@ -100,8 +99,7 @@
100 99 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxinom>;
101 100 vmmc-supply = <&reg_vcc3v3>;
102 101 bus-width = <4>;
103   - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
104   - cd-inverted;
  102 + cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
105 103 status = "okay";
106 104 };
107 105  
108 106  
109 107  
110 108  
111 109  
112 110  
... ... @@ -115,45 +113,37 @@
115 113  
116 114 &pio {
117 115 mmc0_cd_pin_olinuxinom: mmc0_cd_pin@0 {
118   - allwinner,pins = "PG0";
119   - allwinner,function = "gpio_in";
120   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
121   - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
  116 + pins = "PG0";
  117 + function = "gpio_in";
  118 + bias-pull-up;
122 119 };
123 120  
124 121 led_pins_olinuxinom: led_pins@0 {
125   - allwinner,pins = "PG9";
126   - allwinner,function = "gpio_out";
127   - allwinner,drive = <SUN4I_PINCTRL_20_MA>;
128   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  122 + pins = "PG9";
  123 + function = "gpio_out";
  124 + drive-strength = <20>;
129 125 };
130 126  
131 127 usb0_id_detect_pin: usb0_id_detect_pin@0 {
132   - allwinner,pins = "PG2";
133   - allwinner,function = "gpio_in";
134   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
135   - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
  128 + pins = "PG2";
  129 + function = "gpio_in";
  130 + bias-pull-up;
136 131 };
137 132  
138 133 usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
139   - allwinner,pins = "PG1";
140   - allwinner,function = "gpio_in";
141   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
142   - allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
  134 + pins = "PG1";
  135 + function = "gpio_in";
  136 + bias-pull-down;
143 137 };
144 138  
145 139 usb0_vbus_pin_olinuxinom: usb0_vbus_pin@0 {
146   - allwinner,pins = "PG12";
147   - allwinner,function = "gpio_out";
148   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
149   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  140 + pins = "PG12";
  141 + function = "gpio_out";
150 142 };
151 143  
152 144 usb1_vbus_pin_olinuxinom: usb1_vbus_pin@0 {
153   - allwinner,pins = "PG11";
154   - allwinner,function = "gpio_out";
155   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
156   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  145 + pins = "PG11";
  146 + function = "gpio_out";
157 147 };
158 148 };
159 149  
arch/arm/dts/sun5i-a13-olinuxino.dts
Diff comments   View file @ 13b36fa
... ... @@ -48,7 +48,6 @@
48 48  
49 49 #include <dt-bindings/gpio/gpio.h>
50 50 #include <dt-bindings/input/input.h>
51   -#include <dt-bindings/pinctrl/sun4i-a10.h>
52 51  
53 52 / {
54 53 model = "Olimex A13-Olinuxino";
55 54  
... ... @@ -72,8 +71,53 @@
72 71 default-state = "on";
73 72 };
74 73 };
  74 +
  75 + bridge {
  76 + compatible = "dumb-vga-dac";
  77 + #address-cells = <1>;
  78 + #size-cells = <0>;
  79 +
  80 + ports {
  81 + #address-cells = <1>;
  82 + #size-cells = <0>;
  83 +
  84 + port@0 {
  85 + reg = <0>;
  86 +
  87 + vga_bridge_in: endpoint {
  88 + remote-endpoint = <&tcon0_out_vga>;
  89 + };
  90 + };
  91 +
  92 + port@1 {
  93 + reg = <1>;
  94 +
  95 + vga_bridge_out: endpoint {
  96 + remote-endpoint = <&vga_con_in>;
  97 + };
  98 + };
  99 + };
  100 + };
  101 +
  102 + vga {
  103 + compatible = "vga-connector";
  104 +
  105 + port {
  106 + vga_con_in: endpoint {
  107 + remote-endpoint = <&vga_bridge_out>;
  108 + };
  109 + };
  110 + };
75 111 };
76 112  
  113 +&be0 {
  114 + status = "okay";
  115 +};
  116 +
  117 +&codec {
  118 + status = "okay";
  119 +};
  120 +
77 121 &ehci0 {
78 122 status = "okay";
79 123 };
... ... @@ -150,8 +194,7 @@
150 194 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>;
151 195 vmmc-supply = <&reg_vcc3v3>;
152 196 bus-width = <4>;
153   - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
154   - cd-inverted;
  197 + cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
155 198 status = "okay";
156 199 };
157 200  
158 201  
159 202  
160 203  
161 204  
... ... @@ -165,38 +208,32 @@
165 208  
166 209 &pio {
167 210 mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 {
168   - allwinner,pins = "PG0";
169   - allwinner,function = "gpio_in";
170   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
171   - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
  211 + pins = "PG0";
  212 + function = "gpio_in";
  213 + bias-pull-up;
172 214 };
173 215  
174 216 led_pins_olinuxino: led_pins@0 {
175   - allwinner,pins = "PG9";
176   - allwinner,function = "gpio_out";
177   - allwinner,drive = <SUN4I_PINCTRL_20_MA>;
178   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  217 + pins = "PG9";
  218 + function = "gpio_out";
  219 + drive-strength = <20>;
179 220 };
180 221  
181 222 usb0_id_detect_pin: usb0_id_detect_pin@0 {
182   - allwinner,pins = "PG2";
183   - allwinner,function = "gpio_in";
184   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
185   - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
  223 + pins = "PG2";
  224 + function = "gpio_in";
  225 + bias-pull-up;
186 226 };
187 227  
188 228 usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
189   - allwinner,pins = "PG1";
190   - allwinner,function = "gpio_in";
191   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
192   - allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
  229 + pins = "PG1";
  230 + function = "gpio_in";
  231 + bias-pull-down;
193 232 };
194 233  
195 234 usb1_vbus_pin_olinuxino: usb1_vbus_pin@0 {
196   - allwinner,pins = "PG11";
197   - allwinner,function = "gpio_out";
198   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
199   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  235 + pins = "PG11";
  236 + function = "gpio_out";
200 237 };
201 238 };
202 239  
... ... @@ -211,6 +248,19 @@
211 248 status = "okay";
212 249 };
213 250  
  251 +&tcon0 {
  252 + pinctrl-names = "default";
  253 + pinctrl-0 = <&lcd_rgb666_pins>;
  254 + status = "okay";
  255 +};
  256 +
  257 +&tcon0_out {
  258 + tcon0_out_vga: endpoint@0 {
  259 + reg = <0>;
  260 + remote-endpoint = <&vga_bridge_in>;
  261 + };
  262 +};
  263 +
214 264 &uart1 {
215 265 pinctrl-names = "default";
216 266 pinctrl-0 = <&uart1_pins_b>;
... ... @@ -220,10 +270,6 @@
220 270 &usb_otg {
221 271 dr_mode = "otg";
222 272 status = "okay";
223   -};
224   -
225   -&usb0_vbus_pin_a {
226   - allwinner,pins = "PG12";
227 273 };
228 274  
229 275 &usbphy {
arch/arm/dts/sun5i-a13-utoo-p66.dts
Diff comments   View file @ 13b36fa
... ... @@ -80,25 +80,9 @@
80 80 };
81 81  
82 82 &codec_pa_pin {
83   - allwinner,pins = "PG3";
  83 + pins = "PG3";
84 84 };
85 85  
86   -&i2c1 {
87   - icn8318: touchscreen@40 {
88   - compatible = "chipone,icn8318";
89   - reg = <0x40>;
90   - interrupt-parent = <&pio>;
91   - interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */
92   - pinctrl-names = "default";
93   - pinctrl-0 = <&ts_wake_pin_p66>;
94   - wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
95   - touchscreen-size-x = <800>;
96   - touchscreen-size-y = <480>;
97   - touchscreen-inverted-x;
98   - touchscreen-swapped-x-y;
99   - };
100   -};
101   -
102 86 &mmc2 {
103 87 pinctrl-names = "default";
104 88 pinctrl-0 = <&mmc2_pins_a>;
105 89  
106 90  
107 91  
... ... @@ -116,31 +100,36 @@
116 100  
117 101 &pio {
118 102 i2c_lcd_pins: i2c_lcd_pin@0 {
119   - allwinner,pins = "PG10", "PG12";
120   - allwinner,function = "gpio_out";
121   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
122   - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
  103 + pins = "PG10", "PG12";
  104 + function = "gpio_out";
  105 + bias-pull-up;
123 106 };
124   -
125   - ts_wake_pin_p66: ts_wake_pin@0 {
126   - allwinner,pins = "PB3";
127   - allwinner,function = "gpio_out";
128   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
129   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
130   - };
131   -
132 107 };
133 108  
134 109 &reg_usb0_vbus {
135 110 gpio = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
136 111 };
137 112  
  113 +&touchscreen {
  114 + compatible = "chipone,icn8318";
  115 + reg = <0x40>;
  116 + /* The P66 uses a different EINT then the reference design */
  117 + interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */
  118 + /* The icn8318 binding expects wake-gpios instead of power-gpios */
  119 + wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
  120 + touchscreen-size-x = <800>;
  121 + touchscreen-size-y = <480>;
  122 + touchscreen-inverted-x;
  123 + touchscreen-swapped-x-y;
  124 + status = "okay";
  125 +};
  126 +
138 127 &uart1 {
139 128 /* The P66 uses the uart pins as gpios */
140 129 status = "disabled";
141 130 };
142 131  
143 132 &usb0_vbus_pin_a {
144   - allwinner,pins = "PB4";
  133 + pins = "PB4";
145 134 };
arch/arm/dts/sun5i-a13.dtsi
Diff comments   View file @ 13b36fa
... ... @@ -46,27 +46,11 @@
46 46  
47 47 #include "sun5i.dtsi"
48 48  
49   -#include <dt-bindings/pinctrl/sun4i-a10.h>
50 49 #include <dt-bindings/thermal/thermal.h>
51 50  
52 51 / {
53 52 interrupt-parent = <&intc>;
54 53  
55   - chosen {
56   - #address-cells = <1>;
57   - #size-cells = <1>;
58   - ranges;
59   -
60   - framebuffer@0 {
61   - compatible = "allwinner,simple-framebuffer",
62   - "simple-framebuffer";
63   - allwinner,pipeline = "de_be0-lcd0";
64   - clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&de_be_clk>,
65   - <&tcon_ch0_clk>, <&dram_gates 26>;
66   - status = "disabled";
67   - };
68   - };
69   -
70 54 thermal-zones {
71 55 cpu_thermal {
72 56 /* milliseconds */
... ... @@ -84,7 +68,7 @@
84 68 trips {
85 69 cpu_alert0: cpu_alert0 {
86 70 /* milliCelsius */
87   - temperature = <850000>;
  71 + temperature = <85000>;
88 72 hysteresis = <2000>;
89 73 type = "passive";
90 74 };
91 75  
92 76  
93 77  
94 78  
... ... @@ -99,237 +83,27 @@
99 83 };
100 84 };
101 85  
102   - clocks {
103   - ahb_gates: clk@01c20060 {
104   - #clock-cells = <1>;
105   - compatible = "allwinner,sun5i-a13-ahb-gates-clk";
106   - reg = <0x01c20060 0x8>;
107   - clocks = <&ahb>;
108   - clock-indices = <0>, <1>,
109   - <2>, <5>, <6>,
110   - <7>, <8>, <9>,
111   - <10>, <13>,
112   - <14>, <20>,
113   - <21>, <22>,
114   - <28>, <32>, <34>,
115   - <36>, <40>, <44>,
116   - <46>, <51>,
117   - <52>;
118   - clock-output-names = "ahb_usbotg", "ahb_ehci",
119   - "ahb_ohci", "ahb_ss", "ahb_dma",
120   - "ahb_bist", "ahb_mmc0", "ahb_mmc1",
121   - "ahb_mmc2", "ahb_nand",
122   - "ahb_sdram", "ahb_spi0",
123   - "ahb_spi1", "ahb_spi2",
124   - "ahb_stimer", "ahb_ve", "ahb_tve",
125   - "ahb_lcd", "ahb_csi", "ahb_de_be",
126   - "ahb_de_fe", "ahb_iep",
127   - "ahb_mali400";
128   - };
129   -
130   - apb0_gates: clk@01c20068 {
131   - #clock-cells = <1>;
132   - compatible = "allwinner,sun5i-a13-apb0-gates-clk";
133   - reg = <0x01c20068 0x4>;
134   - clocks = <&apb0>;
135   - clock-indices = <0>, <5>,
136   - <6>;
137   - clock-output-names = "apb0_codec", "apb0_pio",
138   - "apb0_ir";
139   - };
140   -
141   - apb1_gates: clk@01c2006c {
142   - #clock-cells = <1>;
143   - compatible = "allwinner,sun5i-a13-apb1-gates-clk";
144   - reg = <0x01c2006c 0x4>;
145   - clocks = <&apb1>;
146   - clock-indices = <0>, <1>,
147   - <2>, <17>,
148   - <19>;
149   - clock-output-names = "apb1_i2c0", "apb1_i2c1",
150   - "apb1_i2c2", "apb1_uart1",
151   - "apb1_uart3";
152   - };
153   -
154   - dram_gates: clk@01c20100 {
155   - #clock-cells = <1>;
156   - compatible = "allwinner,sun5i-a13-dram-gates-clk",
157   - "allwinner,sun4i-a10-gates-clk";
158   - reg = <0x01c20100 0x4>;
159   - clocks = <&pll5 0>;
160   - clock-indices = <0>,
161   - <1>,
162   - <25>,
163   - <26>,
164   - <29>,
165   - <31>;
166   - clock-output-names = "dram_ve",
167   - "dram_csi",
168   - "dram_de_fe",
169   - "dram_de_be",
170   - "dram_ace",
171   - "dram_iep";
172   - };
173   -
174   - de_be_clk: clk@01c20104 {
175   - #clock-cells = <0>;
176   - #reset-cells = <0>;
177   - compatible = "allwinner,sun4i-a10-display-clk";
178   - reg = <0x01c20104 0x4>;
179   - clocks = <&pll3>, <&pll7>, <&pll5 1>;
180   - clock-output-names = "de-be";
181   - };
182   -
183   - de_fe_clk: clk@01c2010c {
184   - #clock-cells = <0>;
185   - #reset-cells = <0>;
186   - compatible = "allwinner,sun4i-a10-display-clk";
187   - reg = <0x01c2010c 0x4>;
188   - clocks = <&pll3>, <&pll7>, <&pll5 1>;
189   - clock-output-names = "de-fe";
190   - };
191   -
192   - tcon_ch0_clk: clk@01c20118 {
193   - #clock-cells = <0>;
194   - #reset-cells = <1>;
195   - compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
196   - reg = <0x01c20118 0x4>;
197   - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
198   - clock-output-names = "tcon-ch0-sclk";
199   - };
200   -
201   - tcon_ch1_clk: clk@01c2012c {
202   - #clock-cells = <0>;
203   - compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
204   - reg = <0x01c2012c 0x4>;
205   - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
206   - clock-output-names = "tcon-ch1-sclk";
207   - };
208   - };
209   -
210 86 display-engine {
211 87 compatible = "allwinner,sun5i-a13-display-engine";
212 88 allwinner,pipelines = <&fe0>;
213 89 };
214 90  
215   - soc@01c00000 {
216   - tcon0: lcd-controller@01c0c000 {
217   - compatible = "allwinner,sun5i-a13-tcon";
218   - reg = <0x01c0c000 0x1000>;
219   - interrupts = <44>;
220   - resets = <&tcon_ch0_clk 1>;
221   - reset-names = "lcd";
222   - clocks = <&ahb_gates 36>,
223   - <&tcon_ch0_clk>,
224   - <&tcon_ch1_clk>;
225   - clock-names = "ahb",
226   - "tcon-ch0",
227   - "tcon-ch1";
228   - clock-output-names = "tcon-pixel-clock";
229   - status = "disabled";
230   -
231   - ports {
232   - #address-cells = <1>;
233   - #size-cells = <0>;
234   -
235   - tcon0_in: port@0 {
236   - #address-cells = <1>;
237   - #size-cells = <0>;
238   - reg = <0>;
239   -
240   - tcon0_in_be0: endpoint@0 {
241   - reg = <0>;
242   - remote-endpoint = <&be0_out_tcon0>;
243   - };
244   - };
245   -
246   - tcon0_out: port@1 {
247   - #address-cells = <1>;
248   - #size-cells = <0>;
249   - reg = <1>;
250   - };
251   - };
252   - };
253   -
254   - pwm: pwm@01c20e00 {
  91 + soc@1c00000 {
  92 + pwm: pwm@1c20e00 {
255 93 compatible = "allwinner,sun5i-a13-pwm";
256 94 reg = <0x01c20e00 0xc>;
257   - clocks = <&osc24M>;
  95 + clocks = <&ccu CLK_HOSC>;
258 96 #pwm-cells = <3>;
259 97 status = "disabled";
260 98 };
261 99  
262   - fe0: display-frontend@01e00000 {
263   - compatible = "allwinner,sun5i-a13-display-frontend";
264   - reg = <0x01e00000 0x20000>;
265   - interrupts = <47>;
266   - clocks = <&ahb_gates 46>, <&de_fe_clk>,
267   - <&dram_gates 25>;
268   - clock-names = "ahb", "mod",
269   - "ram";
270   - resets = <&de_fe_clk>;
271   - status = "disabled";
272   -
273   - ports {
274   - #address-cells = <1>;
275   - #size-cells = <0>;
276   -
277   - fe0_out: port@1 {
278   - #address-cells = <1>;
279   - #size-cells = <0>;
280   - reg = <1>;
281   -
282   - fe0_out_be0: endpoint@0 {
283   - reg = <0>;
284   - remote-endpoint = <&be0_in_fe0>;
285   - };
286   - };
287   - };
288   - };
289   -
290   - be0: display-backend@01e60000 {
291   - compatible = "allwinner,sun5i-a13-display-backend";
292   - reg = <0x01e60000 0x10000>;
293   - clocks = <&ahb_gates 44>, <&de_be_clk>,
294   - <&dram_gates 26>;
295   - clock-names = "ahb", "mod",
296   - "ram";
297   - resets = <&de_be_clk>;
298   - status = "disabled";
299   -
300   - assigned-clocks = <&de_be_clk>;
301   - assigned-clock-rates = <300000000>;
302   -
303   - ports {
304   - #address-cells = <1>;
305   - #size-cells = <0>;
306   -
307   - be0_in: port@0 {
308   - #address-cells = <1>;
309   - #size-cells = <0>;
310   - reg = <0>;
311   -
312   - be0_in_fe0: endpoint@0 {
313   - reg = <0>;
314   - remote-endpoint = <&fe0_out_be0>;
315   - };
316   - };
317   -
318   - be0_out: port@1 {
319   - #address-cells = <1>;
320   - #size-cells = <0>;
321   - reg = <1>;
322   -
323   - be0_out_tcon0: endpoint@0 {
324   - reg = <0>;
325   - remote-endpoint = <&tcon0_in_be0>;
326   - };
327   - };
328   - };
329   - };
330 100 };
331 101 };
332 102  
  103 +&ccu {
  104 + compatible = "allwinner,sun5i-a13-ccu";
  105 +};
  106 +
333 107 &cpu0 {
334 108 clock-latency = <244144>; /* 8 32k periods */
335 109 operating-points = <
336 110  
... ... @@ -342,35 +116,9 @@
342 116 432000 1200000
343 117 >;
344 118 #cooling-cells = <2>;
345   - cooling-min-level = <0>;
346   - cooling-max-level = <5>;
347 119 };
348 120  
349 121 &pio {
350 122 compatible = "allwinner,sun5i-a13-pinctrl";
351   -
352   - lcd_rgb666_pins: lcd_rgb666@0 {
353   - allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
354   - "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
355   - "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
356   - "PD24", "PD25", "PD26", "PD27";
357   - allwinner,function = "lcd0";
358   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
359   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
360   - };
361   -
362   - uart1_pins_a: uart1@0 {
363   - allwinner,pins = "PE10", "PE11";
364   - allwinner,function = "uart1";
365   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
366   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
367   - };
368   -
369   - uart1_pins_b: uart1@1 {
370   - allwinner,pins = "PG3", "PG4";
371   - allwinner,function = "uart1";
372   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
373   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
374   - };
375 123 };
arch/arm/dts/sun5i-gr8-chip-pro.dts
Diff comments   View file @ 13b36fa
... ... @@ -159,23 +159,19 @@
159 159  
160 160 &pio {
161 161 usb0_id_pin_chip_pro: usb0-id-pin@0 {
162   - allwinner,pins = "PG2";
163   - allwinner,function = "gpio_in";
164   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
165   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  162 + pins = "PG2";
  163 + function = "gpio_in";
166 164 };
167 165  
168 166 wifi_reg_on_pin_chip_pro: wifi-reg-on-pin@0 {
169   - allwinner,pins = "PB10";
170   - allwinner,function = "gpio_out";
171   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
172   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  167 + pins = "PB10";
  168 + function = "gpio_out";
173 169 };
174 170 };
175 171  
176 172 &pwm {
177 173 pinctrl-names = "default";
178   - pinctrl-0 = <&pwm0_pins_a>, <&pwm1_pins>;
  174 + pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>;
179 175 status = "disabled";
180 176 };
181 177  
... ... @@ -224,7 +220,7 @@
224 220  
225 221 &uart1 {
226 222 pinctrl-names = "default";
227   - pinctrl-0 = <&uart1_pins_a>, <&uart1_cts_rts_pins_a>;
  223 + pinctrl-0 = <&uart1_pins_b>, <&uart1_cts_rts_pins_a>;
228 224 status = "okay";
229 225 };
230 226  
arch/arm/dts/sun5i-gr8.dtsi
Diff comments   View file @ 13b36fa
Changes suppressed. Click to show
... ... @@ -42,901 +42,33 @@
42 42 * OTHER DEALINGS IN THE SOFTWARE.
43 43 */
44 44  
45   -#include <dt-bindings/clock/sun4i-a10-pll2.h>
  45 +#include "sun5i.dtsi"
  46 +
  47 +#include <dt-bindings/clock/sun5i-ccu.h>
46 48 #include <dt-bindings/dma/sun4i-a10.h>
47   -#include <dt-bindings/pinctrl/sun4i-a10.h>
  49 +#include <dt-bindings/reset/sun5i-ccu.h>
48 50  
49 51 / {
50   - interrupt-parent = <&intc>;
51   - #address-cells = <1>;
52   - #size-cells = <1>;
53   -
54   - cpus {
55   - #address-cells = <1>;
56   - #size-cells = <0>;
57   -
58   - cpu0: cpu@0 {
59   - device_type = "cpu";
60   - compatible = "arm,cortex-a8";
61   - reg = <0x0>;
62   - clocks = <&cpu>;
63   - };
64   - };
65   -
66   - clocks {
67   - #address-cells = <1>;
68   - #size-cells = <1>;
69   - ranges;
70   -
71   - /*
72   - * This is a dummy clock, to be used as placeholder on
73   - * other mux clocks when a specific parent clock is not
74   - * yet implemented. It should be dropped when the driver
75   - * is complete.
76   - */
77   - dummy: dummy {
78   - #clock-cells = <0>;
79   - compatible = "fixed-clock";
80   - clock-frequency = <0>;
81   - };
82   -
83   - osc24M: clk@01c20050 {
84   - #clock-cells = <0>;
85   - compatible = "allwinner,sun4i-a10-osc-clk";
86   - reg = <0x01c20050 0x4>;
87   - clock-frequency = <24000000>;
88   - clock-output-names = "osc24M";
89   - };
90   -
91   - osc3M: osc3M-clk {
92   - compatible = "fixed-factor-clock";
93   - #clock-cells = <0>;
94   - clock-div = <8>;
95   - clock-mult = <1>;
96   - clocks = <&osc24M>;
97   - clock-output-names = "osc3M";
98   - };
99   -
100   - osc32k: clk@0 {
101   - #clock-cells = <0>;
102   - compatible = "fixed-clock";
103   - clock-frequency = <32768>;
104   - clock-output-names = "osc32k";
105   - };
106   -
107   - pll1: clk@01c20000 {
108   - #clock-cells = <0>;
109   - compatible = "allwinner,sun4i-a10-pll1-clk";
110   - reg = <0x01c20000 0x4>;
111   - clocks = <&osc24M>;
112   - clock-output-names = "pll1";
113   - };
114   -
115   - pll2: clk@01c20008 {
116   - #clock-cells = <1>;
117   - compatible = "allwinner,sun5i-a13-pll2-clk";
118   - reg = <0x01c20008 0x8>;
119   - clocks = <&osc24M>;
120   - clock-output-names = "pll2-1x", "pll2-2x",
121   - "pll2-4x", "pll2-8x";
122   - };
123   -
124   - pll3: clk@01c20010 {
125   - #clock-cells = <0>;
126   - compatible = "allwinner,sun4i-a10-pll3-clk";
127   - reg = <0x01c20010 0x4>;
128   - clocks = <&osc3M>;
129   - clock-output-names = "pll3";
130   - };
131   -
132   - pll3x2: pll3x2-clk {
133   - compatible = "allwinner,sun4i-a10-pll3-2x-clk";
134   - #clock-cells = <0>;
135   - clock-div = <1>;
136   - clock-mult = <2>;
137   - clocks = <&pll3>;
138   - clock-output-names = "pll3-2x";
139   - };
140   -
141   - pll4: clk@01c20018 {
142   - #clock-cells = <0>;
143   - compatible = "allwinner,sun4i-a10-pll1-clk";
144   - reg = <0x01c20018 0x4>;
145   - clocks = <&osc24M>;
146   - clock-output-names = "pll4";
147   - };
148   -
149   - pll5: clk@01c20020 {
150   - #clock-cells = <1>;
151   - compatible = "allwinner,sun4i-a10-pll5-clk";
152   - reg = <0x01c20020 0x4>;
153   - clocks = <&osc24M>;
154   - clock-output-names = "pll5_ddr", "pll5_other";
155   - };
156   -
157   - pll6: clk@01c20028 {
158   - #clock-cells = <1>;
159   - compatible = "allwinner,sun4i-a10-pll6-clk";
160   - reg = <0x01c20028 0x4>;
161   - clocks = <&osc24M>;
162   - clock-output-names = "pll6_sata", "pll6_other", "pll6";
163   - };
164   -
165   - pll7: clk@01c20030 {
166   - #clock-cells = <0>;
167   - compatible = "allwinner,sun4i-a10-pll3-clk";
168   - reg = <0x01c20030 0x4>;
169   - clocks = <&osc3M>;
170   - clock-output-names = "pll7";
171   - };
172   -
173   - pll7x2: pll7x2-clk {
174   - compatible = "allwinner,sun4i-a10-pll3-2x-clk";
175   - #clock-cells = <0>;
176   - clock-div = <1>;
177   - clock-mult = <2>;
178   - clocks = <&pll7>;
179   - clock-output-names = "pll7-2x";
180   - };
181   -
182   - /* dummy is 200M */
183   - cpu: cpu@01c20054 {
184   - #clock-cells = <0>;
185   - compatible = "allwinner,sun4i-a10-cpu-clk";
186   - reg = <0x01c20054 0x4>;
187   - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
188   - clock-output-names = "cpu";
189   - };
190   -
191   - axi: axi@01c20054 {
192   - #clock-cells = <0>;
193   - compatible = "allwinner,sun4i-a10-axi-clk";
194   - reg = <0x01c20054 0x4>;
195   - clocks = <&cpu>;
196   - clock-output-names = "axi";
197   - };
198   -
199   - ahb: ahb@01c20054 {
200   - #clock-cells = <0>;
201   - compatible = "allwinner,sun5i-a13-ahb-clk";
202   - reg = <0x01c20054 0x4>;
203   - clocks = <&axi>, <&cpu>, <&pll6 1>;
204   - clock-output-names = "ahb";
205   - /*
206   - * Use PLL6 as parent, instead of CPU/AXI
207   - * which has rate changes due to cpufreq
208   - */
209   - assigned-clocks = <&ahb>;
210   - assigned-clock-parents = <&pll6 1>;
211   - };
212   -
213   - apb0: apb0@01c20054 {
214   - #clock-cells = <0>;
215   - compatible = "allwinner,sun4i-a10-apb0-clk";
216   - reg = <0x01c20054 0x4>;
217   - clocks = <&ahb>;
218   - clock-output-names = "apb0";
219   - };
220   -
221   - apb1: clk@01c20058 {
222   - #clock-cells = <0>;
223   - compatible = "allwinner,sun4i-a10-apb1-clk";
224   - reg = <0x01c20058 0x4>;
225   - clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
226   - clock-output-names = "apb1";
227   - };
228   -
229   - axi_gates: clk@01c2005c {
230   - #clock-cells = <1>;
231   - compatible = "allwinner,sun4i-a10-gates-clk";
232   - reg = <0x01c2005c 0x4>;
233   - clocks = <&axi>;
234   - clock-indices = <0>;
235   - clock-output-names = "axi_dram";
236   - };
237   -
238   - ahb_gates: clk@01c20060 {
239   - #clock-cells = <1>;
240   - compatible = "allwinner,sun5i-a13-ahb-gates-clk";
241   - reg = <0x01c20060 0x8>;
242   - clocks = <&ahb>;
243   - clock-indices = <0>, <1>,
244   - <2>, <5>, <6>,
245   - <7>, <8>, <9>,
246   - <10>, <13>,
247   - <14>, <17>, <20>,
248   - <21>, <22>,
249   - <28>, <32>, <34>,
250   - <36>, <40>, <44>,
251   - <46>, <51>,
252   - <52>;
253   - clock-output-names = "ahb_usbotg", "ahb_ehci",
254   - "ahb_ohci", "ahb_ss", "ahb_dma",
255   - "ahb_bist", "ahb_mmc0", "ahb_mmc1",
256   - "ahb_mmc2", "ahb_nand",
257   - "ahb_sdram", "ahb_emac", "ahb_spi0",
258   - "ahb_spi1", "ahb_spi2",
259   - "ahb_hstimer", "ahb_ve", "ahb_tve",
260   - "ahb_lcd", "ahb_csi", "ahb_de_be",
261   - "ahb_de_fe", "ahb_iep",
262   - "ahb_mali400";
263   - };
264   -
265   - apb0_gates: clk@01c20068 {
266   - #clock-cells = <1>;
267   - compatible = "allwinner,sun4i-a10-gates-clk";
268   - reg = <0x01c20068 0x4>;
269   - clocks = <&apb0>;
270   - clock-indices = <0>, <3>,
271   - <5>, <6>;
272   - clock-output-names = "apb0_codec", "apb0_i2s0",
273   - "apb0_pio", "apb0_ir";
274   - };
275   -
276   - apb1_gates: clk@01c2006c {
277   - #clock-cells = <1>;
278   - compatible = "allwinner,sun4i-a10-gates-clk";
279   - reg = <0x01c2006c 0x4>;
280   - clocks = <&apb1>;
281   - clock-indices = <0>, <1>,
282   - <2>, <17>,
283   - <18>, <19>;
284   - clock-output-names = "apb1_i2c0", "apb1_i2c1",
285   - "apb1_i2c2", "apb1_uart1",
286   - "apb1_uart2", "apb1_uart3";
287   - };
288   -
289   - nand_clk: clk@01c20080 {
290   - #clock-cells = <0>;
291   - compatible = "allwinner,sun4i-a10-mod0-clk";
292   - reg = <0x01c20080 0x4>;
293   - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
294   - clock-output-names = "nand";
295   - };
296   -
297   - ms_clk: clk@01c20084 {
298   - #clock-cells = <0>;
299   - compatible = "allwinner,sun4i-a10-mod0-clk";
300   - reg = <0x01c20084 0x4>;
301   - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
302   - clock-output-names = "ms";
303   - };
304   -
305   - mmc0_clk: clk@01c20088 {
306   - #clock-cells = <1>;
307   - compatible = "allwinner,sun4i-a10-mmc-clk";
308   - reg = <0x01c20088 0x4>;
309   - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
310   - clock-output-names = "mmc0",
311   - "mmc0_output",
312   - "mmc0_sample";
313   - };
314   -
315   - mmc1_clk: clk@01c2008c {
316   - #clock-cells = <1>;
317   - compatible = "allwinner,sun4i-a10-mmc-clk";
318   - reg = <0x01c2008c 0x4>;
319   - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
320   - clock-output-names = "mmc1",
321   - "mmc1_output",
322   - "mmc1_sample";
323   - };
324   -
325   - mmc2_clk: clk@01c20090 {
326   - #clock-cells = <1>;
327   - compatible = "allwinner,sun4i-a10-mmc-clk";
328   - reg = <0x01c20090 0x4>;
329   - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
330   - clock-output-names = "mmc2",
331   - "mmc2_output",
332   - "mmc2_sample";
333   - };
334   -
335   - ts_clk: clk@01c20098 {
336   - #clock-cells = <0>;
337   - compatible = "allwinner,sun4i-a10-mod0-clk";
338   - reg = <0x01c20098 0x4>;
339   - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
340   - clock-output-names = "ts";
341   - };
342   -
343   - ss_clk: clk@01c2009c {
344   - #clock-cells = <0>;
345   - compatible = "allwinner,sun4i-a10-mod0-clk";
346   - reg = <0x01c2009c 0x4>;
347   - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
348   - clock-output-names = "ss";
349   - };
350   -
351   - spi0_clk: clk@01c200a0 {
352   - #clock-cells = <0>;
353   - compatible = "allwinner,sun4i-a10-mod0-clk";
354   - reg = <0x01c200a0 0x4>;
355   - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
356   - clock-output-names = "spi0";
357   - };
358   -
359   - spi1_clk: clk@01c200a4 {
360   - #clock-cells = <0>;
361   - compatible = "allwinner,sun4i-a10-mod0-clk";
362   - reg = <0x01c200a4 0x4>;
363   - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
364   - clock-output-names = "spi1";
365   - };
366   -
367   - spi2_clk: clk@01c200a8 {
368   - #clock-cells = <0>;
369   - compatible = "allwinner,sun4i-a10-mod0-clk";
370   - reg = <0x01c200a8 0x4>;
371   - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
372   - clock-output-names = "spi2";
373   - };
374   -
375   - ir0_clk: clk@01c200b0 {
376   - #clock-cells = <0>;
377   - compatible = "allwinner,sun4i-a10-mod0-clk";
378   - reg = <0x01c200b0 0x4>;
379   - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
380   - clock-output-names = "ir0";
381   - };
382   -
383   - i2s0_clk: clk@01c200b8 {
384   - #clock-cells = <0>;
385   - compatible = "allwinner,sun4i-a10-mod1-clk";
386   - reg = <0x01c200b8 0x4>;
387   - clocks = <&pll2 SUN4I_A10_PLL2_8X>,
388   - <&pll2 SUN4I_A10_PLL2_4X>,
389   - <&pll2 SUN4I_A10_PLL2_2X>,
390   - <&pll2 SUN4I_A10_PLL2_1X>;
391   - clock-output-names = "i2s0";
392   - };
393   -
394   - spdif_clk: clk@01c200c0 {
395   - #clock-cells = <0>;
396   - compatible = "allwinner,sun4i-a10-mod1-clk";
397   - reg = <0x01c200c0 0x4>;
398   - clocks = <&pll2 SUN4I_A10_PLL2_8X>,
399   - <&pll2 SUN4I_A10_PLL2_4X>,
400   - <&pll2 SUN4I_A10_PLL2_2X>,
401   - <&pll2 SUN4I_A10_PLL2_1X>;
402   - clock-output-names = "spdif";
403   - };
404   -
405   - usb_clk: clk@01c200cc {
406   - #clock-cells = <1>;
407   - #reset-cells = <1>;
408   - compatible = "allwinner,sun5i-a13-usb-clk";
409   - reg = <0x01c200cc 0x4>;
410   - clocks = <&pll6 1>;
411   - clock-output-names = "usb_ohci0", "usb_phy";
412   - };
413   -
414   - dram_gates: clk@01c20100 {
415   - #clock-cells = <1>;
416   - compatible = "nextthing,gr8-dram-gates-clk",
417   - "allwinner,sun4i-a10-gates-clk";
418   - reg = <0x01c20100 0x4>;
419   - clocks = <&pll5 0>;
420   - clock-indices = <0>,
421   - <1>,
422   - <25>,
423   - <26>,
424   - <29>,
425   - <31>;
426   - clock-output-names = "dram_ve",
427   - "dram_csi",
428   - "dram_de_fe",
429   - "dram_de_be",
430   - "dram_ace",
431   - "dram_iep";
432   - };
433   -
434   - de_be_clk: clk@01c20104 {
435   - #clock-cells = <0>;
436   - #reset-cells = <0>;
437   - compatible = "allwinner,sun4i-a10-display-clk";
438   - reg = <0x01c20104 0x4>;
439   - clocks = <&pll3>, <&pll7>, <&pll5 1>;
440   - clock-output-names = "de-be";
441   - };
442   -
443   - de_fe_clk: clk@01c2010c {
444   - #clock-cells = <0>;
445   - #reset-cells = <0>;
446   - compatible = "allwinner,sun4i-a10-display-clk";
447   - reg = <0x01c2010c 0x4>;
448   - clocks = <&pll3>, <&pll7>, <&pll5 1>;
449   - clock-output-names = "de-fe";
450   - };
451   -
452   - tcon_ch0_clk: clk@01c20118 {
453   - #clock-cells = <0>;
454   - #reset-cells = <1>;
455   - compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
456   - reg = <0x01c20118 0x4>;
457   - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
458   - clock-output-names = "tcon-ch0-sclk";
459   - };
460   -
461   - tcon_ch1_clk: clk@01c2012c {
462   - #clock-cells = <0>;
463   - compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
464   - reg = <0x01c2012c 0x4>;
465   - clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
466   - clock-output-names = "tcon-ch1-sclk";
467   - };
468   -
469   - codec_clk: clk@01c20140 {
470   - #clock-cells = <0>;
471   - compatible = "allwinner,sun4i-a10-codec-clk";
472   - reg = <0x01c20140 0x4>;
473   - clocks = <&pll2 SUN4I_A10_PLL2_1X>;
474   - clock-output-names = "codec";
475   - };
476   -
477   - mbus_clk: clk@01c2015c {
478   - #clock-cells = <0>;
479   - compatible = "allwinner,sun5i-a13-mbus-clk";
480   - reg = <0x01c2015c 0x4>;
481   - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
482   - clock-output-names = "mbus";
483   - };
484   - };
485   -
486 52 display-engine {
487 53 compatible = "allwinner,sun5i-a13-display-engine";
488 54 allwinner,pipelines = <&fe0>;
489 55 };
490 56  
491   - soc@01c00000 {
492   - compatible = "simple-bus";
493   - #address-cells = <1>;
494   - #size-cells = <1>;
495   - ranges;
496   -
497   - sram-controller@01c00000 {
498   - compatible = "allwinner,sun4i-a10-sram-controller";
499   - reg = <0x01c00000 0x30>;
500   - #address-cells = <1>;
501   - #size-cells = <1>;
502   - ranges;
503   -
504   - sram_a: sram@00000000 {
505   - compatible = "mmio-sram";
506   - reg = <0x00000000 0xc000>;
507   - #address-cells = <1>;
508   - #size-cells = <1>;
509   - ranges = <0 0x00000000 0xc000>;
510   - };
511   -
512   - sram_d: sram@00010000 {
513   - compatible = "mmio-sram";
514   - reg = <0x00010000 0x1000>;
515   - #address-cells = <1>;
516   - #size-cells = <1>;
517   - ranges = <0 0x00010000 0x1000>;
518   -
519   - otg_sram: sram-section@0000 {
520   - compatible = "allwinner,sun4i-a10-sram-d";
521   - reg = <0x0000 0x1000>;
522   - status = "disabled";
523   - };
524   - };
525   - };
526   -
527   - dma: dma-controller@01c02000 {
528   - compatible = "allwinner,sun4i-a10-dma";
529   - reg = <0x01c02000 0x1000>;
530   - interrupts = <27>;
531   - clocks = <&ahb_gates 6>;
532   - #dma-cells = <2>;
533   - };
534   -
535   - nfc: nand@01c03000 {
536   - compatible = "allwinner,sun4i-a10-nand";
537   - reg = <0x01c03000 0x1000>;
538   - interrupts = <37>;
539   - clocks = <&ahb_gates 13>, <&nand_clk>;
540   - clock-names = "ahb", "mod";
541   - dmas = <&dma SUN4I_DMA_DEDICATED 3>;
542   - dma-names = "rxtx";
543   - status = "disabled";
544   - #address-cells = <1>;
545   - #size-cells = <0>;
546   - };
547   -
548   - spi0: spi@01c05000 {
549   - compatible = "allwinner,sun4i-a10-spi";
550   - reg = <0x01c05000 0x1000>;
551   - interrupts = <10>;
552   - clocks = <&ahb_gates 20>, <&spi0_clk>;
553   - clock-names = "ahb", "mod";
554   - dmas = <&dma SUN4I_DMA_DEDICATED 27>,
555   - <&dma SUN4I_DMA_DEDICATED 26>;
556   - dma-names = "rx", "tx";
557   - status = "disabled";
558   - #address-cells = <1>;
559   - #size-cells = <0>;
560   - };
561   -
562   - spi1: spi@01c06000 {
563   - compatible = "allwinner,sun4i-a10-spi";
564   - reg = <0x01c06000 0x1000>;
565   - interrupts = <11>;
566   - clocks = <&ahb_gates 21>, <&spi1_clk>;
567   - clock-names = "ahb", "mod";
568   - dmas = <&dma SUN4I_DMA_DEDICATED 9>,
569   - <&dma SUN4I_DMA_DEDICATED 8>;
570   - dma-names = "rx", "tx";
571   - status = "disabled";
572   - #address-cells = <1>;
573   - #size-cells = <0>;
574   - };
575   -
576   - tve0: tv-encoder@01c0a000 {
577   - compatible = "allwinner,sun4i-a10-tv-encoder";
578   - reg = <0x01c0a000 0x1000>;
579   - clocks = <&ahb_gates 34>;
580   - resets = <&tcon_ch0_clk 0>;
581   - status = "disabled";
582   -
583   - port {
584   - #address-cells = <1>;
585   - #size-cells = <0>;
586   -
587   - tve0_in_tcon0: endpoint@0 {
588   - reg = <0>;
589   - remote-endpoint = <&tcon0_out_tve0>;
590   - };
591   - };
592   - };
593   -
594   - tcon0: lcd-controller@01c0c000 {
595   - compatible = "allwinner,sun5i-a13-tcon";
596   - reg = <0x01c0c000 0x1000>;
597   - interrupts = <44>;
598   - resets = <&tcon_ch0_clk 1>;
599   - reset-names = "lcd";
600   - clocks = <&ahb_gates 36>,
601   - <&tcon_ch0_clk>,
602   - <&tcon_ch1_clk>;
603   - clock-names = "ahb",
604   - "tcon-ch0",
605   - "tcon-ch1";
606   - clock-output-names = "tcon-pixel-clock";
607   - status = "disabled";
608   -
609   - ports {
610   - #address-cells = <1>;
611   - #size-cells = <0>;
612   -
613   - tcon0_in: port@0 {
614   - #address-cells = <1>;
615   - #size-cells = <0>;
616   - reg = <0>;
617   -
618   - tcon0_in_be0: endpoint@0 {
619   - reg = <0>;
620   - remote-endpoint = <&be0_out_tcon0>;
621   - };
622   - };
623   -
624   - tcon0_out: port@1 {
625   - #address-cells = <1>;
626   - #size-cells = <0>;
627   - reg = <1>;
628   -
629   - tcon0_out_tve0: endpoint@1 {
630   - reg = <1>;
631   - remote-endpoint = <&tve0_in_tcon0>;
632   - };
633   - };
634   - };
635   - };
636   -
637   - mmc0: mmc@01c0f000 {
638   - compatible = "allwinner,sun5i-a13-mmc";
639   - reg = <0x01c0f000 0x1000>;
640   - clocks = <&ahb_gates 8>,
641   - <&mmc0_clk 0>,
642   - <&mmc0_clk 1>,
643   - <&mmc0_clk 2>;
644   - clock-names = "ahb",
645   - "mmc",
646   - "output",
647   - "sample";
648   - interrupts = <32>;
649   - status = "disabled";
650   - #address-cells = <1>;
651   - #size-cells = <0>;
652   - };
653   -
654   - mmc1: mmc@01c10000 {
655   - compatible = "allwinner,sun5i-a13-mmc";
656   - reg = <0x01c10000 0x1000>;
657   - clocks = <&ahb_gates 9>,
658   - <&mmc1_clk 0>,
659   - <&mmc1_clk 1>,
660   - <&mmc1_clk 2>;
661   - clock-names = "ahb",
662   - "mmc",
663   - "output",
664   - "sample";
665   - interrupts = <33>;
666   - status = "disabled";
667   - #address-cells = <1>;
668   - #size-cells = <0>;
669   - };
670   -
671   - mmc2: mmc@01c11000 {
672   - compatible = "allwinner,sun5i-a13-mmc";
673   - reg = <0x01c11000 0x1000>;
674   - clocks = <&ahb_gates 10>,
675   - <&mmc2_clk 0>,
676   - <&mmc2_clk 1>,
677   - <&mmc2_clk 2>;
678   - clock-names = "ahb",
679   - "mmc",
680   - "output",
681   - "sample";
682   - interrupts = <34>;
683   - status = "disabled";
684   - #address-cells = <1>;
685   - #size-cells = <0>;
686   - };
687   -
688   - usb_otg: usb@01c13000 {
689   - compatible = "allwinner,sun4i-a10-musb";
690   - reg = <0x01c13000 0x0400>;
691   - clocks = <&ahb_gates 0>;
692   - interrupts = <38>;
693   - interrupt-names = "mc";
694   - phys = <&usbphy 0>;
695   - phy-names = "usb";
696   - extcon = <&usbphy 0>;
697   - allwinner,sram = <&otg_sram 1>;
698   - status = "disabled";
699   -
700   - dr_mode = "otg";
701   - };
702   -
703   - usbphy: phy@01c13400 {
704   - #phy-cells = <1>;
705   - compatible = "allwinner,sun5i-a13-usb-phy";
706   - reg = <0x01c13400 0x10 0x01c14800 0x4>;
707   - reg-names = "phy_ctrl", "pmu1";
708   - clocks = <&usb_clk 8>;
709   - clock-names = "usb_phy";
710   - resets = <&usb_clk 0>, <&usb_clk 1>;
711   - reset-names = "usb0_reset", "usb1_reset";
712   - status = "disabled";
713   - };
714   -
715   - ehci0: usb@01c14000 {
716   - compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
717   - reg = <0x01c14000 0x100>;
718   - interrupts = <39>;
719   - clocks = <&ahb_gates 1>;
720   - phys = <&usbphy 1>;
721   - phy-names = "usb";
722   - status = "disabled";
723   - };
724   -
725   - ohci0: usb@01c14400 {
726   - compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
727   - reg = <0x01c14400 0x100>;
728   - interrupts = <40>;
729   - clocks = <&usb_clk 6>, <&ahb_gates 2>;
730   - phys = <&usbphy 1>;
731   - phy-names = "usb";
732   - status = "disabled";
733   - };
734   -
735   - spi2: spi@01c17000 {
736   - compatible = "allwinner,sun4i-a10-spi";
737   - reg = <0x01c17000 0x1000>;
738   - interrupts = <12>;
739   - clocks = <&ahb_gates 22>, <&spi2_clk>;
740   - clock-names = "ahb", "mod";
741   - dmas = <&dma SUN4I_DMA_DEDICATED 29>,
742   - <&dma SUN4I_DMA_DEDICATED 28>;
743   - dma-names = "rx", "tx";
744   - status = "disabled";
745   - #address-cells = <1>;
746   - #size-cells = <0>;
747   - };
748   -
749   - intc: interrupt-controller@01c20400 {
750   - compatible = "allwinner,sun4i-a10-ic";
751   - reg = <0x01c20400 0x400>;
752   - interrupt-controller;
753   - #interrupt-cells = <1>;
754   - };
755   -
756   - pio: pinctrl@01c20800 {
757   - compatible = "nextthing,gr8-pinctrl";
758   - reg = <0x01c20800 0x400>;
759   - interrupts = <28>;
760   - clocks = <&apb0_gates 5>;
761   - gpio-controller;
762   - interrupt-controller;
763   - #interrupt-cells = <3>;
764   - #gpio-cells = <3>;
765   -
766   - i2c0_pins_a: i2c0@0 {
767   - allwinner,pins = "PB0", "PB1";
768   - allwinner,function = "i2c0";
769   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
770   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
771   - };
772   -
773   - i2c1_pins_a: i2c1@0 {
774   - allwinner,pins = "PB15", "PB16";
775   - allwinner,function = "i2c1";
776   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
777   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
778   - };
779   -
780   - i2c2_pins_a: i2c2@0 {
781   - allwinner,pins = "PB17", "PB18";
782   - allwinner,function = "i2c2";
783   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
784   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
785   - };
786   -
787   - i2s0_data_pins_a: i2s0-data@0 {
788   - allwinner,pins = "PB6", "PB7", "PB8", "PB9";
789   - allwinner,function = "i2s0";
790   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
791   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
792   - };
793   -
794   - i2s0_mclk_pins_a: i2s0-mclk@0 {
795   - allwinner,pins = "PB5";
796   - allwinner,function = "i2s0";
797   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
798   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
799   - };
800   -
801   - ir0_rx_pins_a: ir0@0 {
802   - allwinner,pins = "PB4";
803   - allwinner,function = "ir0";
804   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
805   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
806   - };
807   -
808   - lcd_rgb666_pins: lcd-rgb666@0 {
809   - allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
810   - "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
811   - "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
812   - "PD24", "PD25", "PD26", "PD27";
813   - allwinner,function = "lcd0";
814   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
815   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
816   - };
817   -
818   - mmc0_pins_a: mmc0@0 {
819   - allwinner,pins = "PF0", "PF1", "PF2", "PF3",
820   - "PF4", "PF5";
821   - allwinner,function = "mmc0";
822   - allwinner,drive = <SUN4I_PINCTRL_30_MA>;
823   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
824   - };
825   -
826   - nand_pins_a: nand-base0@0 {
827   - allwinner,pins = "PC0", "PC1", "PC2",
828   - "PC5", "PC8", "PC9", "PC10",
829   - "PC11", "PC12", "PC13", "PC14",
830   - "PC15";
831   - allwinner,function = "nand0";
832   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
833   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
834   - };
835   -
836   - nand_cs0_pins_a: nand-cs@0 {
837   - allwinner,pins = "PC4";
838   - allwinner,function = "nand0";
839   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
840   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
841   - };
842   -
843   - nand_rb0_pins_a: nand-rb@0 {
844   - allwinner,pins = "PC6";
845   - allwinner,function = "nand0";
846   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
847   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
848   - };
849   -
850   - pwm0_pins_a: pwm0@0 {
851   - allwinner,pins = "PB2";
852   - allwinner,function = "pwm0";
853   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
854   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
855   - };
856   -
857   - pwm1_pins: pwm1 {
858   - allwinner,pins = "PG13";
859   - allwinner,function = "pwm1";
860   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
861   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
862   - };
863   -
864   - spdif_tx_pins_a: spdif@0 {
865   - allwinner,pins = "PB10";
866   - allwinner,function = "spdif";
867   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
868   - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
869   - };
870   -
871   - uart1_pins_a: uart1@1 {
872   - allwinner,pins = "PG3", "PG4";
873   - allwinner,function = "uart1";
874   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
875   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
876   - };
877   -
878   - uart1_cts_rts_pins_a: uart1-cts-rts@0 {
879   - allwinner,pins = "PG5", "PG6";
880   - allwinner,function = "uart1";
881   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
882   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
883   - };
884   -
885   - uart2_pins_a: uart2@1 {
886   - allwinner,pins = "PD2", "PD3";
887   - allwinner,function = "uart2";
888   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
889   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
890   - };
891   -
892   - uart2_cts_rts_pins_a: uart2-cts-rts@0 {
893   - allwinner,pins = "PD4", "PD5";
894   - allwinner,function = "uart2";
895   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
896   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
897   - };
898   -
899   - uart3_pins_a: uart3@1 {
900   - allwinner,pins = "PG9", "PG10";
901   - allwinner,function = "uart3";
902   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
903   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
904   - };
905   -
906   - uart3_cts_rts_pins_a: uart3-cts-rts@0 {
907   - allwinner,pins = "PG11", "PG12";
908   - allwinner,function = "uart3";
909   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
910   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
911   - };
912   - };
913   -
914   - pwm: pwm@01c20e00 {
  57 + soc@1c00000 {
  58 + pwm: pwm@1c20e00 {
915 59 compatible = "allwinner,sun5i-a10s-pwm";
916 60 reg = <0x01c20e00 0xc>;
917   - clocks = <&osc24M>;
  61 + clocks = <&ccu CLK_HOSC>;
918 62 #pwm-cells = <3>;
919 63 status = "disabled";
920 64 };
921 65  
922   - timer@01c20c00 {
923   - compatible = "allwinner,sun4i-a10-timer";
924   - reg = <0x01c20c00 0x90>;
925   - interrupts = <22>;
926   - clocks = <&osc24M>;
927   - };
928   -
929   - wdt: watchdog@01c20c90 {
930   - compatible = "allwinner,sun4i-a10-wdt";
931   - reg = <0x01c20c90 0x10>;
932   - };
933   -
934   - spdif: spdif@01c21000 {
  66 + spdif: spdif@1c21000 {
935 67 #sound-dai-cells = <0>;
936 68 compatible = "allwinner,sun4i-a10-spdif";
937 69 reg = <0x01c21000 0x400>;
938 70 interrupts = <13>;
939   - clocks = <&apb0_gates 1>, <&spdif_clk>;
  71 + clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
940 72 clock-names = "apb", "spdif";
941 73 dmas = <&dma SUN4I_DMA_NORMAL 2>,
942 74 <&dma SUN4I_DMA_NORMAL 2>;
943 75  
944 76  
945 77  
946 78  
947 79  
948 80  
949 81  
950 82  
951 83  
... ... @@ -944,190 +76,52 @@
944 76 status = "disabled";
945 77 };
946 78  
947   - ir0: ir@01c21800 {
948   - compatible = "allwinner,sun4i-a10-ir";
949   - clocks = <&apb0_gates 6>, <&ir0_clk>;
950   - clock-names = "apb", "ir";
951   - interrupts = <5>;
952   - reg = <0x01c21800 0x40>;
953   - status = "disabled";
954   - };
955   -
956   - i2s0: i2s@01c22400 {
  79 + i2s0: i2s@1c22400 {
957 80 #sound-dai-cells = <0>;
958 81 compatible = "allwinner,sun4i-a10-i2s";
959 82 reg = <0x01c22400 0x400>;
960 83 interrupts = <16>;
961   - clocks = <&apb0_gates 3>, <&i2s0_clk>;
  84 + clocks = <&ccu CLK_APB0_I2S>, <&ccu CLK_I2S>;
962 85 clock-names = "apb", "mod";
963 86 dmas = <&dma SUN4I_DMA_NORMAL 3>,
964 87 <&dma SUN4I_DMA_NORMAL 3>;
965 88 dma-names = "rx", "tx";
966 89 status = "disabled";
967 90 };
  91 + };
  92 +};
968 93  
969   - lradc: lradc@01c22800 {
970   - compatible = "allwinner,sun4i-a10-lradc-keys";
971   - reg = <0x01c22800 0x100>;
972   - interrupts = <31>;
973   - status = "disabled";
974   - };
  94 +&ccu {
  95 + compatible = "nextthing,gr8-ccu";
  96 +};
975 97  
976   - codec: codec@01c22c00 {
977   - #sound-dai-cells = <0>;
978   - compatible = "allwinner,sun4i-a10-codec";
979   - reg = <0x01c22c00 0x40>;
980   - interrupts = <30>;
981   - clocks = <&apb0_gates 0>, <&codec_clk>;
982   - clock-names = "apb", "codec";
983   - dmas = <&dma SUN4I_DMA_NORMAL 19>,
984   - <&dma SUN4I_DMA_NORMAL 19>;
985   - dma-names = "rx", "tx";
986   - status = "disabled";
987   - };
  98 +&pio {
  99 + compatible = "nextthing,gr8-pinctrl";
988 100  
989   - rtp: rtp@01c25000 {
990   - compatible = "allwinner,sun5i-a13-ts";
991   - reg = <0x01c25000 0x100>;
992   - interrupts = <29>;
993   - #thermal-sensor-cells = <0>;
994   - };
  101 + i2s0_data_pins_a: i2s0-data@0 {
  102 + pins = "PB6", "PB7", "PB8", "PB9";
  103 + function = "i2s0";
  104 + };
995 105  
996   - uart1: serial@01c28400 {
997   - compatible = "snps,dw-apb-uart";
998   - reg = <0x01c28400 0x400>;
999   - interrupts = <2>;
1000   - reg-shift = <2>;
1001   - reg-io-width = <4>;
1002   - clocks = <&apb1_gates 17>;
1003   - status = "disabled";
1004   - };
  106 + i2s0_mclk_pins_a: i2s0-mclk@0 {
  107 + pins = "PB5";
  108 + function = "i2s0";
  109 + };
1005 110  
1006   - uart2: serial@01c28800 {
1007   - compatible = "snps,dw-apb-uart";
1008   - reg = <0x01c28800 0x400>;
1009   - interrupts = <3>;
1010   - reg-shift = <2>;
1011   - reg-io-width = <4>;
1012   - clocks = <&apb1_gates 18>;
1013   - status = "disabled";
1014   - };
  111 + pwm1_pins: pwm1 {
  112 + pins = "PG13";
  113 + function = "pwm1";
  114 + };
1015 115  
1016   - uart3: serial@01c28c00 {
1017   - compatible = "snps,dw-apb-uart";
1018   - reg = <0x01c28c00 0x400>;
1019   - interrupts = <4>;
1020   - reg-shift = <2>;
1021   - reg-io-width = <4>;
1022   - clocks = <&apb1_gates 19>;
1023   - status = "disabled";
1024   - };
  116 + spdif_tx_pins_a: spdif@0 {
  117 + pins = "PB10";
  118 + function = "spdif";
  119 + bias-pull-up;
  120 + };
1025 121  
1026   - i2c0: i2c@01c2ac00 {
1027   - compatible = "allwinner,sun4i-a10-i2c";
1028   - reg = <0x01c2ac00 0x400>;
1029   - interrupts = <7>;
1030   - clocks = <&apb1_gates 0>;
1031   - status = "disabled";
1032   - #address-cells = <1>;
1033   - #size-cells = <0>;
1034   - };
1035   -
1036   - i2c1: i2c@01c2b000 {
1037   - compatible = "allwinner,sun4i-a10-i2c";
1038   - reg = <0x01c2b000 0x400>;
1039   - interrupts = <8>;
1040   - clocks = <&apb1_gates 1>;
1041   - status = "disabled";
1042   - #address-cells = <1>;
1043   - #size-cells = <0>;
1044   - };
1045   -
1046   - i2c2: i2c@01c2b400 {
1047   - compatible = "allwinner,sun4i-a10-i2c";
1048   - reg = <0x01c2b400 0x400>;
1049   - interrupts = <9>;
1050   - clocks = <&apb1_gates 2>;
1051   - status = "disabled";
1052   - #address-cells = <1>;
1053   - #size-cells = <0>;
1054   - };
1055   -
1056   - timer@01c60000 {
1057   - compatible = "allwinner,sun5i-a13-hstimer";
1058   - reg = <0x01c60000 0x1000>;
1059   - interrupts = <82>, <83>;
1060   - clocks = <&ahb_gates 28>;
1061   - };
1062   -
1063   - fe0: display-frontend@01e00000 {
1064   - compatible = "allwinner,sun5i-a13-display-frontend";
1065   - reg = <0x01e00000 0x20000>;
1066   - interrupts = <47>;
1067   - clocks = <&ahb_gates 46>, <&de_fe_clk>,
1068   - <&dram_gates 25>;
1069   - clock-names = "ahb", "mod",
1070   - "ram";
1071   - resets = <&de_fe_clk>;
1072   - status = "disabled";
1073   -
1074   - ports {
1075   - #address-cells = <1>;
1076   - #size-cells = <0>;
1077   -
1078   - fe0_out: port@1 {
1079   - #address-cells = <1>;
1080   - #size-cells = <0>;
1081   - reg = <1>;
1082   -
1083   - fe0_out_be0: endpoint@0 {
1084   - reg = <0>;
1085   - remote-endpoint = <&be0_in_fe0>;
1086   - };
1087   - };
1088   - };
1089   - };
1090   -
1091   - be0: display-backend@01e60000 {
1092   - compatible = "allwinner,sun5i-a13-display-backend";
1093   - reg = <0x01e60000 0x10000>;
1094   - clocks = <&ahb_gates 44>, <&de_be_clk>,
1095   - <&dram_gates 26>;
1096   - clock-names = "ahb", "mod",
1097   - "ram";
1098   - resets = <&de_be_clk>;
1099   - status = "disabled";
1100   -
1101   - assigned-clocks = <&de_be_clk>;
1102   - assigned-clock-rates = <300000000>;
1103   -
1104   - ports {
1105   - #address-cells = <1>;
1106   - #size-cells = <0>;
1107   -
1108   - be0_in: port@0 {
1109   - #address-cells = <1>;
1110   - #size-cells = <0>;
1111   - reg = <0>;
1112   -
1113   - be0_in_fe0: endpoint@0 {
1114   - reg = <0>;
1115   - remote-endpoint = <&fe0_out_be0>;
1116   - };
1117   - };
1118   -
1119   - be0_out: port@1 {
1120   - #address-cells = <1>;
1121   - #size-cells = <0>;
1122   - reg = <1>;
1123   -
1124   - be0_out_tcon0: endpoint@0 {
1125   - reg = <0>;
1126   - remote-endpoint = <&tcon0_in_be0>;
1127   - };
1128   - };
1129   - };
1130   - };
  122 + uart1_cts_rts_pins_a: uart1-cts-rts@0 {
  123 + pins = "PG5", "PG6";
  124 + function = "uart1";
1131 125 };
1132 126 };
arch/arm/dts/sun5i-r8-chip.dts
Diff comments   View file @ 13b36fa
... ... @@ -56,25 +56,39 @@
56 56  
57 57 aliases {
58 58 i2c0 = &i2c0;
  59 + i2c1 = &i2c1;
59 60 i2c2 = &i2c2;
60 61 serial0 = &uart1;
61 62 serial1 = &uart3;
  63 + spi0 = &spi2;
62 64 };
63 65  
64 66 chosen {
65 67 stdout-path = "serial0:115200n8";
66 68 };
67 69  
68   - wifi_reg_on: wifi_reg_on {
69   - compatible = "regulator-fixed";
  70 + leds {
  71 + compatible = "gpio-leds";
  72 +
  73 + status {
  74 + label = "chip:white:status";
  75 + gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>;
  76 + default-state = "on";
  77 + };
  78 + };
  79 +
  80 + mmc0_pwrseq: mmc0_pwrseq {
  81 + compatible = "mmc-pwrseq-simple";
70 82 pinctrl-names = "default";
71 83 pinctrl-0 = <&chip_wifi_reg_on_pin>;
  84 + reset-gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; /* PC19 */
  85 + };
72 86  
73   - regulator-name = "wifi-reg-on";
74   - regulator-min-microvolt = <3300000>;
75   - regulator-max-microvolt = <3300000>;
76   - gpio = <&pio 2 19 GPIO_ACTIVE_HIGH>; /* PC19 */
77   - enable-active-high;
  87 + onewire {
  88 + compatible = "w1-gpio";
  89 + gpios = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */
  90 + pinctrl-names = "default";
  91 + pinctrl-0 = <&chip_w1_pin>;
78 92 };
79 93 };
80 94  
... ... @@ -114,6 +128,20 @@
114 128  
115 129 #include "axp209.dtsi"
116 130  
  131 +&ac_power_supply {
  132 + status = "okay";
  133 +};
  134 +
  135 +&battery_power_supply {
  136 + status = "okay";
  137 +};
  138 +
  139 +&i2c1 {
  140 + pinctrl-names = "default";
  141 + pinctrl-0 = <&i2c1_pins_a>;
  142 + status = "disabled";
  143 +};
  144 +
117 145 &i2c2 {
118 146 pinctrl-names = "default";
119 147 pinctrl-0 = <&i2c2_pins_a>;
120 148  
... ... @@ -134,13 +162,14 @@
134 162 };
135 163  
136 164 &mmc0_pins_a {
137   - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
  165 + bias-pull-up;
138 166 };
139 167  
140 168 &mmc0 {
141 169 pinctrl-names = "default";
142 170 pinctrl-0 = <&mmc0_pins_a>;
143   - vmmc-supply = <&wifi_reg_on>;
  171 + vmmc-supply = <&reg_vcc3v3>;
  172 + mmc-pwrseq = <&mmc0_pwrseq>;
144 173 bus-width = <4>;
145 174 non-removable;
146 175 status = "okay";
147 176  
148 177  
149 178  
... ... @@ -156,25 +185,25 @@
156 185  
157 186 &pio {
158 187 chip_vbus_pin: chip_vbus_pin@0 {
159   - allwinner,pins = "PB10";
160   - allwinner,function = "gpio_out";
161   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
162   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  188 + pins = "PB10";
  189 + function = "gpio_out";
163 190 };
164 191  
165 192 chip_wifi_reg_on_pin: chip_wifi_reg_on_pin@0 {
166   - allwinner,pins = "PC19";
167   - allwinner,function = "gpio_out";
168   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
169   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  193 + pins = "PC19";
  194 + function = "gpio_out";
170 195 };
171 196  
172 197 chip_id_det_pin: chip_id_det_pin@0 {
173   - allwinner,pins = "PG2";
174   - allwinner,function = "gpio_in";
175   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
176   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  198 + pins = "PG2";
  199 + function = "gpio_in";
177 200 };
  201 +
  202 + chip_w1_pin: chip_w1_pin@0 {
  203 + pins = "PD2";
  204 + function = "gpio_in";
  205 + bias-pull-up;
  206 + };
178 207 };
179 208  
180 209 &reg_dcdc2 {
181 210  
182 211  
... ... @@ -202,17 +231,25 @@
202 231 regulator-always-on;
203 232 };
204 233  
  234 +/*
  235 + * Both LDO3 and LDO4 are used in parallel to power up the WiFi/BT
  236 + * Chip.
  237 + *
  238 + * If those are not enabled, the SDIO part will not enumerate, and
  239 + * since there's no way currently to pass DT infos to an SDIO device,
  240 + * we cannot really do better than this ugly hack for now.
  241 + */
205 242 &reg_ldo3 {
206 243 regulator-min-microvolt = <3300000>;
207 244 regulator-max-microvolt = <3300000>;
208   - regulator-name = "vdd-wifi1";
  245 + regulator-name = "vcc-wifi-1";
209 246 regulator-always-on;
210 247 };
211 248  
212 249 &reg_ldo4 {
213 250 regulator-min-microvolt = <3300000>;
214 251 regulator-max-microvolt = <3300000>;
215   - regulator-name = "vdd-wifi2";
  252 + regulator-name = "vcc-wifi-2";
216 253 regulator-always-on;
217 254 };
218 255  
... ... @@ -229,6 +266,12 @@
229 266 status = "okay";
230 267 };
231 268  
  269 +&spi2 {
  270 + pinctrl-names = "default";
  271 + pinctrl-0 = <&spi2_pins_a>;
  272 + status = "disabled";
  273 +};
  274 +
232 275 &tcon0 {
233 276 status = "okay";
234 277 };
... ... @@ -246,7 +289,7 @@
246 289 &uart3 {
247 290 pinctrl-names = "default";
248 291 pinctrl-0 = <&uart3_pins_a>,
249   - <&uart3_pins_cts_rts_a>;
  292 + <&uart3_cts_rts_pins_a>;
250 293 status = "okay";
251 294 };
252 295  
arch/arm/dts/sun5i-r8.dtsi
Diff comments   View file @ 13b36fa
... ... @@ -44,45 +44,4 @@
44 44 */
45 45  
46 46 #include "sun5i-a13.dtsi"
47   -
48   -/ {
49   - chosen {
50   - framebuffer@1 {
51   - compatible = "allwinner,simple-framebuffer",
52   - "simple-framebuffer";
53   - allwinner,pipeline = "de_be0-lcd0-tve0";
54   - clocks = <&ahb_gates 34>, <&ahb_gates 36>,
55   - <&ahb_gates 44>, <&de_be_clk>,
56   - <&tcon_ch1_clk>, <&dram_gates 26>;
57   - status = "disabled";
58   - };
59   - };
60   -
61   - soc@01c00000 {
62   - tve0: tv-encoder@01c0a000 {
63   - compatible = "allwinner,sun4i-a10-tv-encoder";
64   - reg = <0x01c0a000 0x1000>;
65   - clocks = <&ahb_gates 34>;
66   - resets = <&tcon_ch0_clk 0>;
67   - status = "disabled";
68   -
69   - port {
70   - #address-cells = <1>;
71   - #size-cells = <0>;
72   -
73   - tve0_in_tcon0: endpoint@0 {
74   - reg = <0>;
75   - remote-endpoint = <&tcon0_out_tve0>;
76   - };
77   - };
78   - };
79   - };
80   -};
81   -
82   -&tcon0_out {
83   - tcon0_out_tve0: endpoint@1 {
84   - reg = <1>;
85   - remote-endpoint = <&tve0_in_tcon0>;
86   - };
87   -};
arch/arm/dts/sun5i-reference-design-tablet.dtsi
Diff comments   View file @ 13b36fa
... ... @@ -41,6 +41,7 @@
41 41 */
42 42 #include "sunxi-reference-design-tablet.dtsi"
43 43  
  44 +#include <dt-bindings/interrupt-controller/irq.h>
44 45 #include <dt-bindings/pwm/pwm.h>
45 46  
46 47 / {
... ... @@ -84,6 +85,23 @@
84 85 };
85 86  
86 87 &i2c1 {
  88 + /*
  89 + * The gsl1680 is rated at 400KHz and it will not work reliable at
  90 + * 100KHz, this has been confirmed on multiple different q8 tablets.
  91 + * All other devices on this bus are also rated for 400KHz.
  92 + */
  93 + clock-frequency = <400000>;
  94 +
  95 + touchscreen: touchscreen {
  96 + interrupt-parent = <&pio>;
  97 + interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>; /* EINT11 (PG11) */
  98 + pinctrl-names = "default";
  99 + pinctrl-0 = <&ts_power_pin>;
  100 + power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
  101 + /* Tablet dts must provide reg and compatible */
  102 + status = "disabled";
  103 + };
  104 +
87 105 pcf8563: rtc@51 {
88 106 compatible = "nxp,pcf8563";
89 107 reg = <0x51>;
... ... @@ -92,6 +110,14 @@
92 110  
93 111 #include "axp209.dtsi"
94 112  
  113 +&ac_power_supply {
  114 + status = "okay";
  115 +};
  116 +
  117 +&battery_power_supply {
  118 + status = "okay";
  119 +};
  120 +
95 121 &lradc {
96 122 vref-supply = <&reg_ldo2>;
97 123 };
... ... @@ -101,8 +127,7 @@
101 127 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
102 128 vmmc-supply = <&reg_vcc3v0>;
103 129 bus-width = <4>;
104   - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
105   - cd-inverted;
  130 + cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
106 131 status = "okay";
107 132 };
108 133  
109 134  
110 135  
111 136  
112 137  
113 138  
... ... @@ -112,38 +137,38 @@
112 137  
113 138 &pio {
114 139 codec_pa_pin: codec_pa_pin@0 {
115   - allwinner,pins = "PG10";
116   - allwinner,function = "gpio_out";
117   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
118   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  140 + pins = "PG10";
  141 + function = "gpio_out";
119 142 };
120 143  
121 144 mmc0_cd_pin: mmc0_cd_pin@0 {
122   - allwinner,pins = "PG0";
123   - allwinner,function = "gpio_in";
124   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
125   - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
  145 + pins = "PG0";
  146 + function = "gpio_in";
  147 + bias-pull-up;
126 148 };
127 149  
  150 + ts_power_pin: ts_power_pin {
  151 + pins = "PB3";
  152 + function = "gpio_out";
  153 + drive-strength = <10>;
  154 + bias-disable;
  155 + };
  156 +
128 157 usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
129   - allwinner,pins = "PG1";
130   - allwinner,function = "gpio_in";
131   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
132   - allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
  158 + pins = "PG1";
  159 + function = "gpio_in";
  160 + bias-pull-down;
133 161 };
134 162  
135 163 usb0_id_detect_pin: usb0_id_detect_pin@0 {
136   - allwinner,pins = "PG2";
137   - allwinner,function = "gpio_in";
138   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
139   - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
  164 + pins = "PG2";
  165 + function = "gpio_in";
  166 + bias-pull-up;
140 167 };
141 168  
142 169 usb0_vbus_pin_a: usb0_vbus_pin@0 {
143   - allwinner,pins = "PG12";
144   - allwinner,function = "gpio_out";
145   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
146   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  170 + pins = "PG12";
  171 + function = "gpio_out";
147 172 };
148 173 };
149 174  
arch/arm/dts/sun5i.dtsi
Diff comments   View file @ 13b36fa
Changes suppressed. Click to show
... ... @@ -44,9 +44,9 @@
44 44  
45 45 #include "skeleton.dtsi"
46 46  
47   -#include <dt-bindings/clock/sun4i-a10-pll2.h>
  47 +#include <dt-bindings/clock/sun5i-ccu.h>
48 48 #include <dt-bindings/dma/sun4i-a10.h>
49   -#include <dt-bindings/pinctrl/sun4i-a10.h>
  49 +#include <dt-bindings/reset/sun5i-ccu.h>
50 50  
51 51 / {
52 52 interrupt-parent = <&intc>;
53 53  
54 54  
55 55  
56 56  
57 57  
58 58  
59 59  
60 60  
61 61  
... ... @@ -59,316 +59,69 @@
59 59 device_type = "cpu";
60 60 compatible = "arm,cortex-a8";
61 61 reg = <0x0>;
62   - clocks = <&cpu>;
  62 + clocks = <&ccu CLK_CPU>;
63 63 };
64 64 };
65 65  
66   - clocks {
  66 + chosen {
67 67 #address-cells = <1>;
68 68 #size-cells = <1>;
69 69 ranges;
70 70  
71   - /*
72   - * This is a dummy clock, to be used as placeholder on
73   - * other mux clocks when a specific parent clock is not
74   - * yet implemented. It should be dropped when the driver
75   - * is complete.
76   - */
77   - dummy: dummy {
78   - #clock-cells = <0>;
79   - compatible = "fixed-clock";
80   - clock-frequency = <0>;
  71 + framebuffer@0 {
  72 + compatible = "allwinner,simple-framebuffer",
  73 + "simple-framebuffer";
  74 + allwinner,pipeline = "de_be0-lcd0";
  75 + clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
  76 + <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
  77 + status = "disabled";
81 78 };
82 79  
83   - osc24M: clk@01c20050 {
  80 + framebuffer@1 {
  81 + compatible = "allwinner,simple-framebuffer",
  82 + "simple-framebuffer";
  83 + allwinner,pipeline = "de_be0-lcd0-tve0";
  84 + clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
  85 + <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
  86 + <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
  87 + status = "disabled";
  88 + };
  89 + };
  90 +
  91 + clocks {
  92 + #address-cells = <1>;
  93 + #size-cells = <1>;
  94 + ranges;
  95 +
  96 + osc24M: clk@1c20050 {
84 97 #clock-cells = <0>;
85   - compatible = "allwinner,sun4i-a10-osc-clk";
86   - reg = <0x01c20050 0x4>;
  98 + compatible = "fixed-clock";
87 99 clock-frequency = <24000000>;
88 100 clock-output-names = "osc24M";
89 101 };
90 102  
91   - osc3M: osc3M_clk {
92   - compatible = "fixed-factor-clock";
93   - #clock-cells = <0>;
94   - clock-div = <8>;
95   - clock-mult = <1>;
96   - clocks = <&osc24M>;
97   - clock-output-names = "osc3M";
98   - };
99   -
100 103 osc32k: clk@0 {
101 104 #clock-cells = <0>;
102 105 compatible = "fixed-clock";
103 106 clock-frequency = <32768>;
104 107 clock-output-names = "osc32k";
105 108 };
106   -
107   - pll1: clk@01c20000 {
108   - #clock-cells = <0>;
109   - compatible = "allwinner,sun4i-a10-pll1-clk";
110   - reg = <0x01c20000 0x4>;
111   - clocks = <&osc24M>;
112   - clock-output-names = "pll1";
113   - };
114   -
115   - pll2: clk@01c20008 {
116   - #clock-cells = <1>;
117   - compatible = "allwinner,sun5i-a13-pll2-clk";
118   - reg = <0x01c20008 0x8>;
119   - clocks = <&osc24M>;
120   - clock-output-names = "pll2-1x", "pll2-2x",
121   - "pll2-4x", "pll2-8x";
122   - };
123   -
124   - pll3: clk@01c20010 {
125   - #clock-cells = <0>;
126   - compatible = "allwinner,sun4i-a10-pll3-clk";
127   - reg = <0x01c20010 0x4>;
128   - clocks = <&osc3M>;
129   - clock-output-names = "pll3";
130   - };
131   -
132   - pll3x2: pll3x2_clk {
133   - compatible = "allwinner,sun4i-a10-pll3-2x-clk", "fixed-factor-clock";
134   - #clock-cells = <0>;
135   - clock-div = <1>;
136   - clock-mult = <2>;
137   - clocks = <&pll3>;
138   - clock-output-names = "pll3-2x";
139   - };
140   -
141   - pll4: clk@01c20018 {
142   - #clock-cells = <0>;
143   - compatible = "allwinner,sun4i-a10-pll1-clk";
144   - reg = <0x01c20018 0x4>;
145   - clocks = <&osc24M>;
146   - clock-output-names = "pll4";
147   - };
148   -
149   - pll5: clk@01c20020 {
150   - #clock-cells = <1>;
151   - compatible = "allwinner,sun4i-a10-pll5-clk";
152   - reg = <0x01c20020 0x4>;
153   - clocks = <&osc24M>;
154   - clock-output-names = "pll5_ddr", "pll5_other";
155   - };
156   -
157   - pll6: clk@01c20028 {
158   - #clock-cells = <1>;
159   - compatible = "allwinner,sun4i-a10-pll6-clk";
160   - reg = <0x01c20028 0x4>;
161   - clocks = <&osc24M>;
162   - clock-output-names = "pll6_sata", "pll6_other", "pll6";
163   - };
164   -
165   - pll7: clk@01c20030 {
166   - #clock-cells = <0>;
167   - compatible = "allwinner,sun4i-a10-pll3-clk";
168   - reg = <0x01c20030 0x4>;
169   - clocks = <&osc3M>;
170   - clock-output-names = "pll7";
171   - };
172   -
173   - pll7x2: pll7x2_clk {
174   - compatible = "fixed-factor-clock";
175   - #clock-cells = <0>;
176   - clock-div = <1>;
177   - clock-mult = <2>;
178   - clocks = <&pll7>;
179   - clock-output-names = "pll7-2x";
180   - };
181   -
182   - /* dummy is 200M */
183   - cpu: cpu@01c20054 {
184   - #clock-cells = <0>;
185   - compatible = "allwinner,sun4i-a10-cpu-clk";
186   - reg = <0x01c20054 0x4>;
187   - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
188   - clock-output-names = "cpu";
189   - };
190   -
191   - axi: axi@01c20054 {
192   - #clock-cells = <0>;
193   - compatible = "allwinner,sun4i-a10-axi-clk";
194   - reg = <0x01c20054 0x4>;
195   - clocks = <&cpu>;
196   - clock-output-names = "axi";
197   - };
198   -
199   - ahb: ahb@01c20054 {
200   - #clock-cells = <0>;
201   - compatible = "allwinner,sun5i-a13-ahb-clk";
202   - reg = <0x01c20054 0x4>;
203   - clocks = <&axi>, <&cpu>, <&pll6 1>;
204   - clock-output-names = "ahb";
205   - /*
206   - * Use PLL6 as parent, instead of CPU/AXI
207   - * which has rate changes due to cpufreq
208   - */
209   - assigned-clocks = <&ahb>;
210   - assigned-clock-parents = <&pll6 1>;
211   - };
212   -
213   - apb0: apb0@01c20054 {
214   - #clock-cells = <0>;
215   - compatible = "allwinner,sun4i-a10-apb0-clk";
216   - reg = <0x01c20054 0x4>;
217   - clocks = <&ahb>;
218   - clock-output-names = "apb0";
219   - };
220   -
221   - apb1: clk@01c20058 {
222   - #clock-cells = <0>;
223   - compatible = "allwinner,sun4i-a10-apb1-clk";
224   - reg = <0x01c20058 0x4>;
225   - clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
226   - clock-output-names = "apb1";
227   - };
228   -
229   - axi_gates: clk@01c2005c {
230   - #clock-cells = <1>;
231   - compatible = "allwinner,sun4i-a10-axi-gates-clk";
232   - reg = <0x01c2005c 0x4>;
233   - clocks = <&axi>;
234   - clock-indices = <0>;
235   - clock-output-names = "axi_dram";
236   - };
237   -
238   - nand_clk: clk@01c20080 {
239   - #clock-cells = <0>;
240   - compatible = "allwinner,sun4i-a10-mod0-clk";
241   - reg = <0x01c20080 0x4>;
242   - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
243   - clock-output-names = "nand";
244   - };
245   -
246   - ms_clk: clk@01c20084 {
247   - #clock-cells = <0>;
248   - compatible = "allwinner,sun4i-a10-mod0-clk";
249   - reg = <0x01c20084 0x4>;
250   - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
251   - clock-output-names = "ms";
252   - };
253   -
254   - mmc0_clk: clk@01c20088 {
255   - #clock-cells = <1>;
256   - compatible = "allwinner,sun4i-a10-mmc-clk";
257   - reg = <0x01c20088 0x4>;
258   - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
259   - clock-output-names = "mmc0",
260   - "mmc0_output",
261   - "mmc0_sample";
262   - };
263   -
264   - mmc1_clk: clk@01c2008c {
265   - #clock-cells = <1>;
266   - compatible = "allwinner,sun4i-a10-mmc-clk";
267   - reg = <0x01c2008c 0x4>;
268   - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
269   - clock-output-names = "mmc1",
270   - "mmc1_output",
271   - "mmc1_sample";
272   - };
273   -
274   - mmc2_clk: clk@01c20090 {
275   - #clock-cells = <1>;
276   - compatible = "allwinner,sun4i-a10-mmc-clk";
277   - reg = <0x01c20090 0x4>;
278   - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
279   - clock-output-names = "mmc2",
280   - "mmc2_output",
281   - "mmc2_sample";
282   - };
283   -
284   - ts_clk: clk@01c20098 {
285   - #clock-cells = <0>;
286   - compatible = "allwinner,sun4i-a10-mod0-clk";
287   - reg = <0x01c20098 0x4>;
288   - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
289   - clock-output-names = "ts";
290   - };
291   -
292   - ss_clk: clk@01c2009c {
293   - #clock-cells = <0>;
294   - compatible = "allwinner,sun4i-a10-mod0-clk";
295   - reg = <0x01c2009c 0x4>;
296   - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
297   - clock-output-names = "ss";
298   - };
299   -
300   - spi0_clk: clk@01c200a0 {
301   - #clock-cells = <0>;
302   - compatible = "allwinner,sun4i-a10-mod0-clk";
303   - reg = <0x01c200a0 0x4>;
304   - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
305   - clock-output-names = "spi0";
306   - };
307   -
308   - spi1_clk: clk@01c200a4 {
309   - #clock-cells = <0>;
310   - compatible = "allwinner,sun4i-a10-mod0-clk";
311   - reg = <0x01c200a4 0x4>;
312   - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
313   - clock-output-names = "spi1";
314   - };
315   -
316   - spi2_clk: clk@01c200a8 {
317   - #clock-cells = <0>;
318   - compatible = "allwinner,sun4i-a10-mod0-clk";
319   - reg = <0x01c200a8 0x4>;
320   - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
321   - clock-output-names = "spi2";
322   - };
323   -
324   - ir0_clk: clk@01c200b0 {
325   - #clock-cells = <0>;
326   - compatible = "allwinner,sun4i-a10-mod0-clk";
327   - reg = <0x01c200b0 0x4>;
328   - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
329   - clock-output-names = "ir0";
330   - };
331   -
332   - usb_clk: clk@01c200cc {
333   - #clock-cells = <1>;
334   - #reset-cells = <1>;
335   - compatible = "allwinner,sun5i-a13-usb-clk";
336   - reg = <0x01c200cc 0x4>;
337   - clocks = <&pll6 1>;
338   - clock-output-names = "usb_ohci0", "usb_phy";
339   - };
340   -
341   - codec_clk: clk@01c20140 {
342   - #clock-cells = <0>;
343   - compatible = "allwinner,sun4i-a10-codec-clk";
344   - reg = <0x01c20140 0x4>;
345   - clocks = <&pll2 SUN4I_A10_PLL2_1X>;
346   - clock-output-names = "codec";
347   - };
348   -
349   - mbus_clk: clk@01c2015c {
350   - #clock-cells = <0>;
351   - compatible = "allwinner,sun5i-a13-mbus-clk";
352   - reg = <0x01c2015c 0x4>;
353   - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
354   - clock-output-names = "mbus";
355   - };
356 109 };
357 110  
358   - soc@01c00000 {
  111 + soc@1c00000 {
359 112 compatible = "simple-bus";
360 113 #address-cells = <1>;
361 114 #size-cells = <1>;
362 115 ranges;
363 116  
364   - sram-controller@01c00000 {
  117 + sram-controller@1c00000 {
365 118 compatible = "allwinner,sun4i-a10-sram-controller";
366 119 reg = <0x01c00000 0x30>;
367 120 #address-cells = <1>;
368 121 #size-cells = <1>;
369 122 ranges;
370 123  
371   - sram_a: sram@00000000 {
  124 + sram_a: sram@0 {
372 125 compatible = "mmio-sram";
373 126 reg = <0x00000000 0xc000>;
374 127 #address-cells = <1>;
375 128  
... ... @@ -376,14 +129,20 @@
376 129 ranges = <0 0x00000000 0xc000>;
377 130 };
378 131  
379   - sram_d: sram@00010000 {
  132 + emac_sram: sram-section@8000 {
  133 + compatible = "allwinner,sun4i-a10-sram-a3-a4";
  134 + reg = <0x8000 0x4000>;
  135 + status = "disabled";
  136 + };
  137 +
  138 + sram_d: sram@10000 {
380 139 compatible = "mmio-sram";
381 140 reg = <0x00010000 0x1000>;
382 141 #address-cells = <1>;
383 142 #size-cells = <1>;
384 143 ranges = <0 0x00010000 0x1000>;
385 144  
386   - otg_sram: sram-section@0000 {
  145 + otg_sram: sram-section@0 {
387 146 compatible = "allwinner,sun4i-a10-sram-d";
388 147 reg = <0x0000 0x1000>;
389 148 status = "disabled";
390 149  
391 150  
392 151  
... ... @@ -391,19 +150,32 @@
391 150 };
392 151 };
393 152  
394   - dma: dma-controller@01c02000 {
  153 + dma: dma-controller@1c02000 {
395 154 compatible = "allwinner,sun4i-a10-dma";
396 155 reg = <0x01c02000 0x1000>;
397 156 interrupts = <27>;
398   - clocks = <&ahb_gates 6>;
  157 + clocks = <&ccu CLK_AHB_DMA>;
399 158 #dma-cells = <2>;
400 159 };
401 160  
402   - spi0: spi@01c05000 {
  161 + nfc: nand@1c03000 {
  162 + compatible = "allwinner,sun4i-a10-nand";
  163 + reg = <0x01c03000 0x1000>;
  164 + interrupts = <37>;
  165 + clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
  166 + clock-names = "ahb", "mod";
  167 + dmas = <&dma SUN4I_DMA_DEDICATED 3>;
  168 + dma-names = "rxtx";
  169 + status = "disabled";
  170 + #address-cells = <1>;
  171 + #size-cells = <0>;
  172 + };
  173 +
  174 + spi0: spi@1c05000 {
403 175 compatible = "allwinner,sun4i-a10-spi";
404 176 reg = <0x01c05000 0x1000>;
405 177 interrupts = <10>;
406   - clocks = <&ahb_gates 20>, <&spi0_clk>;
  178 + clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
407 179 clock-names = "ahb", "mod";
408 180 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
409 181 <&dma SUN4I_DMA_DEDICATED 26>;
410 182  
... ... @@ -413,11 +185,11 @@
413 185 #size-cells = <0>;
414 186 };
415 187  
416   - spi1: spi@01c06000 {
  188 + spi1: spi@1c06000 {
417 189 compatible = "allwinner,sun4i-a10-spi";
418 190 reg = <0x01c06000 0x1000>;
419 191 interrupts = <11>;
420   - clocks = <&ahb_gates 21>, <&spi1_clk>;
  192 + clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
421 193 clock-names = "ahb", "mod";
422 194 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
423 195 <&dma SUN4I_DMA_DEDICATED 8>;
424 196  
425 197  
426 198  
427 199  
428 200  
429 201  
430 202  
... ... @@ -427,61 +199,122 @@
427 199 #size-cells = <0>;
428 200 };
429 201  
430   - mmc0: mmc@01c0f000 {
  202 + tve0: tv-encoder@1c0a000 {
  203 + compatible = "allwinner,sun4i-a10-tv-encoder";
  204 + reg = <0x01c0a000 0x1000>;
  205 + clocks = <&ccu CLK_AHB_TVE>;
  206 + resets = <&ccu RST_TVE>;
  207 + status = "disabled";
  208 +
  209 + port {
  210 + #address-cells = <1>;
  211 + #size-cells = <0>;
  212 +
  213 + tve0_in_tcon0: endpoint@0 {
  214 + reg = <0>;
  215 + remote-endpoint = <&tcon0_out_tve0>;
  216 + };
  217 + };
  218 + };
  219 +
  220 + emac: ethernet@1c0b000 {
  221 + compatible = "allwinner,sun4i-a10-emac";
  222 + reg = <0x01c0b000 0x1000>;
  223 + interrupts = <55>;
  224 + clocks = <&ccu CLK_AHB_EMAC>;
  225 + allwinner,sram = <&emac_sram 1>;
  226 + status = "disabled";
  227 + };
  228 +
  229 + mdio: mdio@1c0b080 {
  230 + compatible = "allwinner,sun4i-a10-mdio";
  231 + reg = <0x01c0b080 0x14>;
  232 + status = "disabled";
  233 + #address-cells = <1>;
  234 + #size-cells = <0>;
  235 + };
  236 +
  237 + tcon0: lcd-controller@1c0c000 {
  238 + compatible = "allwinner,sun5i-a13-tcon";
  239 + reg = <0x01c0c000 0x1000>;
  240 + interrupts = <44>;
  241 + resets = <&ccu RST_LCD>;
  242 + reset-names = "lcd";
  243 + clocks = <&ccu CLK_AHB_LCD>,
  244 + <&ccu CLK_TCON_CH0>,
  245 + <&ccu CLK_TCON_CH1>;
  246 + clock-names = "ahb",
  247 + "tcon-ch0",
  248 + "tcon-ch1";
  249 + clock-output-names = "tcon-pixel-clock";
  250 + status = "disabled";
  251 +
  252 + ports {
  253 + #address-cells = <1>;
  254 + #size-cells = <0>;
  255 +
  256 + tcon0_in: port@0 {
  257 + #address-cells = <1>;
  258 + #size-cells = <0>;
  259 + reg = <0>;
  260 +
  261 + tcon0_in_be0: endpoint@0 {
  262 + reg = <0>;
  263 + remote-endpoint = <&be0_out_tcon0>;
  264 + };
  265 + };
  266 +
  267 + tcon0_out: port@1 {
  268 + #address-cells = <1>;
  269 + #size-cells = <0>;
  270 + reg = <1>;
  271 +
  272 + tcon0_out_tve0: endpoint@1 {
  273 + reg = <1>;
  274 + remote-endpoint = <&tve0_in_tcon0>;
  275 + allwinner,tcon-channel = <1>;
  276 + };
  277 + };
  278 + };
  279 + };
  280 +
  281 + mmc0: mmc@1c0f000 {
431 282 compatible = "allwinner,sun5i-a13-mmc";
432 283 reg = <0x01c0f000 0x1000>;
433   - clocks = <&ahb_gates 8>,
434   - <&mmc0_clk 0>,
435   - <&mmc0_clk 1>,
436   - <&mmc0_clk 2>;
437   - clock-names = "ahb",
438   - "mmc",
439   - "output",
440   - "sample";
  284 + clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
  285 + clock-names = "ahb", "mmc";
441 286 interrupts = <32>;
442 287 status = "disabled";
443 288 #address-cells = <1>;
444 289 #size-cells = <0>;
445 290 };
446 291  
447   - mmc1: mmc@01c10000 {
  292 + mmc1: mmc@1c10000 {
448 293 compatible = "allwinner,sun5i-a13-mmc";
449 294 reg = <0x01c10000 0x1000>;
450   - clocks = <&ahb_gates 9>,
451   - <&mmc1_clk 0>,
452   - <&mmc1_clk 1>,
453   - <&mmc1_clk 2>;
454   - clock-names = "ahb",
455   - "mmc",
456   - "output",
457   - "sample";
  295 + clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
  296 + clock-names = "ahb", "mmc";
458 297 interrupts = <33>;
459 298 status = "disabled";
460 299 #address-cells = <1>;
461 300 #size-cells = <0>;
462 301 };
463 302  
464   - mmc2: mmc@01c11000 {
  303 + mmc2: mmc@1c11000 {
465 304 compatible = "allwinner,sun5i-a13-mmc";
466 305 reg = <0x01c11000 0x1000>;
467   - clocks = <&ahb_gates 10>,
468   - <&mmc2_clk 0>,
469   - <&mmc2_clk 1>,
470   - <&mmc2_clk 2>;
471   - clock-names = "ahb",
472   - "mmc",
473   - "output",
474   - "sample";
  306 + clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
  307 + clock-names = "ahb", "mmc";
475 308 interrupts = <34>;
476 309 status = "disabled";
477 310 #address-cells = <1>;
478 311 #size-cells = <0>;
479 312 };
480 313  
481   - usb_otg: usb@01c13000 {
  314 + usb_otg: usb@1c13000 {
482 315 compatible = "allwinner,sun4i-a10-musb";
483 316 reg = <0x01c13000 0x0400>;
484   - clocks = <&ahb_gates 0>;
  317 + clocks = <&ccu CLK_AHB_OTG>;
485 318 interrupts = <38>;
486 319 interrupt-names = "mc";
487 320 phys = <&usbphy 0>;
488 321  
489 322  
490 323  
491 324  
492 325  
493 326  
494 327  
495 328  
... ... @@ -491,43 +324,52 @@
491 324 status = "disabled";
492 325 };
493 326  
494   - usbphy: phy@01c13400 {
  327 + usbphy: phy@1c13400 {
495 328 #phy-cells = <1>;
496 329 compatible = "allwinner,sun5i-a13-usb-phy";
497 330 reg = <0x01c13400 0x10 0x01c14800 0x4>;
498 331 reg-names = "phy_ctrl", "pmu1";
499   - clocks = <&usb_clk 8>;
  332 + clocks = <&ccu CLK_USB_PHY0>;
500 333 clock-names = "usb_phy";
501   - resets = <&usb_clk 0>, <&usb_clk 1>;
  334 + resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
502 335 reset-names = "usb0_reset", "usb1_reset";
503 336 status = "disabled";
504 337 };
505 338  
506   - ehci0: usb@01c14000 {
  339 + ehci0: usb@1c14000 {
507 340 compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
508 341 reg = <0x01c14000 0x100>;
509 342 interrupts = <39>;
510   - clocks = <&ahb_gates 1>;
  343 + clocks = <&ccu CLK_AHB_EHCI>;
511 344 phys = <&usbphy 1>;
512 345 phy-names = "usb";
513 346 status = "disabled";
514 347 };
515 348  
516   - ohci0: usb@01c14400 {
  349 + ohci0: usb@1c14400 {
517 350 compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
518 351 reg = <0x01c14400 0x100>;
519 352 interrupts = <40>;
520   - clocks = <&usb_clk 6>, <&ahb_gates 2>;
  353 + clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
521 354 phys = <&usbphy 1>;
522 355 phy-names = "usb";
523 356 status = "disabled";
524 357 };
525 358  
526   - spi2: spi@01c17000 {
  359 + crypto: crypto-engine@1c15000 {
  360 + compatible = "allwinner,sun5i-a13-crypto",
  361 + "allwinner,sun4i-a10-crypto";
  362 + reg = <0x01c15000 0x1000>;
  363 + interrupts = <54>;
  364 + clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
  365 + clock-names = "ahb", "mod";
  366 + };
  367 +
  368 + spi2: spi@1c17000 {
527 369 compatible = "allwinner,sun4i-a10-spi";
528 370 reg = <0x01c17000 0x1000>;
529 371 interrupts = <12>;
530   - clocks = <&ahb_gates 22>, <&spi2_clk>;
  372 + clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
531 373 clock-names = "ahb", "mod";
532 374 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
533 375 <&dma SUN4I_DMA_DEDICATED 28>;
534 376  
535 377  
536 378  
537 379  
538 380  
539 381  
540 382  
541 383  
542 384  
543 385  
544 386  
545 387  
546 388  
547 389  
548 390  
549 391  
550 392  
551 393  
552 394  
... ... @@ -537,107 +379,199 @@
537 379 #size-cells = <0>;
538 380 };
539 381  
540   - intc: interrupt-controller@01c20400 {
  382 + ccu: clock@1c20000 {
  383 + reg = <0x01c20000 0x400>;
  384 + clocks = <&osc24M>, <&osc32k>;
  385 + clock-names = "hosc", "losc";
  386 + #clock-cells = <1>;
  387 + #reset-cells = <1>;
  388 + };
  389 +
  390 + intc: interrupt-controller@1c20400 {
541 391 compatible = "allwinner,sun4i-a10-ic";
542 392 reg = <0x01c20400 0x400>;
543 393 interrupt-controller;
544 394 #interrupt-cells = <1>;
545 395 };
546 396  
547   - pio: pinctrl@01c20800 {
  397 + pio: pinctrl@1c20800 {
548 398 reg = <0x01c20800 0x400>;
549 399 interrupts = <28>;
550   - clocks = <&apb0_gates 5>;
  400 + clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
  401 + clock-names = "apb", "hosc", "losc";
551 402 gpio-controller;
552 403 interrupt-controller;
553 404 #interrupt-cells = <3>;
554 405 #gpio-cells = <3>;
555 406  
  407 + emac_pins_a: emac0@0 {
  408 + pins = "PD6", "PD7", "PD10",
  409 + "PD11", "PD12", "PD13", "PD14",
  410 + "PD15", "PD18", "PD19", "PD20",
  411 + "PD21", "PD22", "PD23", "PD24",
  412 + "PD25", "PD26", "PD27";
  413 + function = "emac";
  414 + };
  415 +
556 416 i2c0_pins_a: i2c0@0 {
557   - allwinner,pins = "PB0", "PB1";
558   - allwinner,function = "i2c0";
559   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
560   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  417 + pins = "PB0", "PB1";
  418 + function = "i2c0";
561 419 };
562 420  
563 421 i2c1_pins_a: i2c1@0 {
564   - allwinner,pins = "PB15", "PB16";
565   - allwinner,function = "i2c1";
566   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
567   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  422 + pins = "PB15", "PB16";
  423 + function = "i2c1";
568 424 };
569 425  
570 426 i2c2_pins_a: i2c2@0 {
571   - allwinner,pins = "PB17", "PB18";
572   - allwinner,function = "i2c2";
573   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
574   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  427 + pins = "PB17", "PB18";
  428 + function = "i2c2";
575 429 };
576 430  
  431 + ir0_rx_pins_a: ir0@0 {
  432 + pins = "PB4";
  433 + function = "ir0";
  434 + };
  435 +
  436 + lcd_rgb565_pins: lcd_rgb565@0 {
  437 + pins = "PD3", "PD4", "PD5", "PD6", "PD7",
  438 + "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
  439 + "PD19", "PD20", "PD21", "PD22", "PD23",
  440 + "PD24", "PD25", "PD26", "PD27";
  441 + function = "lcd0";
  442 + };
  443 +
  444 + lcd_rgb666_pins: lcd_rgb666@0 {
  445 + pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
  446 + "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
  447 + "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
  448 + "PD24", "PD25", "PD26", "PD27";
  449 + function = "lcd0";
  450 + };
  451 +
577 452 mmc0_pins_a: mmc0@0 {
578   - allwinner,pins = "PF0", "PF1", "PF2", "PF3",
579   - "PF4", "PF5";
580   - allwinner,function = "mmc0";
581   - allwinner,drive = <SUN4I_PINCTRL_30_MA>;
582   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  453 + pins = "PF0", "PF1", "PF2", "PF3",
  454 + "PF4", "PF5";
  455 + function = "mmc0";
  456 + drive-strength = <30>;
  457 + bias-pull-up;
583 458 };
584 459  
585 460 mmc2_pins_a: mmc2@0 {
586   - allwinner,pins = "PC6", "PC7", "PC8", "PC9",
587   - "PC10", "PC11", "PC12", "PC13",
588   - "PC14", "PC15";
589   - allwinner,function = "mmc2";
590   - allwinner,drive = <SUN4I_PINCTRL_30_MA>;
591   - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
  461 + pins = "PC6", "PC7", "PC8", "PC9",
  462 + "PC10", "PC11", "PC12", "PC13",
  463 + "PC14", "PC15";
  464 + function = "mmc2";
  465 + drive-strength = <30>;
  466 + bias-pull-up;
592 467 };
593 468  
  469 + mmc2_4bit_pins_a: mmc2-4bit@0 {
  470 + pins = "PC6", "PC7", "PC8", "PC9",
  471 + "PC10", "PC11";
  472 + function = "mmc2";
  473 + drive-strength = <30>;
  474 + bias-pull-up;
  475 + };
  476 +
  477 + nand_pins_a: nand-base0@0 {
  478 + pins = "PC0", "PC1", "PC2",
  479 + "PC5", "PC8", "PC9", "PC10",
  480 + "PC11", "PC12", "PC13", "PC14",
  481 + "PC15";
  482 + function = "nand0";
  483 + };
  484 +
  485 + nand_cs0_pins_a: nand-cs@0 {
  486 + pins = "PC4";
  487 + function = "nand0";
  488 + };
  489 +
  490 + nand_rb0_pins_a: nand-rb@0 {
  491 + pins = "PC6";
  492 + function = "nand0";
  493 + };
  494 +
  495 + spi2_pins_a: spi2@0 {
  496 + pins = "PE1", "PE2", "PE3";
  497 + function = "spi2";
  498 + };
  499 +
  500 + spi2_cs0_pins_a: spi2-cs0@0 {
  501 + pins = "PE0";
  502 + function = "spi2";
  503 + };
  504 +
  505 + uart1_pins_a: uart1@0 {
  506 + pins = "PE10", "PE11";
  507 + function = "uart1";
  508 + };
  509 +
  510 + uart1_pins_b: uart1@1 {
  511 + pins = "PG3", "PG4";
  512 + function = "uart1";
  513 + };
  514 +
  515 + uart2_pins_a: uart2@0 {
  516 + pins = "PD2", "PD3";
  517 + function = "uart2";
  518 + };
  519 +
  520 + uart2_cts_rts_pins_a: uart2-cts-rts@0 {
  521 + pins = "PD4", "PD5";
  522 + function = "uart2";
  523 + };
  524 +
594 525 uart3_pins_a: uart3@0 {
595   - allwinner,pins = "PG9", "PG10";
596   - allwinner,function = "uart3";
597   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
598   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  526 + pins = "PG9", "PG10";
  527 + function = "uart3";
599 528 };
600 529  
601   - uart3_pins_cts_rts_a: uart3-cts-rts@0 {
602   - allwinner,pins = "PG11", "PG12";
603   - allwinner,function = "uart3";
604   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
605   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  530 + uart3_cts_rts_pins_a: uart3-cts-rts@0 {
  531 + pins = "PG11", "PG12";
  532 + function = "uart3";
606 533 };
607 534  
608 535 pwm0_pins: pwm0 {
609   - allwinner,pins = "PB2";
610   - allwinner,function = "pwm";
611   - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
612   - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  536 + pins = "PB2";
  537 + function = "pwm";
613 538 };
614 539 };
615 540  
616   - timer@01c20c00 {
  541 + timer@1c20c00 {
617 542 compatible = "allwinner,sun4i-a10-timer";
618 543 reg = <0x01c20c00 0x90>;
619 544 interrupts = <22>;
620   - clocks = <&osc24M>;
  545 + clocks = <&ccu CLK_HOSC>;
621 546 };
622 547  
623   - wdt: watchdog@01c20c90 {
  548 + wdt: watchdog@1c20c90 {
624 549 compatible = "allwinner,sun4i-a10-wdt";
625 550 reg = <0x01c20c90 0x10>;
626 551 };
627 552  
628   - lradc: lradc@01c22800 {
  553 + ir0: ir@1c21800 {
  554 + compatible = "allwinner,sun4i-a10-ir";
  555 + clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>;
  556 + clock-names = "apb", "ir";
  557 + interrupts = <5>;
  558 + reg = <0x01c21800 0x40>;
  559 + status = "disabled";
  560 + };
  561 +
  562 + lradc: lradc@1c22800 {
629 563 compatible = "allwinner,sun4i-a10-lradc-keys";
630 564 reg = <0x01c22800 0x100>;
631 565 interrupts = <31>;
632 566 status = "disabled";
633 567 };
634 568  
635   - codec: codec@01c22c00 {
  569 + codec: codec@1c22c00 {
636 570 #sound-dai-cells = <0>;
637 571 compatible = "allwinner,sun4i-a10-codec";
638 572 reg = <0x01c22c00 0x40>;
639 573 interrupts = <30>;
640   - clocks = <&apb0_gates 0>, <&codec_clk>;
  574 + clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
641 575 clock-names = "apb", "codec";
642 576 dmas = <&dma SUN4I_DMA_NORMAL 19>,
643 577 <&dma SUN4I_DMA_NORMAL 19>;
644 578  
645 579  
646 580  
647 581  
648 582  
649 583  
650 584  
651 585  
652 586  
653 587  
654 588  
655 589  
656 590  
657 591  
658 592  
... ... @@ -645,73 +579,163 @@
645 579 status = "disabled";
646 580 };
647 581  
648   - sid: eeprom@01c23800 {
  582 + sid: eeprom@1c23800 {
649 583 compatible = "allwinner,sun4i-a10-sid";
650 584 reg = <0x01c23800 0x10>;
651 585 };
652 586  
653   - rtp: rtp@01c25000 {
  587 + rtp: rtp@1c25000 {
654 588 compatible = "allwinner,sun5i-a13-ts";
655 589 reg = <0x01c25000 0x100>;
656 590 interrupts = <29>;
657 591 #thermal-sensor-cells = <0>;
658 592 };
659 593  
660   - uart1: serial@01c28400 {
  594 + uart0: serial@1c28000 {
661 595 compatible = "snps,dw-apb-uart";
  596 + reg = <0x01c28000 0x400>;
  597 + interrupts = <1>;
  598 + reg-shift = <2>;
  599 + reg-io-width = <4>;
  600 + clocks = <&ccu CLK_APB1_UART0>;
  601 + status = "disabled";
  602 + };
  603 +
  604 + uart1: serial@1c28400 {
  605 + compatible = "snps,dw-apb-uart";
662 606 reg = <0x01c28400 0x400>;
663 607 interrupts = <2>;
664 608 reg-shift = <2>;
665 609 reg-io-width = <4>;
666   - clocks = <&apb1_gates 17>;
  610 + clocks = <&ccu CLK_APB1_UART1>;
667 611 status = "disabled";
668 612 };
669 613  
670   - uart3: serial@01c28c00 {
  614 + uart2: serial@1c28800 {
671 615 compatible = "snps,dw-apb-uart";
  616 + reg = <0x01c28800 0x400>;
  617 + interrupts = <3>;
  618 + reg-shift = <2>;
  619 + reg-io-width = <4>;
  620 + clocks = <&ccu CLK_APB1_UART2>;
  621 + status = "disabled";
  622 + };
  623 +
  624 + uart3: serial@1c28c00 {
  625 + compatible = "snps,dw-apb-uart";
672 626 reg = <0x01c28c00 0x400>;
673 627 interrupts = <4>;
674 628 reg-shift = <2>;
675 629 reg-io-width = <4>;
676   - clocks = <&apb1_gates 19>;
  630 + clocks = <&ccu CLK_APB1_UART3>;
677 631 status = "disabled";
678 632 };
679 633  
680   - i2c0: i2c@01c2ac00 {
  634 + i2c0: i2c@1c2ac00 {
681 635 compatible = "allwinner,sun4i-a10-i2c";
682 636 reg = <0x01c2ac00 0x400>;
683 637 interrupts = <7>;
684   - clocks = <&apb1_gates 0>;
  638 + clocks = <&ccu CLK_APB1_I2C0>;
685 639 status = "disabled";
686 640 #address-cells = <1>;
687 641 #size-cells = <0>;
688 642 };
689 643  
690   - i2c1: i2c@01c2b000 {
  644 + i2c1: i2c@1c2b000 {
691 645 compatible = "allwinner,sun4i-a10-i2c";
692 646 reg = <0x01c2b000 0x400>;
693 647 interrupts = <8>;
694   - clocks = <&apb1_gates 1>;
  648 + clocks = <&ccu CLK_APB1_I2C1>;
695 649 status = "disabled";
696 650 #address-cells = <1>;
697 651 #size-cells = <0>;
698 652 };
699 653  
700   - i2c2: i2c@01c2b400 {
  654 + i2c2: i2c@1c2b400 {
701 655 compatible = "allwinner,sun4i-a10-i2c";
702 656 reg = <0x01c2b400 0x400>;
703 657 interrupts = <9>;
704   - clocks = <&apb1_gates 2>;
  658 + clocks = <&ccu CLK_APB1_I2C2>;
705 659 status = "disabled";
706 660 #address-cells = <1>;
707 661 #size-cells = <0>;
708 662 };
709 663  
710   - timer@01c60000 {
  664 + timer@1c60000 {
711 665 compatible = "allwinner,sun5i-a13-hstimer";
712 666 reg = <0x01c60000 0x1000>;
713 667 interrupts = <82>, <83>;
714   - clocks = <&ahb_gates 28>;
  668 + clocks = <&ccu CLK_AHB_HSTIMER>;
  669 + };
  670 +
  671 + fe0: display-frontend@1e00000 {
  672 + compatible = "allwinner,sun5i-a13-display-frontend";
  673 + reg = <0x01e00000 0x20000>;
  674 + interrupts = <47>;
  675 + clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,
  676 + <&ccu CLK_DRAM_DE_FE>;
  677 + clock-names = "ahb", "mod",
  678 + "ram";
  679 + resets = <&ccu RST_DE_FE>;
  680 + status = "disabled";
  681 +
  682 + ports {
  683 + #address-cells = <1>;
  684 + #size-cells = <0>;
  685 +
  686 + fe0_out: port@1 {
  687 + #address-cells = <1>;
  688 + #size-cells = <0>;
  689 + reg = <1>;
  690 +
  691 + fe0_out_be0: endpoint@0 {
  692 + reg = <0>;
  693 + remote-endpoint = <&be0_in_fe0>;
  694 + };
  695 + };
  696 + };
  697 + };
  698 +
  699 + be0: display-backend@1e60000 {
  700 + compatible = "allwinner,sun5i-a13-display-backend";
  701 + reg = <0x01e60000 0x10000>;
  702 + interrupts = <47>;
  703 + clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
  704 + <&ccu CLK_DRAM_DE_BE>;
  705 + clock-names = "ahb", "mod",
  706 + "ram";
  707 + resets = <&ccu RST_DE_BE>;
  708 + status = "disabled";
  709 +
  710 + assigned-clocks = <&ccu CLK_DE_BE>;
  711 + assigned-clock-rates = <300000000>;
  712 +
  713 + ports {
  714 + #address-cells = <1>;
  715 + #size-cells = <0>;
  716 +
  717 + be0_in: port@0 {
  718 + #address-cells = <1>;
  719 + #size-cells = <0>;
  720 + reg = <0>;
  721 +
  722 + be0_in_fe0: endpoint@0 {
  723 + reg = <0>;
  724 + remote-endpoint = <&fe0_out_be0>;
  725 + };
  726 + };
  727 +
  728 + be0_out: port@1 {
  729 + #address-cells = <1>;
  730 + #size-cells = <0>;
  731 + reg = <1>;
  732 +
  733 + be0_out_tcon0: endpoint@0 {
  734 + reg = <0>;
  735 + remote-endpoint = <&tcon0_in_be0>;
  736 + };
  737 + };
  738 + };
715 739 };
716 740 };
717 741 };
include/dt-bindings/clock/sun5i-ccu.h
Diff comments   View file @ 13b36fa
  1 +/*
  2 + * Copyright 2016 Maxime Ripard
  3 + *
  4 + * Maxime Ripard <maxime.ripard@free-electrons.com>
  5 + *
  6 + * This program is free software; you can redistribute it and/or modify
  7 + * it under the terms of the GNU General Public License as published by
  8 + * the Free Software Foundation; either version 2 of the License, or
  9 + * (at your option) any later version.
  10 + *
  11 + * This program is distributed in the hope that it will be useful,
  12 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14 + * GNU General Public License for more details.
  15 + */
  16 +
  17 +#ifndef _DT_BINDINGS_CLK_SUN5I_H_
  18 +#define _DT_BINDINGS_CLK_SUN5I_H_
  19 +
  20 +#define CLK_HOSC 1
  21 +
  22 +#define CLK_PLL_VIDEO0_2X 9
  23 +
  24 +#define CLK_PLL_VIDEO1_2X 16
  25 +#define CLK_CPU 17
  26 +
  27 +#define CLK_AHB_OTG 23
  28 +#define CLK_AHB_EHCI 24
  29 +#define CLK_AHB_OHCI 25
  30 +#define CLK_AHB_SS 26
  31 +#define CLK_AHB_DMA 27
  32 +#define CLK_AHB_BIST 28
  33 +#define CLK_AHB_MMC0 29
  34 +#define CLK_AHB_MMC1 30
  35 +#define CLK_AHB_MMC2 31
  36 +#define CLK_AHB_NAND 32
  37 +#define CLK_AHB_SDRAM 33
  38 +#define CLK_AHB_EMAC 34
  39 +#define CLK_AHB_TS 35
  40 +#define CLK_AHB_SPI0 36
  41 +#define CLK_AHB_SPI1 37
  42 +#define CLK_AHB_SPI2 38
  43 +#define CLK_AHB_GPS 39
  44 +#define CLK_AHB_HSTIMER 40
  45 +#define CLK_AHB_VE 41
  46 +#define CLK_AHB_TVE 42
  47 +#define CLK_AHB_LCD 43
  48 +#define CLK_AHB_CSI 44
  49 +#define CLK_AHB_HDMI 45
  50 +#define CLK_AHB_DE_BE 46
  51 +#define CLK_AHB_DE_FE 47
  52 +#define CLK_AHB_IEP 48
  53 +#define CLK_AHB_GPU 49
  54 +#define CLK_APB0_CODEC 50
  55 +#define CLK_APB0_SPDIF 51
  56 +#define CLK_APB0_I2S 52
  57 +#define CLK_APB0_PIO 53
  58 +#define CLK_APB0_IR 54
  59 +#define CLK_APB0_KEYPAD 55
  60 +#define CLK_APB1_I2C0 56
  61 +#define CLK_APB1_I2C1 57
  62 +#define CLK_APB1_I2C2 58
  63 +#define CLK_APB1_UART0 59
  64 +#define CLK_APB1_UART1 60
  65 +#define CLK_APB1_UART2 61
  66 +#define CLK_APB1_UART3 62
  67 +#define CLK_NAND 63
  68 +#define CLK_MMC0 64
  69 +#define CLK_MMC1 65
  70 +#define CLK_MMC2 66
  71 +#define CLK_TS 67
  72 +#define CLK_SS 68
  73 +#define CLK_SPI0 69
  74 +#define CLK_SPI1 70
  75 +#define CLK_SPI2 71
  76 +#define CLK_IR 72
  77 +#define CLK_I2S 73
  78 +#define CLK_SPDIF 74
  79 +#define CLK_KEYPAD 75
  80 +#define CLK_USB_OHCI 76
  81 +#define CLK_USB_PHY0 77
  82 +#define CLK_USB_PHY1 78
  83 +#define CLK_GPS 79
  84 +#define CLK_DRAM_VE 80
  85 +#define CLK_DRAM_CSI 81
  86 +#define CLK_DRAM_TS 82
  87 +#define CLK_DRAM_TVE 83
  88 +#define CLK_DRAM_DE_FE 84
  89 +#define CLK_DRAM_DE_BE 85
  90 +#define CLK_DRAM_ACE 86
  91 +#define CLK_DRAM_IEP 87
  92 +#define CLK_DE_BE 88
  93 +#define CLK_DE_FE 89
  94 +#define CLK_TCON_CH0 90
  95 +
  96 +#define CLK_TCON_CH1 92
  97 +#define CLK_CSI 93
  98 +#define CLK_VE 94
  99 +#define CLK_CODEC 95
  100 +#define CLK_AVS 96
  101 +#define CLK_HDMI 97
  102 +#define CLK_GPU 98
  103 +
  104 +#define CLK_IEP 100
  105 +
  106 +#endif /* _DT_BINDINGS_CLK_SUN5I_H_ */
include/dt-bindings/reset/sun5i-ccu.h
Diff comments   View file @ 13b36fa
  1 +/*
  2 + * Copyright 2016 Maxime Ripard
  3 + *
  4 + * Maxime Ripard <maxime.ripard@free-electrons.com>
  5 + *
  6 + * This program is free software; you can redistribute it and/or modify
  7 + * it under the terms of the GNU General Public License as published by
  8 + * the Free Software Foundation; either version 2 of the License, or
  9 + * (at your option) any later version.
  10 + *
  11 + * This program is distributed in the hope that it will be useful,
  12 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14 + * GNU General Public License for more details.
  15 + */
  16 +
  17 +#ifndef _RST_SUN5I_H_
  18 +#define _RST_SUN5I_H_
  19 +
  20 +#define RST_USB_PHY0 0
  21 +#define RST_USB_PHY1 1
  22 +#define RST_GPS 2
  23 +#define RST_DE_BE 3
  24 +#define RST_DE_FE 4
  25 +#define RST_TVE 5
  26 +#define RST_LCD 6
  27 +#define RST_CSI 7
  28 +#define RST_VE 8
  29 +#define RST_GPU 9
  30 +#define RST_IEP 10
  31 +
  32 +#endif /* _RST_SUN5I_H_ */