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Commit 13e81d45f80b58e57a78daf6850d4f3a6bc20d9e

Authored by Pavel Machek
Committed by Marek Vasut
1 parent 60d804c2f3
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: socfpga: nic301: Add NIC-301 configuration code 

Add code which configures the AMBA NIC-301 and the SCU on the SoCFPGA .
The code sets the access permissions for the CPU to the AMBA slaves such
that the CPU can access them in both secure and non-secure mode.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>

Showing 1 changed file with 26 additions and 0 deletions Inline Diff

arch/arm/cpu/armv7/socfpga/misc.c
Diff comments   View file @ 13e81d4
1 /* 1 /*
2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <asm/io.h> 8 #include <asm/io.h>
9 #include <altera.h> 9 #include <altera.h>
10 #include <miiphy.h> 10 #include <miiphy.h>
11 #include <netdev.h> 11 #include <netdev.h>
12 #include <asm/arch/reset_manager.h> 12 #include <asm/arch/reset_manager.h>
13 #include <asm/arch/system_manager.h> 13 #include <asm/arch/system_manager.h>
14 #include <asm/arch/dwmmc.h> 14 #include <asm/arch/dwmmc.h>
15 #include <asm/arch/nic301.h> 15 #include <asm/arch/nic301.h>
16 #include <asm/arch/scu.h>
16 #include <asm/pl310.h> 17 #include <asm/pl310.h>
17 18
18 DECLARE_GLOBAL_DATA_PTR; 19 DECLARE_GLOBAL_DATA_PTR;
19 20
20 static struct pl310_regs *const pl310 = 21 static struct pl310_regs *const pl310 =
21 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 22 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
22 static struct socfpga_system_manager *sysmgr_regs = 23 static struct socfpga_system_manager *sysmgr_regs =
23 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 24 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
24 static struct nic301_registers *nic301_regs = 25 static struct nic301_registers *nic301_regs =
25 (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; 26 (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
27 static struct scu_registers *scu_regs =
28 (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
26 29
27 int dram_init(void) 30 int dram_init(void)
28 { 31 {
29 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); 32 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
30 return 0; 33 return 0;
31 } 34 }
32 35
33 /* 36 /*
34 * DesignWare Ethernet initialization 37 * DesignWare Ethernet initialization
35 */ 38 */
36 #ifdef CONFIG_DESIGNWARE_ETH 39 #ifdef CONFIG_DESIGNWARE_ETH
37 int cpu_eth_init(bd_t *bis) 40 int cpu_eth_init(bd_t *bis)
38 { 41 {
39 #if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS 42 #if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
40 const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB; 43 const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
41 #elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS 44 #elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
42 const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; 45 const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
43 #else 46 #else
44 #error "Incorrect CONFIG_EMAC_BASE value!" 47 #error "Incorrect CONFIG_EMAC_BASE value!"
45 #endif 48 #endif
46 49
47 /* Initialize EMAC. This needs to be done at least once per boot. */ 50 /* Initialize EMAC. This needs to be done at least once per boot. */
48 51
49 /* 52 /*
50 * Putting the EMAC controller to reset when configuring the PHY 53 * Putting the EMAC controller to reset when configuring the PHY
51 * interface select at System Manager 54 * interface select at System Manager
52 */ 55 */
53 socfpga_emac_reset(1); 56 socfpga_emac_reset(1);
54 57
55 /* Clearing emac0 PHY interface select to 0 */ 58 /* Clearing emac0 PHY interface select to 0 */
56 clrbits_le32(&sysmgr_regs->emacgrp_ctrl, 59 clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
57 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift); 60 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
58 61
59 /* configure to PHY interface select choosed */ 62 /* configure to PHY interface select choosed */
60 setbits_le32(&sysmgr_regs->emacgrp_ctrl, 63 setbits_le32(&sysmgr_regs->emacgrp_ctrl,
61 SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift); 64 SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
62 65
63 /* Release the EMAC controller from reset */ 66 /* Release the EMAC controller from reset */
64 socfpga_emac_reset(0); 67 socfpga_emac_reset(0);
65 68
66 /* initialize and register the emac */ 69 /* initialize and register the emac */
67 return designware_initialize(CONFIG_EMAC_BASE, 70 return designware_initialize(CONFIG_EMAC_BASE,
68 CONFIG_PHY_INTERFACE_MODE); 71 CONFIG_PHY_INTERFACE_MODE);
69 } 72 }
70 #endif 73 #endif
71 74
72 #ifdef CONFIG_DWMMC 75 #ifdef CONFIG_DWMMC
73 /* 76 /*
74 * Initializes MMC controllers. 77 * Initializes MMC controllers.
75 * to override, implement board_mmc_init() 78 * to override, implement board_mmc_init()
76 */ 79 */
77 int cpu_mmc_init(bd_t *bis) 80 int cpu_mmc_init(bd_t *bis)
78 { 81 {
79 return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS, 82 return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS,
80 CONFIG_HPS_SDMMC_BUSWIDTH, 0); 83 CONFIG_HPS_SDMMC_BUSWIDTH, 0);
81 } 84 }
82 #endif 85 #endif
83 86
84 #if defined(CONFIG_DISPLAY_CPUINFO) 87 #if defined(CONFIG_DISPLAY_CPUINFO)
85 /* 88 /*
86 * Print CPU information 89 * Print CPU information
87 */ 90 */
88 int print_cpuinfo(void) 91 int print_cpuinfo(void)
89 { 92 {
90 puts("CPU: Altera SoCFPGA Platform\n"); 93 puts("CPU: Altera SoCFPGA Platform\n");
91 return 0; 94 return 0;
92 } 95 }
93 #endif 96 #endif
94 97
95 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ 98 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
96 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) 99 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
97 int overwrite_console(void) 100 int overwrite_console(void)
98 { 101 {
99 return 0; 102 return 0;
100 } 103 }
101 #endif 104 #endif
102 105
103 #ifdef CONFIG_FPGA 106 #ifdef CONFIG_FPGA
104 /* 107 /*
105 * FPGA programming support for SoC FPGA Cyclone V 108 * FPGA programming support for SoC FPGA Cyclone V
106 */ 109 */
107 static Altera_desc altera_fpga[] = { 110 static Altera_desc altera_fpga[] = {
108 { 111 {
109 /* Family */ 112 /* Family */
110 Altera_SoCFPGA, 113 Altera_SoCFPGA,
111 /* Interface type */ 114 /* Interface type */
112 fast_passive_parallel, 115 fast_passive_parallel,
113 /* No limitation as additional data will be ignored */ 116 /* No limitation as additional data will be ignored */
114 -1, 117 -1,
115 /* No device function table */ 118 /* No device function table */
116 NULL, 119 NULL,
117 /* Base interface address specified in driver */ 120 /* Base interface address specified in driver */
118 NULL, 121 NULL,
119 /* No cookie implementation */ 122 /* No cookie implementation */
120 0 123 0
121 }, 124 },
122 }; 125 };
123 126
124 /* add device descriptor to FPGA device table */ 127 /* add device descriptor to FPGA device table */
125 static void socfpga_fpga_add(void) 128 static void socfpga_fpga_add(void)
126 { 129 {
127 int i; 130 int i;
128 fpga_init(); 131 fpga_init();
129 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) 132 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
130 fpga_add(fpga_altera, &altera_fpga[i]); 133 fpga_add(fpga_altera, &altera_fpga[i]);
131 } 134 }
132 #else 135 #else
133 static inline void socfpga_fpga_add(void) {} 136 static inline void socfpga_fpga_add(void) {}
134 #endif 137 #endif
135 138
136 int arch_cpu_init(void) 139 int arch_cpu_init(void)
137 { 140 {
138 /* 141 /*
139 * If the HW watchdog is NOT enabled, make sure it is not running, 142 * If the HW watchdog is NOT enabled, make sure it is not running,
140 * for example because it was enabled in the preloader. This might 143 * for example because it was enabled in the preloader. This might
141 * trigger a watchdog-triggered reboot of Linux kernel later. 144 * trigger a watchdog-triggered reboot of Linux kernel later.
142 */ 145 */
143 #ifndef CONFIG_HW_WATCHDOG 146 #ifndef CONFIG_HW_WATCHDOG
144 socfpga_watchdog_reset(); 147 socfpga_watchdog_reset();
145 #endif 148 #endif
146 return 0; 149 return 0;
147 } 150 }
148 151
152 /*
153 * Convert all NIC-301 AMBA slaves from secure to non-secure
154 */
155 static void socfpga_nic301_slave_ns(void)
156 {
157 writel(0x1, &nic301_regs->lwhps2fpgaregs);
158 writel(0x1, &nic301_regs->hps2fpgaregs);
159 writel(0x1, &nic301_regs->acp);
160 writel(0x1, &nic301_regs->rom);
161 writel(0x1, &nic301_regs->ocram);
162 writel(0x1, &nic301_regs->sdrdata);
163 }
164
149 int misc_init_r(void) 165 int misc_init_r(void)
150 { 166 {
167 socfpga_bridges_reset(1);
168 socfpga_nic301_slave_ns();
169
170 /*
171 * Private components security:
172 * U-Boot : configure private timer, global timer and cpu component
173 * access as non secure for kernel stage (as required by Linux)
174 */
175 setbits_le32(&scu_regs->sacr, 0xfff);
176
151 /* Configure the L2 controller to make SDRAM start at 0 */ 177 /* Configure the L2 controller to make SDRAM start at 0 */
152 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 178 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
153 writel(0x2, &nic301_regs->remap); 179 writel(0x2, &nic301_regs->remap);
154 #else 180 #else
155 writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ 181 writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
156 writel(0x1, &pl310->pl310_addr_filter_start); 182 writel(0x1, &pl310->pl310_addr_filter_start);
157 #endif 183 #endif
158 184
159 /* Add device descriptor to FPGA device table */ 185 /* Add device descriptor to FPGA device table */
160 socfpga_fpga_add(); 186 socfpga_fpga_add();
161 return 0; 187 return 0;
162 } 188 }
163 189