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Commit 60d804c2f3ddd0071348c6e65999e19b4d07d16a

Authored by Marek Vasut
1 parent 7056efcc32
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: socfpga: pl310: Map SDRAM to 0x0 

Configure the PL310 address filter to make sure DRAM is mapped to 0x0.
This code also configures the "remap" register of NIC-301 and sets the
required 'mpuzero' bit.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

Showing 1 changed file with 14 additions and 0 deletions Side-by-side Diff

arch/arm/cpu/armv7/socfpga/misc.c
Diff comments   View file @ 60d804c
... ... @@ -12,11 +12,17 @@
12 12 #include <asm/arch/reset_manager.h>
13 13 #include <asm/arch/system_manager.h>
14 14 #include <asm/arch/dwmmc.h>
  15 +#include <asm/arch/nic301.h>
  16 +#include <asm/pl310.h>
15 17  
16 18 DECLARE_GLOBAL_DATA_PTR;
17 19  
  20 +static struct pl310_regs *const pl310 =
  21 + (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
18 22 static struct socfpga_system_manager *sysmgr_regs =
19 23 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  24 +static struct nic301_registers *nic301_regs =
  25 + (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
20 26  
21 27 int dram_init(void)
22 28 {
... ... @@ -142,6 +148,14 @@
142 148  
143 149 int misc_init_r(void)
144 150 {
  151 + /* Configure the L2 controller to make SDRAM start at 0 */
  152 +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
  153 + writel(0x2, &nic301_regs->remap);
  154 +#else
  155 + writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
  156 + writel(0x1, &pl310->pl310_addr_filter_start);
  157 +#endif
  158 +
145 159 /* Add device descriptor to FPGA device table */
146 160 socfpga_fpga_add();
147 161 return 0;