Eric Lee / smarc-uboot

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Commit 142c9751a6cb7e2f9d18847570bc01c5e991aeeb

Authored by Wolfgang Wallner
Committed by Bin Meng
1 parent 7d53b5a4ce
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

x86: Move itss.h from Apollo Lake to the generic x86 include directory 

The code in this file is not specific to Apollo Lake. According to
coreboot sources (where this code comes from), it is common to at least:
  * Apollo Lake
  * Cannon Lake
  * Ice Lake
  * Skylake

Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Showing 4 changed files with 47 additions and 47 deletions Side-by-side Diff

arch/x86/cpu/apollolake/itss.c
Diff comments   View file @ 142c975
... ... @@ -15,7 +15,7 @@
15 15 #include <irq.h>
16 16 #include <p2sb.h>
17 17 #include <spl.h>
18   -#include <asm/arch/itss.h>
  18 +#include <asm/itss.h>
19 19  
20 20 struct apl_itss_platdata {
21 21 #if CONFIG_IS_ENABLED(OF_PLATDATA)
arch/x86/include/asm/arch-apollolake/itss.h
View file @ 142c975
1   -/* SPDX-License-Identifier: GPL-2.0 */
2   -/*
3   - * Interrupt Timer Subsystem
4   - *
5   - * Copyright (C) 2017 Intel Corporation.
6   - * Copyright 2019 Google LLC
7   - *
8   - * Modified from coreboot itss.h
9   - */
10   -
11   -#ifndef _ASM_ARCH_ITSS_H
12   -#define _ASM_ARCH_ITSS_H
13   -
14   -#define GPIO_IRQ_START 50
15   -#define GPIO_IRQ_END ITSS_MAX_IRQ
16   -
17   -#define ITSS_MAX_IRQ 119
18   -#define IRQS_PER_IPC 32
19   -#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1) / IRQS_PER_IPC)
20   -
21   -/* Max PXRC registers in ITSS */
22   -#define MAX_PXRC_CONFIG (PCR_ITSS_PIRQH_ROUT - PCR_ITSS_PIRQA_ROUT + 1)
23   -
24   -/* PIRQA Routing Control Register */
25   -#define PCR_ITSS_PIRQA_ROUT 0x3100
26   -/* PIRQB Routing Control Register */
27   -#define PCR_ITSS_PIRQB_ROUT 0x3101
28   -/* PIRQC Routing Control Register */
29   -#define PCR_ITSS_PIRQC_ROUT 0x3102
30   -/* PIRQD Routing Control Register */
31   -#define PCR_ITSS_PIRQD_ROUT 0x3103
32   -/* PIRQE Routing Control Register */
33   -#define PCR_ITSS_PIRQE_ROUT 0x3104
34   -/* PIRQF Routing Control Register */
35   -#define PCR_ITSS_PIRQF_ROUT 0x3105
36   -/* PIRQG Routing Control Register */
37   -#define PCR_ITSS_PIRQG_ROUT 0x3106
38   -/* PIRQH Routing Control Register */
39   -#define PCR_ITSS_PIRQH_ROUT 0x3107
40   -/* ITSS Interrupt polarity control */
41   -#define PCR_ITSS_IPC0_CONF 0x3200
42   -/* ITSS Power reduction control */
43   -#define PCR_ITSS_ITSSPRC 0x3300
44   -
45   -#endif /* _ASM_ARCH_ITSS_H */
arch/x86/include/asm/itss.h
Diff comments   View file @ 142c975
  1 +/* SPDX-License-Identifier: GPL-2.0 */
  2 +/*
  3 + * Interrupt Timer Subsystem
  4 + *
  5 + * Copyright (C) 2017 Intel Corporation.
  6 + * Copyright 2019 Google LLC
  7 + *
  8 + * Modified from coreboot itss.h
  9 + */
  10 +
  11 +#ifndef _ASM_ARCH_ITSS_H
  12 +#define _ASM_ARCH_ITSS_H
  13 +
  14 +#define GPIO_IRQ_START 50
  15 +#define GPIO_IRQ_END ITSS_MAX_IRQ
  16 +
  17 +#define ITSS_MAX_IRQ 119
  18 +#define IRQS_PER_IPC 32
  19 +#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1) / IRQS_PER_IPC)
  20 +
  21 +/* Max PXRC registers in ITSS */
  22 +#define MAX_PXRC_CONFIG (PCR_ITSS_PIRQH_ROUT - PCR_ITSS_PIRQA_ROUT + 1)
  23 +
  24 +/* PIRQA Routing Control Register */
  25 +#define PCR_ITSS_PIRQA_ROUT 0x3100
  26 +/* PIRQB Routing Control Register */
  27 +#define PCR_ITSS_PIRQB_ROUT 0x3101
  28 +/* PIRQC Routing Control Register */
  29 +#define PCR_ITSS_PIRQC_ROUT 0x3102
  30 +/* PIRQD Routing Control Register */
  31 +#define PCR_ITSS_PIRQD_ROUT 0x3103
  32 +/* PIRQE Routing Control Register */
  33 +#define PCR_ITSS_PIRQE_ROUT 0x3104
  34 +/* PIRQF Routing Control Register */
  35 +#define PCR_ITSS_PIRQF_ROUT 0x3105
  36 +/* PIRQG Routing Control Register */
  37 +#define PCR_ITSS_PIRQG_ROUT 0x3106
  38 +/* PIRQH Routing Control Register */
  39 +#define PCR_ITSS_PIRQH_ROUT 0x3107
  40 +/* ITSS Interrupt polarity control */
  41 +#define PCR_ITSS_IPC0_CONF 0x3200
  42 +/* ITSS Power reduction control */
  43 +#define PCR_ITSS_ITSSPRC 0x3300
  44 +
  45 +#endif /* _ASM_ARCH_ITSS_H */
drivers/pinctrl/intel/pinctrl.c
Diff comments   View file @ 142c975
... ... @@ -25,7 +25,7 @@
25 25 #include <asm/intel_pinctrl.h>
26 26 #include <asm/intel_pinctrl_defs.h>
27 27 #include <asm/arch/gpio.h>
28   -#include <asm/arch/itss.h>
  28 +#include <asm/itss.h>
29 29 #include <dm/device-internal.h>
30 30 #include <dt-bindings/gpio/gpio.h>
31 31