mx35: factorize SDRAM setup in flea3

Drop local function to setup SDRAM controller and use the common one for i.MX35. Signed-off-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Heiko Schocher <hs@denx.de>

mx35: factorize SDRAM setup in flea3
Drop local function to setup SDRAM controller and use the common one for i.MX35. Signed-off-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Heiko Schocher <hs@denx.de>
Stefano Babic
1 parent 72c1015307
Showing 1 changed file with 3 additions and 90 deletions Side-by-side Diff
board/CarMediaLab/flea3/flea3.c
@@ -30,18 +30,6 @@
 #define CCM_CCMR_CONFIG		0x003F4208
  
 #define ESDCTL_DDR2_CONFIG	0x007FFC3F
-#define ESDCTL_0x92220000	0x92220000
-#define ESDCTL_0xA2220000	0xA2220000
-#define ESDCTL_0xB2220000	0xB2220000
-#define ESDCTL_0x82228080	0x82228080
-#define ESDCTL_DDR2_EMR2	0x04000000
-#define ESDCTL_DDR2_EMR3	0x06000000
-#define ESDCTL_PRECHARGE	0x00000400
-#define ESDCTL_DDR2_EN_DLL	0x02000400
-#define ESDCTL_DDR2_RESET_DLL	0x00000333
-#define ESDCTL_DDR2_MR		0x00000233
-#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
-#define ESDCTL_DELAY_LINE5	0x00F49F00
  
 static inline void dram_wait(unsigned int count)
 {
@@ -61,83 +49,6 @@
 	return 0;
 }
  
-static void board_setup_sdram_bank(u32 start_address)
-
-{
-	struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
-	u32 *cfg_reg, *ctl_reg;
-	u32 val;
-
-	switch (start_address) {
-	case CSD0_BASE_ADDR:
-		cfg_reg = &esdc->esdcfg0;
-		ctl_reg = &esdc->esdctl0;
-		break;
-	case CSD1_BASE_ADDR:
-		cfg_reg = &esdc->esdcfg1;
-		ctl_reg = &esdc->esdctl1;
-		break;
-	default:
-		return;
-	}
-
-	/* Initialize MISC register for DDR2 */
-	val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
-		ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
-	writel(val, &esdc->esdmisc);
-	val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
-	writel(val, &esdc->esdmisc);
-
-	/*
-	 * according to DDR2 specs, wait a while before
-	 * the PRECHARGE_ALL command
-	 */
-	dram_wait(0x20000);
-
-	/* Load DDR2 config and timing */
-	writel(ESDCTL_DDR2_CONFIG, cfg_reg);
-
-	/* Precharge ALL */
-	writel(ESDCTL_0x92220000,
-		ctl_reg);
-	writel(0xda, start_address + ESDCTL_PRECHARGE);
-
-	/* Load mode */
-	writel(ESDCTL_0xB2220000,
-		ctl_reg);
-	writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
-	writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
-	writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
-	writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
-
-	/* Precharge ALL */
-	writel(ESDCTL_0x92220000,
-		ctl_reg);
-	writel(0xda, start_address + ESDCTL_PRECHARGE);
-
-	/* Set mode auto refresh : at least two refresh are required */
-	writel(ESDCTL_0xA2220000,
-		ctl_reg);
-	writel(0xda, start_address);
-	writel(0xda, start_address);
-
-	writel(ESDCTL_0xB2220000,
-		ctl_reg);
-	writeb(0xda, start_address + ESDCTL_DDR2_MR);
-	writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
-
-	/* OCD mode exit */
-	writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
-
-	/* Set normal mode */
-	writel(ESDCTL_0x82228080,
-		ctl_reg);
-
-	dram_wait(0x20000);
-
-	/* Do not set delay lines, only for MDDR */
-}
-
 static void board_setup_sdram(void)
 {
 	struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
@@ -146,7 +57,9 @@
 	writel(0x2000, &esdc->esdctl0);
 	writel(0x2000, &esdc->esdctl1);
  
-	board_setup_sdram_bank(CSD0_BASE_ADDR);
+
+	mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
+			     13, 10, 2, 0x8080);
 }
  
 static void setup_iomux_uart3(void)
...	...	@@ -30,18 +30,6 @@
30	30	#define CCM_CCMR_CONFIG 0x003F4208
31	31
32	32	#define ESDCTL_DDR2_CONFIG 0x007FFC3F
33		-#define ESDCTL_0x92220000 0x92220000
34		-#define ESDCTL_0xA2220000 0xA2220000
35		-#define ESDCTL_0xB2220000 0xB2220000
36		-#define ESDCTL_0x82228080 0x82228080
37		-#define ESDCTL_DDR2_EMR2 0x04000000
38		-#define ESDCTL_DDR2_EMR3 0x06000000
39		-#define ESDCTL_PRECHARGE 0x00000400
40		-#define ESDCTL_DDR2_EN_DLL 0x02000400
41		-#define ESDCTL_DDR2_RESET_DLL 0x00000333
42		-#define ESDCTL_DDR2_MR 0x00000233
43		-#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
44		-#define ESDCTL_DELAY_LINE5 0x00F49F00
45	33
46	34	static inline void dram_wait(unsigned int count)
47	35	{
...	...	@@ -61,83 +49,6 @@
61	49	return 0;
62	50	}
63	51
64		-static void board_setup_sdram_bank(u32 start_address)
65		-
66		-{
67		- struct esdc_regs esdc = (struct esdc_regs )ESDCTL_BASE_ADDR;
68		- u32 cfg_reg, ctl_reg;
69		- u32 val;
70		-
71		- switch (start_address) {
72		- case CSD0_BASE_ADDR:
73		- cfg_reg = &esdc->esdcfg0;
74		- ctl_reg = &esdc->esdctl0;
75		- break;
76		- case CSD1_BASE_ADDR:
77		- cfg_reg = &esdc->esdcfg1;
78		- ctl_reg = &esdc->esdctl1;
79		- break;
80		- default:
81		- return;
82		- }
83		-
84		- /* Initialize MISC register for DDR2 */
85		- val = ESDC_MISC_RST \| ESDC_MISC_MDDR_EN \| ESDC_MISC_MDDR_DL_RST \|
86		- ESDC_MISC_DDR_EN \| ESDC_MISC_DDR2_EN;
87		- writel(val, &esdc->esdmisc);
88		- val &= ~(ESDC_MISC_RST \| ESDC_MISC_MDDR_DL_RST);
89		- writel(val, &esdc->esdmisc);
90		-
91		- /*
92		- * according to DDR2 specs, wait a while before
93		- * the PRECHARGE_ALL command
94		- */
95		- dram_wait(0x20000);
96		-
97		- /* Load DDR2 config and timing */
98		- writel(ESDCTL_DDR2_CONFIG, cfg_reg);
99		-
100		- /* Precharge ALL */
101		- writel(ESDCTL_0x92220000,
102		- ctl_reg);
103		- writel(0xda, start_address + ESDCTL_PRECHARGE);
104		-
105		- /* Load mode */
106		- writel(ESDCTL_0xB2220000,
107		- ctl_reg);
108		- writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
109		- writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
110		- writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
111		- writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
112		-
113		- /* Precharge ALL */
114		- writel(ESDCTL_0x92220000,
115		- ctl_reg);
116		- writel(0xda, start_address + ESDCTL_PRECHARGE);
117		-
118		- /* Set mode auto refresh : at least two refresh are required */
119		- writel(ESDCTL_0xA2220000,
120		- ctl_reg);
121		- writel(0xda, start_address);
122		- writel(0xda, start_address);
123		-
124		- writel(ESDCTL_0xB2220000,
125		- ctl_reg);
126		- writeb(0xda, start_address + ESDCTL_DDR2_MR);
127		- writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
128		-
129		- /* OCD mode exit */
130		- writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
131		-
132		- /* Set normal mode */
133		- writel(ESDCTL_0x82228080,
134		- ctl_reg);
135		-
136		- dram_wait(0x20000);
137		-
138		- /* Do not set delay lines, only for MDDR */
139		-}
140		-
141	52	static void board_setup_sdram(void)
142	53	{
143	54	struct esdc_regs esdc = (struct esdc_regs )ESDCTL_BASE_ADDR;
...	...	@@ -146,7 +57,9 @@
146	57	writel(0x2000, &esdc->esdctl0);
147	58	writel(0x2000, &esdc->esdctl1);
148	59
149		- board_setup_sdram_bank(CSD0_BASE_ADDR);
	60	+
	61	+ mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
	62	+ 13, 10, 2, 0x8080);
150	63	}
151	64
152	65	static void setup_iomux_uart3(void)