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Commit 14cfc4f3735d9704cb6a630ef302be596d380684

Authored by Michal Simek
1 parent 2df9d5c431
Exists in v2017.01-smarct4x and in 40 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

fpga: xilinx: Simplify load/dump/info function handling 

Connect FPGA version with appropriate operations
to remove huge switch-cases for every FPGA family.
Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Showing 12 changed files with 104 additions and 223 deletions Side-by-side Diff

board/armadeus/apf27/fpga.c
Diff comments   View file @ 14cfc4f
... ... @@ -48,6 +48,7 @@
48 48 1196128l/8,
49 49 (void *)&fpga_fns,
50 50 0,
  51 + &spartan3_op,
51 52 "3s200aft256"}
52 53 };
53 54  
board/astro/mcf5373l/fpga.c
Diff comments   View file @ 14cfc4f
... ... @@ -379,7 +379,8 @@
379 379 slave_serial,
380 380 XILINX_XC3S4000_SIZE,
381 381 (void *)&xilinx_fns,
382   - 0}
  382 + 0,
  383 + &spartan3_op}
383 384 };
384 385  
385 386 /* Initialize the fpga. Return 1 on success, 0 on failure. */
drivers/fpga/spartan2.c
Diff comments   View file @ 14cfc4f
... ... @@ -41,7 +41,7 @@
41 41  
42 42 /* ------------------------------------------------------------------------- */
43 43 /* Spartan-II Generic Implementation */
44   -int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize)
  44 +static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize)
45 45 {
46 46 int ret_val = FPGA_FAIL;
47 47  
... ... @@ -64,7 +64,7 @@
64 64 return ret_val;
65 65 }
66 66  
67   -int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
  67 +static int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
68 68 {
69 69 int ret_val = FPGA_FAIL;
70 70  
... ... @@ -87,7 +87,7 @@
87 87 return ret_val;
88 88 }
89 89  
90   -int spartan2_info(xilinx_desc *desc)
  90 +static int spartan2_info(xilinx_desc *desc)
91 91 {
92 92 return FPGA_SUCCESS;
93 93 }
... ... @@ -447,4 +447,10 @@
447 447 __FUNCTION__);
448 448 return FPGA_FAIL;
449 449 }
  450 +
  451 +struct xilinx_fpga_op spartan2_op = {
  452 + .load = spartan2_load,
  453 + .dump = spartan2_dump,
  454 + .info = spartan2_info,
  455 +};
drivers/fpga/spartan3.c
Diff comments   View file @ 14cfc4f
... ... @@ -45,7 +45,7 @@
45 45  
46 46 /* ------------------------------------------------------------------------- */
47 47 /* Spartan-II Generic Implementation */
48   -int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize)
  48 +static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize)
49 49 {
50 50 int ret_val = FPGA_FAIL;
51 51  
... ... @@ -68,7 +68,7 @@
68 68 return ret_val;
69 69 }
70 70  
71   -int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize)
  71 +static int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize)
72 72 {
73 73 int ret_val = FPGA_FAIL;
74 74  
... ... @@ -91,7 +91,7 @@
91 91 return ret_val;
92 92 }
93 93  
94   -int spartan3_info(xilinx_desc *desc)
  94 +static int spartan3_info(xilinx_desc *desc)
95 95 {
96 96 return FPGA_SUCCESS;
97 97 }
... ... @@ -465,4 +465,10 @@
465 465 __FUNCTION__);
466 466 return FPGA_FAIL;
467 467 }
  468 +
  469 +struct xilinx_fpga_op spartan3_op = {
  470 + .load = spartan3_load,
  471 + .dump = spartan3_dump,
  472 + .info = spartan3_info,
  473 +};
drivers/fpga/virtex2.c
Diff comments   View file @ 14cfc4f
... ... @@ -90,7 +90,7 @@
90 90 static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
91 91 static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
92 92  
93   -int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize)
  93 +static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize)
94 94 {
95 95 int ret_val = FPGA_FAIL;
96 96  
... ... @@ -112,7 +112,7 @@
112 112 return ret_val;
113 113 }
114 114  
115   -int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
  115 +static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
116 116 {
117 117 int ret_val = FPGA_FAIL;
118 118  
... ... @@ -134,7 +134,7 @@
134 134 return ret_val;
135 135 }
136 136  
137   -int virtex2_info(xilinx_desc *desc)
  137 +static int virtex2_info(xilinx_desc *desc)
138 138 {
139 139 return FPGA_SUCCESS;
140 140 }
... ... @@ -417,4 +417,10 @@
417 417 }
418 418  
419 419 /* vim: set ts=4 tw=78: */
  420 +
  421 +struct xilinx_fpga_op virtex2_op = {
  422 + .load = virtex2_load,
  423 + .dump = virtex2_dump,
  424 + .info = virtex2_info,
  425 +};
drivers/fpga/xilinx.c
Diff comments   View file @ 14cfc4f
... ... @@ -19,17 +19,6 @@
19 19 #include <spartan3.h>
20 20 #include <zynqpl.h>
21 21  
22   -#if 0
23   -#define FPGA_DEBUG
24   -#endif
25   -
26   -/* Define FPGA_DEBUG to get debug printf's */
27   -#ifdef FPGA_DEBUG
28   -#define PRINTF(fmt,args...) printf (fmt ,##args)
29   -#else
30   -#define PRINTF(fmt,args...)
31   -#endif
32   -
33 22 /* Local Static Functions */
34 23 static int xilinx_validate(xilinx_desc *desc, char *fn);
35 24  
36 25  
37 26  
38 27  
39 28  
40 29  
... ... @@ -143,116 +132,22 @@
143 132  
144 133 int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize)
145 134 {
146   - int ret_val = FPGA_FAIL; /* assume a failure */
147   -
148 135 if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
149 136 printf ("%s: Invalid device descriptor\n", __FUNCTION__);
150   - } else
151   - switch (desc->family) {
152   - case xilinx_spartan2:
153   -#if defined(CONFIG_FPGA_SPARTAN2)
154   - PRINTF ("%s: Launching the Spartan-II Loader...\n",
155   - __FUNCTION__);
156   - ret_val = spartan2_load(desc, buf, bsize);
157   -#else
158   - printf ("%s: No support for Spartan-II devices.\n",
159   - __FUNCTION__);
160   -#endif
161   - break;
162   - case xilinx_spartan3:
163   -#if defined(CONFIG_FPGA_SPARTAN3)
164   - PRINTF ("%s: Launching the Spartan-III Loader...\n",
165   - __FUNCTION__);
166   - ret_val = spartan3_load(desc, buf, bsize);
167   -#else
168   - printf ("%s: No support for Spartan-III devices.\n",
169   - __FUNCTION__);
170   -#endif
171   - break;
172   - case xilinx_virtex2:
173   -#if defined(CONFIG_FPGA_VIRTEX2)
174   - PRINTF ("%s: Launching the Virtex-II Loader...\n",
175   - __FUNCTION__);
176   - ret_val = virtex2_load(desc, buf, bsize);
177   -#else
178   - printf ("%s: No support for Virtex-II devices.\n",
179   - __FUNCTION__);
180   -#endif
181   - break;
182   - case xilinx_zynq:
183   -#if defined(CONFIG_FPGA_ZYNQPL)
184   - PRINTF("%s: Launching the Zynq PL Loader...\n",
185   - __func__);
186   - ret_val = zynq_load(desc, buf, bsize);
187   -#else
188   - printf("%s: No support for Zynq devices.\n",
189   - __func__);
190   -#endif
191   - break;
  137 + return FPGA_FAIL;
  138 + }
192 139  
193   - default:
194   - printf ("%s: Unsupported family type, %d\n",
195   - __FUNCTION__, desc->family);
196   - }
197   -
198   - return ret_val;
  140 + return desc->operations->load(desc, buf, bsize);
199 141 }
200 142  
201 143 int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
202 144 {
203   - int ret_val = FPGA_FAIL; /* assume a failure */
204   -
205 145 if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
206 146 printf ("%s: Invalid device descriptor\n", __FUNCTION__);
207   - } else
208   - switch (desc->family) {
209   - case xilinx_spartan2:
210   -#if defined(CONFIG_FPGA_SPARTAN2)
211   - PRINTF ("%s: Launching the Spartan-II Reader...\n",
212   - __FUNCTION__);
213   - ret_val = spartan2_dump(desc, buf, bsize);
214   -#else
215   - printf ("%s: No support for Spartan-II devices.\n",
216   - __FUNCTION__);
217   -#endif
218   - break;
219   - case xilinx_spartan3:
220   -#if defined(CONFIG_FPGA_SPARTAN3)
221   - PRINTF ("%s: Launching the Spartan-III Reader...\n",
222   - __FUNCTION__);
223   - ret_val = spartan3_dump(desc, buf, bsize);
224   -#else
225   - printf ("%s: No support for Spartan-III devices.\n",
226   - __FUNCTION__);
227   -#endif
228   - break;
229   - case xilinx_virtex2:
230   -#if defined( CONFIG_FPGA_VIRTEX2)
231   - PRINTF ("%s: Launching the Virtex-II Reader...\n",
232   - __FUNCTION__);
233   - ret_val = virtex2_dump(desc, buf, bsize);
234   -#else
235   - printf ("%s: No support for Virtex-II devices.\n",
236   - __FUNCTION__);
237   -#endif
238   - break;
239   - case xilinx_zynq:
240   -#if defined(CONFIG_FPGA_ZYNQPL)
241   - PRINTF("%s: Launching the Zynq PL Reader...\n",
242   - __func__);
243   - ret_val = zynq_dump(desc, buf, bsize);
244   -#else
245   - printf("%s: No support for Zynq devices.\n",
246   - __func__);
247   -#endif
248   - break;
  147 + return FPGA_FAIL;
  148 + }
249 149  
250   - default:
251   - printf ("%s: Unsupported family type, %d\n",
252   - __FUNCTION__, desc->family);
253   - }
254   -
255   - return ret_val;
  150 + return desc->operations->dump(desc, buf, bsize);
256 151 }
257 152  
258 153 int xilinx_info(xilinx_desc *desc)
... ... @@ -315,47 +210,7 @@
315 210  
316 211 if (desc->iface_fns) {
317 212 printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
318   - switch (desc->family) {
319   - case xilinx_spartan2:
320   -#if defined(CONFIG_FPGA_SPARTAN2)
321   - spartan2_info(desc);
322   -#else
323   - /* just in case */
324   - printf ("%s: No support for Spartan-II devices.\n",
325   - __FUNCTION__);
326   -#endif
327   - break;
328   - case xilinx_spartan3:
329   -#if defined(CONFIG_FPGA_SPARTAN3)
330   - spartan3_info(desc);
331   -#else
332   - /* just in case */
333   - printf ("%s: No support for Spartan-III devices.\n",
334   - __FUNCTION__);
335   -#endif
336   - break;
337   - case xilinx_virtex2:
338   -#if defined(CONFIG_FPGA_VIRTEX2)
339   - virtex2_info(desc);
340   -#else
341   - /* just in case */
342   - printf ("%s: No support for Virtex-II devices.\n",
343   - __FUNCTION__);
344   -#endif
345   - break;
346   - case xilinx_zynq:
347   -#if defined(CONFIG_FPGA_ZYNQPL)
348   - zynq_info(desc);
349   -#else
350   - /* just in case */
351   - printf("%s: No support for Zynq devices.\n",
352   - __func__);
353   -#endif
354   - /* Add new family types here */
355   - default:
356   - /* we don't need a message here - we give one up above */
357   - ;
358   - }
  213 + desc->operations->info(desc);
359 214 } else
360 215 printf ("No Device Function Table.\n");
361 216  
drivers/fpga/zynqpl.c
Diff comments   View file @ 14cfc4f
... ... @@ -36,7 +36,7 @@
36 36 #define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */
37 37 #endif
38 38  
39   -int zynq_info(xilinx_desc *desc)
  39 +static int zynq_info(xilinx_desc *desc)
40 40 {
41 41 return FPGA_SUCCESS;
42 42 }
... ... @@ -152,8 +152,7 @@
152 152 return 0;
153 153 }
154 154  
155   -
156   -int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize)
  155 +static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize)
157 156 {
158 157 unsigned long ts; /* Timestamp */
159 158 u32 partialbit = 0;
160 159  
... ... @@ -358,8 +357,14 @@
358 357 return FPGA_SUCCESS;
359 358 }
360 359  
361   -int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize)
  360 +static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize)
362 361 {
363 362 return FPGA_FAIL;
364 363 }
  364 +
  365 +struct xilinx_fpga_op zynq_op = {
  366 + .load = zynq_load,
  367 + .dump = zynq_dump,
  368 + .info = zynq_info,
  369 +};
... ... @@ -10,10 +10,6 @@
10 10  
11 11 #include <xilinx.h>
12 12  
13   -int spartan2_load(xilinx_desc *desc, const void *image, size_t size);
14   -int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize);
15   -int spartan2_info(xilinx_desc *desc);
16   -
17 13 /* Slave Parallel Implementation function table */
18 14 typedef struct {
19 15 xilinx_pre_fn pre;
... ... @@ -42,6 +38,8 @@
42 38 xilinx_post_fn post;
43 39 } xilinx_spartan2_slave_serial_fns;
44 40  
  41 +extern struct xilinx_fpga_op spartan2_op;
  42 +
45 43 /* Device Image Sizes
46 44 *********************************************************************/
47 45 /* Spartan-II (2.5V) */
48 46  
49 47  
50 48  
51 49  
52 50  
53 51  
54 52  
55 53  
56 54  
57 55  
... ... @@ -63,37 +61,37 @@
63 61 *********************************************************************/
64 62 /* Spartan-II devices */
65 63 #define XILINX_XC2S15_DESC(iface, fn_table, cookie) \
66   -{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie }
  64 +{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, &spartan2_op }
67 65  
68 66 #define XILINX_XC2S30_DESC(iface, fn_table, cookie) \
69   -{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie }
  67 +{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, &spartan2_op }
70 68  
71 69 #define XILINX_XC2S50_DESC(iface, fn_table, cookie) \
72   -{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie }
  70 +{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, &spartan2_op }
73 71  
74 72 #define XILINX_XC2S100_DESC(iface, fn_table, cookie) \
75   -{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie }
  73 +{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, &spartan2_op }
76 74  
77 75 #define XILINX_XC2S150_DESC(iface, fn_table, cookie) \
78   -{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie }
  76 +{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, &spartan2_op }
79 77  
80 78 #define XILINX_XC2S200_DESC(iface, fn_table, cookie) \
81   -{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie }
  79 +{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, &spartan2_op }
82 80  
83 81 #define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \
84   -{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie }
  82 +{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, &spartan2_op }
85 83  
86 84 #define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \
87   -{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie }
  85 +{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, &spartan2_op }
88 86  
89 87 #define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \
90   -{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie }
  88 +{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, &spartan2_op }
91 89  
92 90 #define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \
93   -{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie }
  91 +{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, &spartan2_op }
94 92  
95 93 #define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \
96   -{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie }
  94 +{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, &spartan2_op }
97 95  
98 96 #endif /* _SPARTAN2_H_ */
... ... @@ -10,10 +10,6 @@
10 10  
11 11 #include <xilinx.h>
12 12  
13   -int spartan3_load(xilinx_desc *desc, const void *image, size_t size);
14   -int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize);
15   -int spartan3_info(xilinx_desc *desc);
16   -
17 13 /* Slave Parallel Implementation function table */
18 14 typedef struct {
19 15 xilinx_pre_fn pre;
... ... @@ -44,6 +40,8 @@
44 40 xilinx_abort_fn abort;
45 41 } xilinx_spartan3_slave_serial_fns;
46 42  
  43 +extern struct xilinx_fpga_op spartan3_op;
  44 +
47 45 /* Device Image Sizes
48 46 *********************************************************************/
49 47 /* Spartan-III (1.2V) */
50 48  
51 49  
52 50  
53 51  
54 52  
55 53  
56 54  
57 55  
58 56  
59 57  
60 58  
61 59  
62 60  
... ... @@ -73,47 +71,49 @@
73 71 *********************************************************************/
74 72 /* Spartan-III devices */
75 73 #define XILINX_XC3S50_DESC(iface, fn_table, cookie) \
76   -{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie }
  74 +{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, &spartan3_op }
77 75  
78 76 #define XILINX_XC3S200_DESC(iface, fn_table, cookie) \
79   -{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie }
  77 +{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, &spartan3_op }
80 78  
81 79 #define XILINX_XC3S400_DESC(iface, fn_table, cookie) \
82   -{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie }
  80 +{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, &spartan3_op }
83 81  
84 82 #define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \
85   -{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie }
  83 +{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, &spartan3_op }
86 84  
87 85 #define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \
88   -{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie }
  86 +{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, &spartan3_op }
89 87  
90 88 #define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \
91   -{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie }
  89 +{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, &spartan3_op }
92 90  
93 91 #define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \
94   -{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie }
  92 +{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, &spartan3_op }
95 93  
96 94 #define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
97   -{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie }
  95 +{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, &spartan3_op }
98 96  
99 97 /* Spartan-3E devices */
100 98 #define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \
101   -{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie }
  99 +{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, &spartan3_op }
102 100  
103 101 #define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \
104   -{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie }
  102 +{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, &spartan3_op }
105 103  
106 104 #define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \
107   -{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie }
  105 +{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, &spartan3_op }
108 106  
109 107 #define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \
110   -{ xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie }
  108 +{ xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie, \
  109 + &spartan3_op }
111 110  
112 111 #define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \
113   -{ xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie }
  112 +{ xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie, \
  113 + &spartan3_op }
114 114  
115 115 #define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \
116   -{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie }
  116 +{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, &spartan3_op }
117 117  
118 118 #endif /* _SPARTAN3_H_ */
... ... @@ -11,9 +11,7 @@
11 11  
12 12 #include <xilinx.h>
13 13  
14   -int virtex2_load(xilinx_desc *desc, const void *image, size_t size);
15   -int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize);
16   -int virtex2_info(xilinx_desc *desc);
  14 +extern struct xilinx_fpga_op virtex2_op;
17 15  
18 16 /*
19 17 * Slave SelectMap Implementation function table.
20 18  
21 19  
22 20  
23 21  
24 22  
25 23  
26 24  
27 25  
28 26  
29 27  
30 28  
... ... @@ -60,40 +58,40 @@
60 58 /* Descriptor Macros
61 59 *********************************************************************/
62 60 #define XILINX_XC2V40_DESC(iface, fn_table, cookie) \
63   -{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie }
  61 +{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, &virtex2_op }
64 62  
65 63 #define XILINX_XC2V80_DESC(iface, fn_table, cookie) \
66   -{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie }
  64 +{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, &virtex2_op }
67 65  
68 66 #define XILINX_XC2V250_DESC(iface, fn_table, cookie) \
69   -{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie }
  67 +{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, &virtex2_op }
70 68  
71 69 #define XILINX_XC2V500_DESC(iface, fn_table, cookie) \
72   -{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie }
  70 +{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, &virtex2_op }
73 71  
74 72 #define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \
75   -{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie }
  73 +{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, &virtex2_op }
76 74  
77 75 #define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \
78   -{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie }
  76 +{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, &virtex2_op }
79 77  
80 78 #define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \
81   -{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie }
  79 +{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, &virtex2_op }
82 80  
83 81 #define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \
84   -{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie }
  82 +{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, &virtex2_op }
85 83  
86 84 #define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \
87   -{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie }
  85 +{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, &virtex2_op }
88 86  
89 87 #define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \
90   -{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie }
  88 +{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, &virtex2_op }
91 89  
92 90 #define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \
93   -{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie }
  91 +{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, &virtex2_op }
94 92  
95 93 #define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \
96   -{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie }
  94 +{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, &virtex2_op }
97 95  
98 96 #endif /* _VIRTEX2_H_ */
... ... @@ -40,8 +40,15 @@
40 40 size_t size; /* bytes of data part can accept */
41 41 void *iface_fns; /* interface function table */
42 42 int cookie; /* implementation specific cookie */
  43 + struct xilinx_fpga_op *operations; /* operations */
43 44 char *name; /* device name in bitstream */
44 45 } xilinx_desc; /* end, typedef xilinx_desc */
  46 +
  47 +struct xilinx_fpga_op {
  48 + int (*load)(xilinx_desc *, const void *, size_t);
  49 + int (*dump)(xilinx_desc *, const void *, size_t);
  50 + int (*info)(xilinx_desc *);
  51 +};
45 52  
46 53 /* Generic Xilinx Functions
47 54 *********************************************************************/
... ... @@ -12,9 +12,7 @@
12 12  
13 13 #include <xilinx.h>
14 14  
15   -int zynq_load(xilinx_desc *desc, const void *image, size_t size);
16   -int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize);
17   -int zynq_info(xilinx_desc *desc);
  15 +extern struct xilinx_fpga_op zynq_op;
18 16  
19 17 #define XILINX_ZYNQ_7010 0x2
20 18 #define XILINX_ZYNQ_7015 0x1b
21 19  
22 20  
23 21  
24 22  
25 23  
... ... @@ -33,22 +31,22 @@
33 31  
34 32 /* Descriptor Macros */
35 33 #define XILINX_XC7Z010_DESC(cookie) \
36   -{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, "7z010" }
  34 +{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, &zynq_op, "7z010" }
37 35  
38 36 #define XILINX_XC7Z015_DESC(cookie) \
39   -{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, "7z015" }
  37 +{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, &zynq_op, "7z015" }
40 38  
41 39 #define XILINX_XC7Z020_DESC(cookie) \
42   -{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, "7z020" }
  40 +{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, &zynq_op, "7z020" }
43 41  
44 42 #define XILINX_XC7Z030_DESC(cookie) \
45   -{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, "7z030" }
  43 +{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, &zynq_op, "7z030" }
46 44  
47 45 #define XILINX_XC7Z045_DESC(cookie) \
48   -{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, "7z045" }
  46 +{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, &zynq_op, "7z045" }
49 47  
50 48 #define XILINX_XC7Z100_DESC(cookie) \
51   -{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, "7z100" }
  49 +{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, &zynq_op, "7z100" }
52 50  
53 51 #endif /* _ZYNQPL_H_ */