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Commit 1521cdc5303db2a3ec5a09231fbaa5831561bf71

Authored by Masahiro Yamada
Committed by Tom Rini
1 parent dc9617e0ce
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

powerpc: ppc4xx: remove board support for CRAYL1 

This board has been orphaned for more than 6 months.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Showing 15 changed files with 1 additions and 1470 deletions Side-by-side Diff

arch/powerpc/cpu/ppc4xx/Kconfig
Diff comments   View file @ 1521cdc
... ... @@ -106,9 +106,6 @@
106 106 config TARGET_V5FX30TEVAL
107 107 bool "Support v5fx30teval"
108 108  
109   -config TARGET_CRAYL1
110   - bool "Support CRAYL1"
111   -
112 109 config TARGET_CATCENTER
113 110 bool "Support CATcenter"
114 111  
... ... @@ -260,7 +257,6 @@
260 257 source "board/amcc/yucca/Kconfig"
261 258 source "board/avnet/fx12mm/Kconfig"
262 259 source "board/avnet/v5fx30teval/Kconfig"
263   -source "board/cray/L1/Kconfig"
264 260 source "board/csb272/Kconfig"
265 261 source "board/csb472/Kconfig"
266 262 source "board/dave/PPChameleonEVB/Kconfig"
board/cray/L1/.gitignore
View file @ 1521cdc
1   -bootscript.c
2   -bootscript.image
board/cray/L1/Kconfig
View file @ 1521cdc
1   -if TARGET_CRAYL1
2   -
3   -config SYS_BOARD
4   - default "L1"
5   -
6   -config SYS_VENDOR
7   - default "cray"
8   -
9   -config SYS_CONFIG_NAME
10   - default "CRAYL1"
11   -
12   -endif
board/cray/L1/L1.c
View file @ 1521cdc
1   -/*
2   - * (C) Copyright 2000
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -#include <asm/processor.h>
10   -#include <asm/ppc4xx-i2c.h>
11   -#include <command.h>
12   -#include <rtc.h>
13   -#include <post.h>
14   -#include <net.h>
15   -#include <malloc.h>
16   -
17   -#define L1_MEMSIZE (32*1024*1024)
18   -
19   -/* the std. DHCP stufff */
20   -#define DHCP_ROUTER 3
21   -#define DHCP_NETMASK 1
22   -#define DHCP_BOOTFILE 67
23   -#define DHCP_ROOTPATH 17
24   -#define DHCP_HOSTNAME 12
25   -
26   -/* some extras used by CRAY
27   - *
28   - * on the server this looks like:
29   - *
30   - * option L1-initrd-image code 224 = string;
31   - * option L1-initrd-image "/opt/craysv2/craymcu/l1/flash/initrd.image"
32   - */
33   -#define DHCP_L1_INITRD 224
34   -
35   -/* new, [better?] way via official vendor-extensions, defining an option
36   - * space.
37   - * on the server this looks like:
38   - *
39   - * option space CRAYL1;
40   - * option CRAYL1.initrd code 3 = string;
41   - * ..etc...
42   - */
43   -#define DHCP_VENDOR_SPECX 43
44   -#define DHCP_VX_INITRD 3
45   -#define DHCP_VX_BOOTCMD 4
46   -#define DHCP_VX_BOOTARGS 5
47   -#define DHCP_VX_ROOTDEV 6
48   -#define DHCP_VX_FROMFLASH 7
49   -#define DHCP_VX_BOOTSCRIPT 8
50   -#define DHCP_VX_RCFILE 9
51   -#define DHCP_VX_MAGIC 10
52   -
53   -/* Things DHCP server can tellme about. If there's no flash address, then
54   - * they dont participate in 'update' to flash, and we force their values
55   - * back to '0' every boot to be sure to get them fresh from DHCP. Yes, I
56   - * know this is a pain...
57   - *
58   - * If I get no bootfile, boot from flash. If rootpath, use that. If no
59   - * rootpath use initrd in flash.
60   - */
61   -typedef struct dhcp_item_s {
62   - u8 dhcp_option;
63   - u8 dhcp_vendor_option;
64   - char *dhcpvalue;
65   - char *envname;
66   -} dhcp_item_t;
67   -static dhcp_item_t Things[] = {
68   - {DHCP_ROUTER, 0, NULL, "gateway"},
69   - {DHCP_NETMASK, 0, NULL, "netmask"},
70   - {DHCP_BOOTFILE, 0, NULL, "bootfile"},
71   - {DHCP_ROOTPATH, 0, NULL, "rootpath"},
72   - {DHCP_HOSTNAME, 0, NULL, "hostname"},
73   - {DHCP_L1_INITRD, 0, NULL, "initrd"},
74   -/* and the other way.. */
75   - {DHCP_VENDOR_SPECX, DHCP_VX_INITRD, NULL, "initrd"},
76   - {DHCP_VENDOR_SPECX, DHCP_VX_BOOTCMD, NULL, "bootcmd"},
77   - {DHCP_VENDOR_SPECX, DHCP_VX_FROMFLASH, NULL, "fromflash"},
78   - {DHCP_VENDOR_SPECX, DHCP_VX_BOOTSCRIPT, NULL, "bootscript"},
79   - {DHCP_VENDOR_SPECX, DHCP_VX_RCFILE, NULL, "rcfile"},
80   - {DHCP_VENDOR_SPECX, DHCP_VX_BOOTARGS, NULL, "xbootargs"},
81   - {DHCP_VENDOR_SPECX, DHCP_VX_ROOTDEV, NULL, NULL},
82   - {DHCP_VENDOR_SPECX, DHCP_VX_MAGIC, NULL, NULL}
83   -};
84   -
85   -#define N_THINGS ((sizeof(Things))/(sizeof(dhcp_item_t)))
86   -
87   -extern char bootscript[];
88   -
89   -/* Here is the boot logic as HUSH script. Overridden by any TFP provided
90   - * bootscript file.
91   - */
92   -
93   -static void init_sdram (void);
94   -
95   -/* ------------------------------------------------------------------------- */
96   -int board_early_init_f (void)
97   -{
98   - /* Running from ROM: global data is still READONLY */
99   - init_sdram ();
100   - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
101   - mtdcr (UIC0ER, 0x00000000); /* disable all ints */
102   - mtdcr (UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */
103   - mtdcr (UIC0PR, 0xFFFFFFE0); /* set int polarities */
104   - mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
105   - mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
106   - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
107   - return 0;
108   -}
109   -
110   -/* ------------------------------------------------------------------------- */
111   -int checkboard (void)
112   -{
113   - return (0);
114   -}
115   -/* ------------------------------------------------------------------------- */
116   -
117   -/* ------------------------------------------------------------------------- */
118   -int misc_init_r (void)
119   -{
120   - char *s, *e;
121   - image_header_t *hdr;
122   - time_t timestamp;
123   - struct rtc_time tm;
124   - char bootcmd[32];
125   -
126   - hdr = (image_header_t *) (CONFIG_SYS_MONITOR_BASE - image_get_header_size ());
127   -#if defined(CONFIG_FIT)
128   - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
129   - puts ("Non legacy image format not supported\n");
130   - return -1;
131   - }
132   -#endif
133   -
134   - timestamp = (time_t)image_get_time (hdr);
135   - to_tm (timestamp, &tm);
136   - printf ("Welcome to U-Boot on Cray L1. Compiled %4d-%02d-%02d %2d:%02d:%02d (UTC)\n", tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec);
137   -
138   -#define FACTORY_SETTINGS 0xFFFC0000
139   - if ((s = getenv ("ethaddr")) == NULL) {
140   - e = (char *) (FACTORY_SETTINGS);
141   - if (*(e + 0) != '0'
142   - || *(e + 1) != '0'
143   - || *(e + 2) != ':'
144   - || *(e + 3) != '4' || *(e + 4) != '0' || *(e + 17) != '\0') {
145   - printf ("No valid MAC address in flash location 0x3C0000!\n");
146   - } else {
147   - printf ("Factory MAC: %s\n", e);
148   - setenv ("ethaddr", e);
149   - }
150   - }
151   - sprintf (bootcmd,"source %X",(unsigned)bootscript);
152   - setenv ("bootcmd", bootcmd);
153   - return (0);
154   -}
155   -
156   -/* ------------------------------------------------------------------------- */
157   -/* stubs so we can print dates w/o any nvram RTC.*/
158   -int rtc_get (struct rtc_time *tmp)
159   -{
160   - return 0;
161   -}
162   -int rtc_set (struct rtc_time *tmp)
163   -{
164   - return 0;
165   -}
166   -void rtc_reset (void)
167   -{
168   - return;
169   -}
170   -
171   -/* ------------------------------------------------------------------------- */
172   -/* Do sdram bank init in C so I can read it..no console to print to yet!
173   - */
174   -static void init_sdram (void)
175   -{
176   - unsigned long tmp;
177   -
178   - /* write SDRAM bank 0 register */
179   - mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
180   - mtdcr (SDRAM0_CFGDATA, 0x00062001);
181   -
182   -/* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */
183   -/* To set the appropriate timings, we need to know the SDRAM speed. */
184   -/* We can use the PLB speed since the SDRAM speed is the same as */
185   -/* the PLB speed. The PLB speed is the FBK divider times the */
186   -/* 405GP reference clock, which on the L1 is 25MHz. */
187   -/* Thus, if FBK div is 2, SDRAM is 50MHz; if FBK div is 3, SDRAM is */
188   -/* 150MHz; if FBK is 3, SDRAM is 150MHz. */
189   -
190   - /* divisor = ((mfdcr(strap)>> 28) & 0x3); */
191   -
192   -/* write SDRAM timing for 100MHz. */
193   - mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
194   - mtdcr (SDRAM0_CFGDATA, 0x0086400D);
195   -
196   -/* write SDRAM refresh interval register */
197   - mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
198   - mtdcr (SDRAM0_CFGDATA, 0x05F00000);
199   - udelay (200);
200   -
201   -/* sdram controller.*/
202   - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
203   - mtdcr (SDRAM0_CFGDATA, 0x90800000);
204   - udelay (200);
205   -
206   -/* initially, disable ECC on all banks */
207   - udelay (200);
208   - mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
209   - tmp = mfdcr (SDRAM0_CFGDATA);
210   - tmp &= 0xff0fffff;
211   - mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
212   - mtdcr (SDRAM0_CFGDATA, tmp);
213   -
214   - return;
215   -}
216   -
217   -extern int memory_post_test (int flags);
218   -
219   -int testdram (void)
220   -{
221   - unsigned long tmp;
222   - uint *pstart = (uint *) 0x00000000;
223   - uint *pend = (uint *) L1_MEMSIZE;
224   - uint *p;
225   -
226   - if (getenv_f("booted",NULL,0) <= 0)
227   - {
228   - printf ("testdram..");
229   - /*AA*/
230   - for (p = pstart; p < pend; p++)
231   - *p = 0xaaaaaaaa;
232   - for (p = pstart; p < pend; p++) {
233   - if (*p != 0xaaaaaaaa) {
234   - printf ("SDRAM test fails at: %08x, was %08x expected %08x\n",
235   - (uint) p, *p, 0xaaaaaaaa);
236   - return 1;
237   - }
238   - }
239   - /*55*/
240   - for (p = pstart; p < pend; p++)
241   - *p = 0x55555555;
242   - for (p = pstart; p < pend; p++) {
243   - if (*p != 0x55555555) {
244   - printf ("SDRAM test fails at: %08x, was %08x expected %08x\n",
245   - (uint) p, *p, 0x55555555);
246   - return 1;
247   - }
248   - }
249   - /*addr*/
250   - for (p = pstart; p < pend; p++)
251   - *p = (unsigned)p;
252   - for (p = pstart; p < pend; p++) {
253   - if (*p != (unsigned)p) {
254   - printf ("SDRAM test fails at: %08x, was %08x expected %08x\n",
255   - (uint) p, *p, (uint)p);
256   - return 1;
257   - }
258   - }
259   - printf ("Success. ");
260   - }
261   - printf ("Enable ECC..");
262   -
263   - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
264   - tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000;
265   - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
266   - mtdcr (SDRAM0_CFGDATA, tmp);
267   - udelay (600);
268   - for (p = (unsigned long) 0; ((unsigned long) p < L1_MEMSIZE); *p++ = 0L)
269   - ;
270   - udelay (400);
271   - mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
272   - tmp = mfdcr (SDRAM0_CFGDATA);
273   - tmp |= 0x00800000;
274   - mtdcr (SDRAM0_CFGDATA, tmp);
275   - udelay (400);
276   - printf ("enabled.\n");
277   - return (0);
278   -}
279   -
280   -/* ------------------------------------------------------------------------- */
281   -static u8 *dhcp_env_update (u8 thing, u8 * pop)
282   -{
283   - u8 i, oplen;
284   -
285   - oplen = *(pop + 1);
286   -
287   - if ((Things[thing].dhcpvalue = malloc (oplen)) == NULL) {
288   - printf ("Whoops! failed to malloc space for DHCP thing %s\n",
289   - Things[thing].envname);
290   - return NULL;
291   - }
292   - for (i = 0; (i < oplen); i++)
293   - if ((*(Things[thing].dhcpvalue + i) = *(pop + 2 + i)) == ' ')
294   - break;
295   - *(Things[thing].dhcpvalue + i) = '\0';
296   -
297   -/* set env. */
298   - if (Things[thing].envname)
299   - {
300   - setenv (Things[thing].envname, Things[thing].dhcpvalue);
301   - }
302   - return ((u8 *)(Things[thing].dhcpvalue));
303   -}
304   -
305   -/* ------------------------------------------------------------------------- */
306   -u8 *dhcp_vendorex_prep (u8 * e)
307   -{
308   - u8 thing;
309   -
310   -/* ask for the things I want. */
311   - *e++ = 55; /* Parameter Request List */
312   - *e++ = N_THINGS;
313   - for (thing = 0; thing < N_THINGS; thing++)
314   - *e++ = Things[thing].dhcp_option;
315   - *e++ = 255;
316   -
317   - return e;
318   -}
319   -
320   -/* ------------------------------------------------------------------------- */
321   -/* .. return NULL means it wasnt mine, non-null means I got it..*/
322   -u8 *dhcp_vendorex_proc (u8 * pop)
323   -{
324   - u8 oplen, *sub_op, sub_oplen, *retval;
325   - u8 thing = 0;
326   -
327   - retval = NULL;
328   - oplen = *(pop + 1);
329   -/* if pop is vender spec indicator, there are sub-options. */
330   - if (*pop == DHCP_VENDOR_SPECX) {
331   - for (sub_op = pop + 2;
332   - oplen && (sub_oplen = *(sub_op + 1));
333   - oplen -= sub_oplen, sub_op += (sub_oplen + 2)) {
334   - for (thing = 0; thing < N_THINGS; thing++) {
335   - if (*sub_op == Things[thing].dhcp_vendor_option) {
336   - if (!(retval = dhcp_env_update (thing, sub_op))) {
337   - return NULL;
338   - }
339   - }
340   - }
341   - }
342   - } else {
343   - for (thing = 0; thing < N_THINGS; thing++) {
344   - if (*pop == Things[thing].dhcp_option)
345   - if (!(retval = dhcp_env_update (thing, pop)))
346   - return NULL;
347   - }
348   - }
349   - return (pop);
350   -}
board/cray/L1/MAINTAINERS
View file @ 1521cdc
1   -L1 BOARD
2   -#M: David Updegraff <dave@cray.com>
3   -S: Orphan (since 2014-03)
4   -F: board/cray/L1/
5   -F: include/configs/CRAYL1.h
6   -F: configs/CRAYL1_defconfig
board/cray/L1/Makefile
View file @ 1521cdc
1   -#
2   -# (C) Copyright 2000-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -obj-y = L1.o flash.o
9   -obj-y += init.o
10   -obj-y += bootscript.o
11   -
12   -quiet_cmd_awk = AWK $@
13   - cmd_awk = od -t x1 -v -A x $< | $(AWK) -f $(filter-out $<,$^) > $@
14   -
15   -$(obj)/bootscript.c: $(obj)/bootscript.image $(src)/x2c.awk
16   - $(call cmd,awk)
17   -
18   -MKIMAGEFLAGS_bootscript.image := -A ppc -O linux -T script -C none \
19   - -a 0 -e 0 -n bootscript
20   -$(obj)/bootscript.image: $(src)/bootscript.hush
21   - $(call cmd,mkimage)
22   -
23   -clean-files := bootscript.c bootscript.image
board/cray/L1/bootscript.hush
View file @ 1521cdc
1   -# $Header$
2   -# hush bootscript for PPCBOOT on L1
3   -# note: all #s are in hex, do _NOT_ prefix it with 0x
4   -
5   -flash_rfs=ffc00000
6   -flash_krl=fff00000
7   -tftp_addr=100000
8   -tftp2_addr=1000000
9   -
10   -if printenv booted
11   -then
12   - echo already booted before
13   -else
14   - echo first boot in environment, create and save settings
15   - setenv booted OK
16   - saveenv
17   -fi
18   -
19   -setenv autoload no
20   -# clear out stale env stuff, so we get fresh from dhcp.
21   -for setting in initrd fromflash kernel rootfs rootpath
22   -do
23   -setenv $setting
24   -done
25   -
26   -dhcp
27   -
28   -# if host provides us with a different bootscript, us it.
29   -if printenv bootscript
30   - then
31   - tftp $tftp_addr $bootcript
32   - if imi $tftp_addr
33   - then
34   - source $tftp_addr
35   - fi
36   -fi
37   -
38   -# default base kernel arguments.
39   -setenv bootargs $xbootargs devfs=mount ip=$ipaddr:$serverip:$gatewayip:$netmask:L1:eth0:off wdt=120
40   -
41   -# Have a kernel in flash?
42   -if imi $flash_krl
43   -then
44   - echo ok kernel to boot from $flash_krl
45   - setenv kernel $flash_krl
46   -else
47   - echo no kernel to boot from $flash_krl, need tftp
48   -fi
49   -
50   -# Have a rootfs in flash?
51   -echo test for SQUASHfs at $flash_rfs
52   -
53   -if imi $flash_rfs
54   -then
55   - echo appears to be a good initrd image at base of flash OK
56   - setenv rootfs $flash_rfs
57   -else
58   - echo no image at base of flash, need nfsroot or initrd
59   -fi
60   -
61   -# I boot from flash if told to and I can.
62   -if printenv fromflash && printenv kernel && printenv rootfs
63   -then
64   - echo booting entirely from flash
65   - setenv bootargs root=/dev/ram0 rw $bootargs
66   - bootm $kernel $rootfs
67   - echo oh no failed so I try some other stuff
68   -fi
69   -
70   -# TFTP down a kernel
71   -if printenv bootfile
72   -then
73   - tftp $tftp_addr $bootfile
74   - setenv kernel $tftp_addr
75   - echo I will boot the TFTP kernel
76   -else
77   - if printenv kernel
78   - then
79   - echo no bootfile specified, will use one from flash
80   - else
81   - setenv bootfile /opt/crayx1/craymcu/l1/flash/linux.image
82   - echo OH NO! we have no bootfile,nor flash kernel! try default: $bootfile
83   - tftp $tftp_addr $bootfile
84   - setenv kernel $tftp_addr
85   - fi
86   -fi
87   -
88   -# the rootfs.
89   -if printenv rootpath
90   -then
91   - echo rootpath is $rootpath
92   - if printenv initrd
93   - then
94   - echo initrd is also specified, so use $initrd
95   - tftp $tftp2_addr $initrd
96   - setenv bootargs root=/dev/ram0 rw cwsroot=$serverip:$rootpath $bootargs
97   - bootm $kernel $tftp2_addr
98   - else
99   - echo initrd is not specified, so use NFSROOT $rootpat
100   - setenv bootargs root=/dev/nfs ro nfsroot=$serverip:$rootpath $bootargs
101   - bootm $kernel
102   - fi
103   -else
104   - echo we have no rootpath check for one in flash
105   - if printenv rootfs
106   - then
107   - echo I will use the one in flash
108   - setenv bootargs root=/dev/mtdblock/0 ro rootfstype=squashfs $bootargs
109   - bootm $kernel
110   - else
111   - setenv rootpath /export/crayl1
112   - echo OH NO! we have no rootpath,nor flash kernel! try default: $rootpath
113   - setenv bootargs root=/dev/mtdblock/0 ro rootfstype=squashfs $bootargs
114   - bootm $kernel
115   - fi
116   -fi
117   -reset
board/cray/L1/flash.c
View file @ 1521cdc
1   -/*
2   - * (C) Copyright 2000
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -/*
9   - * Modified 4/5/2001
10   - * Wait for completion of each sector erase command issued
11   - * 4/5/2001
12   - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
13   - */
14   -
15   -/*
16   - * Modified July 20, 2001
17   - * Strip down to support ONLY the AMD29F032B.
18   - * Dave Updegraff - Cray, Inc. dave@cray.com
19   - */
20   -
21   -#include <common.h>
22   -#include <asm/ppc4xx.h>
23   -#include <asm/processor.h>
24   -
25   -/* The flash chip we use... */
26   -#define AMD_ID_F032B 0x41 /* 29F032B ID 32 Mbit,64 64Kx8 sectors */
27   -#define FLASH_AM320B 0x0009
28   -
29   -
30   -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
31   -
32   -/*-----------------------------------------------------------------------
33   - * Functions
34   - */
35   -static ulong flash_get_size (vu_long *addr, flash_info_t *info);
36   -static int write_word (flash_info_t *info, ulong dest, ulong data);
37   -static void flash_get_offsets (ulong base, flash_info_t *info);
38   -
39   -#define ADDR0 0x5555
40   -#define ADDR1 0x2aaa
41   -#define FLASH_WORD_SIZE unsigned char
42   -
43   -/*-----------------------------------------------------------------------
44   - */
45   -
46   -unsigned long flash_init (void)
47   -{
48   - unsigned long size_b0, size_b1;
49   - int i;
50   -
51   - /* Init: no FLASHes known */
52   - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
53   - flash_info[i].flash_id = FLASH_UNKNOWN;
54   - }
55   -
56   - /* Static FLASH Bank configuration here - FIXME XXX */
57   -
58   - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
59   -
60   - if (flash_info[0].flash_id == FLASH_UNKNOWN) {
61   - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
62   - size_b0, size_b0<<20);
63   - }
64   -
65   - /* Only one bank */
66   - if (CONFIG_SYS_MAX_FLASH_BANKS == 1)
67   - {
68   - /* Setup offsets */
69   - flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
70   -
71   -#if 0
72   - /* Monitor protection ON by default */
73   - (void)flash_protect(FLAG_PROTECT_SET,
74   - FLASH_BASE0_PRELIM,
75   - FLASH_BASE0_PRELIM+monitor_flash_len-1,
76   - &flash_info[0]);
77   -#endif
78   - size_b1 = 0 ;
79   - flash_info[0].size = size_b0;
80   - }
81   -
82   - return (size_b0 + size_b1);
83   -}
84   -
85   -
86   -/*-----------------------------------------------------------------------
87   - */
88   -static void flash_get_offsets (ulong base, flash_info_t *info)
89   -{
90   - int i;
91   -
92   - /* set up sector start address table */
93   - for (i = 0; i < info->sector_count; i++)
94   - info->start[i] = base + (i * 0x00010000);
95   -}
96   -
97   -/*-----------------------------------------------------------------------
98   - */
99   -void flash_print_info (flash_info_t *info)
100   -{
101   - int i;
102   - int k;
103   - int size;
104   - int erased;
105   - volatile unsigned long *flash;
106   -
107   - if (info->flash_id == FLASH_UNKNOWN) {
108   - printf ("missing or unknown FLASH type\n");
109   - return;
110   - }
111   -
112   - switch (info->flash_id & FLASH_VENDMASK) {
113   - case FLASH_MAN_AMD: printf ("AMD "); break;
114   - default: printf ("Unknown Vendor "); break;
115   - }
116   -
117   - switch (info->flash_id & FLASH_TYPEMASK) {
118   - case FLASH_AM320B:printf ("AM29F032B (32 Mbit 64x64KB uniform sectors)\n");
119   - break;
120   - default: printf ("Unknown Chip Type\n");
121   - break;
122   - }
123   -
124   - printf (" Size: %ld KB in %d Sectors\n",
125   - info->size >> 10, info->sector_count);
126   -
127   - printf (" Sector Start Addresses:");
128   - for (i=0; i<info->sector_count; ++i) {
129   - /*
130   - * Check if whole sector is erased
131   - */
132   - if (i != (info->sector_count-1))
133   - size = info->start[i+1] - info->start[i];
134   - else
135   - size = info->start[0] + info->size - info->start[i];
136   - erased = 1;
137   - flash = (volatile unsigned long *)info->start[i];
138   - size = size >> 2; /* divide by 4 for longword access */
139   - for (k=0; k<size; k++)
140   - {
141   - if (*flash++ != 0xffffffff)
142   - {
143   - erased = 0;
144   - break;
145   - }
146   - }
147   -
148   - if ((i % 5) == 0)
149   - printf ("\n ");
150   -
151   - printf (" %08lX%s%s",
152   - info->start[i],
153   - erased ? " E" : " ",
154   - info->protect[i] ? "RO " : " "
155   - );
156   - }
157   - printf ("\n");
158   -}
159   -
160   -/*-----------------------------------------------------------------------
161   - */
162   -
163   -
164   -/*-----------------------------------------------------------------------
165   - */
166   -
167   -/*
168   - * The following code cannot be run from FLASH!
169   - */
170   -static ulong flash_get_size (vu_long *addr, flash_info_t *info)
171   -{
172   - short i;
173   - FLASH_WORD_SIZE value;
174   - ulong base = (ulong)addr;
175   - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
176   -
177   - /* Write auto select command: read Manufacturer ID */
178   - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
179   - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
180   - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
181   -
182   - value = addr2[0];
183   -
184   - switch (value) {
185   - case (FLASH_WORD_SIZE)AMD_MANUFACT:
186   - info->flash_id = FLASH_MAN_AMD;
187   - break;
188   - default:
189   - info->flash_id = FLASH_UNKNOWN;
190   - info->sector_count = 0;
191   - info->size = 0;
192   - return (0); /* no or unknown flash */
193   - }
194   -
195   - value = addr2[1]; /* device ID */
196   -
197   - switch (value) {
198   - case (FLASH_WORD_SIZE)AMD_ID_F032B:
199   - info->flash_id += FLASH_AM320B;
200   - info->sector_count = 64;
201   - info->size = 0x0400000; /* => 4 MB */
202   - break;
203   - default:
204   - info->flash_id = FLASH_UNKNOWN;
205   - return (0); /* => no or unknown flash */
206   -
207   - }
208   -
209   - /* set up sector start address table */
210   - for (i = 0; i < info->sector_count; i++)
211   - info->start[i] = base + (i * 0x00010000);
212   -
213   - /* check for protected sectors */
214   - for (i = 0; i < info->sector_count; i++) {
215   - /* read sector protection at sector address, (A7 .. A0) = 0x02 */
216   - /* D0 = 1 if protected */
217   - addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
218   - info->protect[i] = addr2[2] & 1;
219   - }
220   -
221   - /*
222   - * Prevent writes to uninitialized FLASH.
223   - */
224   - if (info->flash_id != FLASH_UNKNOWN) {
225   - addr2 = (FLASH_WORD_SIZE *)info->start[0];
226   - *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
227   - }
228   -
229   - return (info->size);
230   -}
231   -
232   -int wait_for_DQ7(flash_info_t *info, int sect)
233   -{
234   - ulong start, now, last;
235   - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
236   -
237   - start = get_timer (0);
238   - last = start;
239   - while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
240   - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
241   - printf ("Timeout\n");
242   - return -1;
243   - }
244   - /* show that we're waiting */
245   - if ((now - last) > 1000) { /* every second */
246   - putc ('.');
247   - last = now;
248   - }
249   - }
250   - return 0;
251   -}
252   -
253   -/*-----------------------------------------------------------------------
254   - */
255   -
256   -int flash_erase (flash_info_t *info, int s_first, int s_last)
257   -{
258   - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
259   - volatile FLASH_WORD_SIZE *addr2;
260   - int flag, prot, sect;
261   -
262   - if ((s_first < 0) || (s_first > s_last)) {
263   - if (info->flash_id == FLASH_UNKNOWN) {
264   - printf ("- missing\n");
265   - } else {
266   - printf ("- no sectors to erase\n");
267   - }
268   - return 1;
269   - }
270   -
271   - if (info->flash_id == FLASH_UNKNOWN) {
272   - printf ("Can't erase unknown flash type - aborted\n");
273   - return 1;
274   - }
275   -
276   - prot = 0;
277   - for (sect=s_first; sect<=s_last; ++sect) {
278   - if (info->protect[sect]) {
279   - prot++;
280   - }
281   - }
282   -
283   - if (prot) {
284   - printf ("- Warning: %d protected sectors will not be erased!\n",
285   - prot);
286   - } else {
287   - printf ("\n");
288   - }
289   -
290   - /* Disable interrupts which might cause a timeout here */
291   - flag = disable_interrupts();
292   -
293   - /* Start erase on unprotected sectors */
294   - for (sect = s_first; sect<=s_last; sect++) {
295   - if (info->protect[sect] == 0) { /* not protected */
296   - addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
297   - printf("Erasing sector %p\n", addr2);
298   -
299   - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
300   - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
301   - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
302   - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
303   - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
304   - addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
305   - /*
306   - * Wait for each sector to complete, it's more
307   - * reliable. According to AMD Spec, you must
308   - * issue all erase commands within a specified
309   - * timeout. This has been seen to fail, especially
310   - * if printf()s are included (for debug)!!
311   - */
312   - wait_for_DQ7(info, sect);
313   - }
314   - }
315   -
316   - /* re-enable interrupts if necessary */
317   - if (flag)
318   - enable_interrupts();
319   -
320   - /* wait at least 80us - let's wait 1 ms */
321   - udelay (1000);
322   -
323   - /* reset to read mode */
324   - addr = (FLASH_WORD_SIZE *)info->start[0];
325   - addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
326   -
327   - printf (" done\n");
328   - return 0;
329   -}
330   -
331   -/*-----------------------------------------------------------------------
332   - * Copy memory to flash, returns:
333   - * 0 - OK
334   - * 1 - write timeout
335   - * 2 - Flash not erased
336   - */
337   -
338   -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
339   -{
340   - ulong cp, wp, data;
341   - int i, l, rc;
342   -
343   - wp = (addr & ~3); /* get lower word aligned address */
344   -
345   - /*
346   - * handle unaligned start bytes
347   - */
348   - if ((l = addr - wp) != 0) {
349   - data = 0;
350   - for (i=0, cp=wp; i<l; ++i, ++cp) {
351   - data = (data << 8) | (*(uchar *)cp);
352   - }
353   - for (; i<4 && cnt>0; ++i) {
354   - data = (data << 8) | *src++;
355   - --cnt;
356   - ++cp;
357   - }
358   - for (; cnt==0 && i<4; ++i, ++cp) {
359   - data = (data << 8) | (*(uchar *)cp);
360   - }
361   -
362   - if ((rc = write_word(info, wp, data)) != 0) {
363   - return (rc);
364   - }
365   - wp += 4;
366   - }
367   -
368   - /*
369   - * handle word aligned part
370   - */
371   - while (cnt >= 4) {
372   - data = 0;
373   - for (i=0; i<4; ++i) {
374   - data = (data << 8) | *src++;
375   - }
376   - if ((rc = write_word(info, wp, data)) != 0) {
377   - return (rc);
378   - }
379   - wp += 4;
380   - cnt -= 4;
381   - }
382   -
383   - if (cnt == 0) {
384   - return (0);
385   - }
386   -
387   - /*
388   - * handle unaligned tail bytes
389   - */
390   - data = 0;
391   - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
392   - data = (data << 8) | *src++;
393   - --cnt;
394   - }
395   - for (; i<4; ++i, ++cp) {
396   - data = (data << 8) | (*(uchar *)cp);
397   - }
398   -
399   - return (write_word(info, wp, data));
400   -}
401   -
402   -/*-----------------------------------------------------------------------
403   - * Write a word to Flash, returns:
404   - * 0 - OK
405   - * 1 - write timeout
406   - * 2 - Flash not erased
407   - */
408   -static int write_word (flash_info_t *info, ulong dest, ulong data)
409   -{
410   - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]);
411   - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest;
412   - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
413   - ulong start;
414   - int flag;
415   - int i;
416   -
417   - /* Check if Flash is (sufficiently) erased */
418   - if ((*((volatile FLASH_WORD_SIZE *)dest) &
419   - (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
420   - return (2);
421   - }
422   - /* Disable interrupts which might cause a timeout here */
423   - flag = disable_interrupts();
424   -
425   - for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++)
426   - {
427   - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
428   - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
429   - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0;
430   -
431   - dest2[i] = data2[i];
432   -
433   - /* re-enable interrupts if necessary */
434   - if (flag)
435   - enable_interrupts();
436   -
437   - /* data polling for D7 */
438   - start = get_timer (0);
439   - while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) !=
440   - (data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
441   - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
442   - return (1);
443   - }
444   - }
445   - }
446   -
447   - return (0);
448   -}
449   -
450   -/*-----------------------------------------------------------------------
451   - */
board/cray/L1/init.S
View file @ 1521cdc
1   -/*
2   - * SPDX-License-Identifier: GPL-2.0 IBM-pibs
3   - */
4   -
5   -/*----------------------------------------------------------------------------- */
6   -/* Function: ext_bus_cntlr_init */
7   -/* Description: Initializes the External Bus Controller for the external */
8   -/* peripherals. IMPORTANT: For pass1 this code must run from */
9   -/* cache since you can not reliably change a peripheral banks */
10   -/* timing register (pbxap) while running code from that bank. */
11   -/* For ex., since we are running from ROM on bank 0, we can NOT */
12   -/* execute the code that modifies bank 0 timings from ROM, so */
13   -/* we run it from cache. */
14   -/* Bank 0 - Flash and SRAM */
15   -/* Bank 1 - NVRAM/RTC */
16   -/* Bank 2 - Keyboard/Mouse controller */
17   -/* Bank 3 - IR controller */
18   -/* Bank 4 - not used */
19   -/* Bank 5 - not used */
20   -/* Bank 6 - not used */
21   -/* Bank 7 - FPGA registers */
22   -/*-----------------------------------------------------------------------------#include <config.h> */
23   -#include <asm/ppc4xx.h>
24   -
25   -#include <ppc_asm.tmpl>
26   -#include <ppc_defs.h>
27   -
28   -#include <asm/cache.h>
29   -#include <asm/mmu.h>
30   -
31   -/* CRAY - L1: only nominally a 'walnut', since ext.Bus.Cntlr is all empty */
32   -/* except for #1 which we use for DMA'ing to IOCA-like things, so the */
33   -/* control registers to set that up are determined by what we've */
34   -/* empirically discovered work there. */
35   -
36   - .globl ext_bus_cntlr_init
37   -ext_bus_cntlr_init:
38   - mflr r4 /* save link register */
39   - bl ..getAddr
40   -..getAddr:
41   - mflr r3 /* get address of ..getAddr */
42   - mtlr r4 /* restore link register */
43   - addi r4,0,14 /* set ctr to 10; used to prefetch */
44   - mtctr r4 /* 10 cache lines to fit this function */
45   - /* in cache (gives us 8x10=80 instrctns) */
46   -..ebcloop:
47   - icbt r0,r3 /* prefetch cache line for addr in r3 */
48   - addi r3,r3,32 /* move to next cache line */
49   - bdnz ..ebcloop /* continue for 10 cache lines */
50   -
51   - /*------------------------------------------------------------------- */
52   - /* Delay to ensure all accesses to ROM are complete before changing */
53   - /* bank 0 timings. 200usec should be enough. */
54   - /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
55   - /*------------------------------------------------------------------- */
56   - addis r3,0,0x0
57   - ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
58   - mtctr r3
59   -..spinlp:
60   - bdnz ..spinlp /* spin loop */
61   -
62   -
63   - /*---------------------------------------------------------------------- */
64   - /* Peripheral Bank 0 (Flash) initialization */
65   - /*---------------------------------------------------------------------- */
66   - /* 0x7F8FFE80 slowest boot */
67   - addi r4,0,PB1AP
68   - mtdcr EBC0_CFGADDR,r4
69   - addis r4,0,0x9B01
70   - ori r4,r4,0x5480
71   - mtdcr EBC0_CFGDATA,r4
72   -
73   - addi r4,0,PB0CR
74   - mtdcr EBC0_CFGADDR,r4
75   - addis r4,0,0xFFC5 /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */
76   - ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
77   - mtdcr EBC0_CFGDATA,r4
78   -
79   - blr
80   -
81   - /*---------------------------------------------------------------------- */
82   - /* Peripheral Bank 1 (NVRAM/RTC) initialization */
83   - /* CRAY:the L1 has NOT this bank, it is tied to SV2/IOCA/etc/ instead */
84   - /* and we do DMA on it. The ConfigurationRegister part is threfore */
85   - /* almost arbitrary, except that our linux driver needs to know the */
86   - /* address, but it can query, it.. */
87   - /* */
88   - /* The AccessParameter is CRITICAL, */
89   - /* thouch, since it needs to agree with the electrical timings on the */
90   - /* IOCA parallel interface. That value is: 0x0185,4380 */
91   - /* BurstModeEnable BME=0 */
92   - /* TransferWait TWT=3 */
93   - /* ChipSelectOnTiming CSN=1 */
94   - /* OutputEnableOnTimimg OEN=1 */
95   - /* WriteByteEnableOnTiming WBN=1 */
96   - /* WriteByteEnableOffTiming WBF=0 */
97   - /* TransferHold TH=1 */
98   - /* ReadyEnable RE=1 */
99   - /* SampleOnReady SOR=1 */
100   - /* ByteEnableMode BEM=0 */
101   - /* ParityEnable PEN=0 */
102   - /* all reserved bits=0 */
103   - /*---------------------------------------------------------------------- */
104   - /*---------------------------------------------------------------------- */
105   - addi r4,0,PB1AP
106   - mtdcr EBC0_CFGADDR,r4
107   - addis r4,0,0x0185 /* hiword */
108   - ori r4,r4,0x4380 /* loword */
109   - mtdcr EBC0_CFGDATA,r4
110   -
111   - addi r4,0,PB1CR
112   - mtdcr EBC0_CFGADDR,r4
113   - addis r4,0,0xF001 /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */
114   - ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
115   - mtdcr EBC0_CFGDATA,r4
116   -
117   - blr
board/cray/L1/patchme
View file @ 1521cdc
1   -# master confi.mk
2   -echo "CROSS_COMPILE = powerpc-linux-" >>include/config.mk
3   -
4   -# patch the examples/Makefile to ignore return value from OBJCOPY
5   -sed -e 's/$(OBJCOPY)/-&/' < examples/Makefile > examples/makefile
6   -
7   -# add a built target for mkimage on the target architecture
8   -sed -e 's/^all:.*$/all: .depend envcrc mkimage mkimage.ppc/' < tools/Makefile > tools/makefile
9   -
10   -cat <<EOF >>tools/makefile
11   -mkimage.ppc : mkimage.o.ppc crc32.o.ppc
12   - powerpc-linux-gcc -msoft-float -Wall -Wstrict-prototypes -o \$@ \$^
13   - powerpc-linux-strip $@
14   -
15   -XFLAGS="-D__KERNEL__ -I../include -DCONFIG_4xx -Wall -Wstict-prototypes"
16   -mkimage.o.ppc: mkimage.c
17   - powerpc-linux-gcc -msoft-float -Wall -I../include -c -o \$@ \$^
18   -
19   -crc32.o.ppc: crc32.c
20   - powerpc-linux-gcc -msoft-float -Wall -I../include -c -o \$@ \$^
21   -
22   -EOF
23   -
24   -# make an image by default out of the u-boot image
25   -sed -e 's/^all:.*$/all: u-boot.image /' < Makefile > makefile
26   -cat <<EOF >>makefile
27   -u-boot.image: u-boot.bin
28   - tools/mkimage -A ppc -O linux -T firmware -C none -a 0 -e 0 -n U-Boot -d \$^ \$@
29   -
30   -EOF
board/cray/L1/u-boot.lds.debug
View file @ 1521cdc
1   -/*
2   - * (C) Copyright 2000
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -OUTPUT_ARCH(powerpc)
9   -/* Do we need any of these for elf?
10   - __DYNAMIC = 0; */
11   -SECTIONS
12   -{
13   - /* Read-only sections, merged into text segment: */
14   - . = + SIZEOF_HEADERS;
15   - .interp : { *(.interp) }
16   - .hash : { *(.hash) }
17   - .dynsym : { *(.dynsym) }
18   - .dynstr : { *(.dynstr) }
19   - .rel.text : { *(.rel.text) }
20   - .rela.text : { *(.rela.text) }
21   - .rel.data : { *(.rel.data) }
22   - .rela.data : { *(.rela.data) }
23   - .rel.rodata : { *(.rel.rodata) }
24   - .rela.rodata : { *(.rela.rodata) }
25   - .rel.got : { *(.rel.got) }
26   - .rela.got : { *(.rela.got) }
27   - .rel.ctors : { *(.rel.ctors) }
28   - .rela.ctors : { *(.rela.ctors) }
29   - .rel.dtors : { *(.rel.dtors) }
30   - .rela.dtors : { *(.rela.dtors) }
31   - .rel.bss : { *(.rel.bss) }
32   - .rela.bss : { *(.rela.bss) }
33   - .rel.plt : { *(.rel.plt) }
34   - .rela.plt : { *(.rela.plt) }
35   - .init : { *(.init) }
36   - .plt : { *(.plt) }
37   - .text :
38   - {
39   - /* WARNING - the following is hand-optimized to fit within */
40   - /* the sector layout of our flash chips! XXX FIXME XXX */
41   -
42   - mpc8xx/start.o (.text)
43   - common/dlmalloc.o (.text)
44   - lib/vsprintf.o (.text)
45   - lib/crc32.o (.text)
46   - arch/powerpc/lib/extable.o (.text)
47   -
48   - common/env_embedded.o(.text)
49   -
50   - *(.text)
51   - *(.got1)
52   - }
53   - _etext = .;
54   - PROVIDE (etext = .);
55   - .rodata :
56   - {
57   - *(.rodata)
58   - *(.rodata1)
59   - *(.rodata.str1.4)
60   - *(.eh_frame)
61   - }
62   - .fini : { *(.fini) } =0
63   - .ctors : { *(.ctors) }
64   - .dtors : { *(.dtors) }
65   -
66   - /* Read-write section, merged into data segment: */
67   - . = (. + 0x0FFF) & 0xFFFFF000;
68   - _erotext = .;
69   - PROVIDE (erotext = .);
70   - .reloc :
71   - {
72   - *(.got)
73   - _GOT2_TABLE_ = .;
74   - *(.got2)
75   - _FIXUP_TABLE_ = .;
76   - *(.fixup)
77   - }
78   - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
79   - __fixup_entries = (. - _FIXUP_TABLE_)>>2;
80   -
81   - .data :
82   - {
83   - *(.data)
84   - *(.data1)
85   - *(.sdata)
86   - *(.sdata2)
87   - *(.dynamic)
88   - CONSTRUCTORS
89   - }
90   - _edata = .;
91   - PROVIDE (edata = .);
92   -
93   -
94   - . = ALIGN(4);
95   - .u_boot_list : {
96   - KEEP(*(SORT(.u_boot_list*)));
97   - }
98   -
99   -
100   - __start___ex_table = .;
101   - __ex_table : { *(__ex_table) }
102   - __stop___ex_table = .;
103   -
104   - . = ALIGN(4096);
105   - __init_begin = .;
106   - .text.init : { *(.text.init) }
107   - .data.init : { *(.data.init) }
108   - . = ALIGN(4096);
109   - __init_end = .;
110   -
111   - __bss_start = .;
112   - .bss :
113   - {
114   - *(.sbss) *(.scommon)
115   - *(.dynbss)
116   - *(.bss)
117   - *(COMMON)
118   - }
119   - __bss_end = . ;
120   - PROVIDE (end = .);
121   -}
board/cray/L1/x2c.awk
View file @ 1521cdc
1   -#!/bin/awk
2   -BEGIN { print "unsigned char bootscript[] = { \n"}
3   -{ for (i = 2; i <= NF ; i++ ) printf "0x"$i","
4   - print ""
5   -}
6   -END { print "\n};\n" }
configs/CRAYL1_defconfig
View file @ 1521cdc
1   -CONFIG_PPC=y
2   -CONFIG_4xx=y
3   -CONFIG_TARGET_CRAYL1=y
doc/README.scrapyard
Diff comments   View file @ 1521cdc
... ... @@ -12,6 +12,7 @@
12 12  
13 13 Board Arch CPU Commit Removed Last known maintainer/contact
14 14 =================================================================================================
  15 +CRAYL1 powerpc ppc4xx - - David Updegraff <dave@cray.com>
15 16 KAREF powerpc ppc4xx - - Travis Sawyer <travis.sawyer@sandburst.com>
16 17 METROBOX powerpc ppc4xx - - Travis Sawyer <travis.sawyer@sandburst.com>
17 18 PK1C20 nios2 - 70fbc461 2014-08-24 Scott McNutt <smcnutt@psyent.com>
include/configs/CRAYL1.h
View file @ 1521cdc
1   -/*
2   - * (C) Copyright 2000-2004
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - * David Updegraff, Cray, Inc. dave@cray.com: our 405 is walnut-lite..
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -/*
9   - * board/config.h - configuration options, board specific
10   - */
11   -
12   -#ifndef __CONFIG_H
13   -#define __CONFIG_H
14   -
15   -#define CONFIG_CRAYL1
16   -/*
17   - * High Level Configuration Options
18   - * (easy to change)
19   - */
20   -
21   -#define CONFIG_405GP 1 /* This is a PPC405 CPU */
22   -
23   -/*
24   - * Note: I make an "image" from U-Boot itself, which prefixes 0x40
25   - * bytes of header info, hence start address is thus shifted.
26   - */
27   -#define CONFIG_SYS_TEXT_BASE 0xFFFD0040
28   -
29   -#define CONFIG_SYS_CLK_FREQ 25000000
30   -#define CONFIG_BAUDRATE 9600
31   -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
32   -
33   -#define CONFIG_PPC4xx_EMAC
34   -#define CONFIG_MII 1 /* MII PHY management */
35   -#define CONFIG_PHY_ADDR 1 /* PHY address; handling of ENET */
36   -#define CONFIG_BOARD_EARLY_INIT_F 1 /* early setup for 405gp */
37   -#define CONFIG_MISC_INIT_R 1 /* so that a misc_init_r() is called */
38   -
39   -#define CONFIG_CONS_INDEX 1 /* Use UART0 */
40   -#define CONFIG_SYS_NS16550
41   -#define CONFIG_SYS_NS16550_SERIAL
42   -#define CONFIG_SYS_NS16550_REG_SIZE 1
43   -#define CONFIG_SYS_NS16550_CLK get_serial_clock()
44   -
45   -/* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to
46   - * keep possible initrd ramdisk decompression out. This is in k (1024 bytes)
47   - #define CONFIG_PRAM 16
48   - */
49   -#define CONFIG_LOADADDR 0x100000 /* where TFTP images go */
50   -#undef CONFIG_BOOTARGS
51   -
52   -/* Bootcmd is overridden by the bootscript in board/cray/L1
53   - */
54   -#define CONFIG_SYS_AUTOLOAD "no"
55   -#define CONFIG_BOOTCOMMAND "dhcp"
56   -
57   -/*
58   - * ..during experiments..
59   - #define CONFIG_SERVERIP 10.0.0.1
60   - #define CONFIG_ETHADDR 00:40:a6:80:14:5
61   - */
62   -#define CONFIG_SYS_I2C
63   -#define CONFIG_SYS_I2C_PPC4XX
64   -#define CONFIG_SYS_I2C_PPC4XX_CH0
65   -#define CONFIG_SDRAM_BANK0 1
66   -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
67   -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
68   -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
69   -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
70   -#define CONFIG_IDENT_STRING "Cray L1"
71   -#define CONFIG_ENV_OVERWRITE 1
72   -#define CONFIG_SYS_HUSH_PARSER 1
73   -#define CONFIG_SOURCE 1
74   -
75   -
76   -/*
77   - * Command line configuration.
78   - */
79   -
80   -#define CONFIG_CMD_ASKENV
81   -#define CONFIG_CMD_BDI
82   -#define CONFIG_CMD_CONSOLE
83   -#define CONFIG_CMD_DATE
84   -#define CONFIG_CMD_DHCP
85   -#define CONFIG_CMD_DIAG
86   -#define CONFIG_CMD_ECHO
87   -#define CONFIG_CMD_EEPROM
88   -#define CONFIG_CMD_FLASH
89   -#define CONFIG_CMD_I2C
90   -#define CONFIG_CMD_IMI
91   -#define CONFIG_CMD_IMMAP
92   -#define CONFIG_CMD_MEMORY
93   -#define CONFIG_CMD_NET
94   -#define CONFIG_CMD_REGINFO
95   -#define CONFIG_CMD_RUN
96   -#define CONFIG_CMD_SAVEENV
97   -#define CONFIG_CMD_SETGETDCR
98   -#define CONFIG_CMD_SOURCE
99   -
100   -
101   -/*
102   - * BOOTP options
103   - */
104   -#define CONFIG_BOOTP_SUBNETMASK
105   -#define CONFIG_BOOTP_GATEWAY
106   -#define CONFIG_BOOTP_HOSTNAME
107   -#define CONFIG_BOOTP_BOOTPATH
108   -#define CONFIG_BOOTP_VENDOREX
109   -#define CONFIG_BOOTP_DNS
110   -#define CONFIG_BOOTP_BOOTFILESIZE
111   -
112   -
113   -/*
114   - * how many time to fail & restart a net-TFTP before giving up & resetting
115   - * the board hoping that a reset of net interface might help..
116   - */
117   -#define CONFIG_NET_RESET 5
118   -
119   -/*
120   - * bauds. Just to make it compile; in our case, I read the base_baud
121   - * from the DCR anyway, so its kinda-tied to the above ref. clock which in turn
122   - * drives the system clock.
123   - */
124   -#define CONFIG_SYS_BASE_BAUD 403225
125   -#define CONFIG_SYS_BAUDRATE_TABLE \
126   - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
127   -
128   -/*
129   - * Miscellaneous configurable options
130   - */
131   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
132   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
133   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
134   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
135   -
136   -
137   -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* where to load what we get from TFTP */
138   -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
139   -#define CONFIG_SYS_DRAM_TEST 1
140   -
141   -/*-----------------------------------------------------------------------
142   - * Start addresses for the final memory configuration
143   - * (Set up by the startup code)
144   - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
145   - */
146   -#define CONFIG_SYS_SDRAM_BASE 0x00000000
147   -#define CONFIG_SYS_FLASH_BASE 0xFFC00000
148   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
149   -
150   -
151   -#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */
152   -
153   -/*
154   - * For booting Linux, the board info and command line data
155   - * have to be in the first 8 MB of memory, since this is
156   - * the maximum mapped by the Linux kernel during initialization.
157   - */
158   -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
159   -/*-----------------------------------------------------------------------
160   - * FLASH organization
161   - */
162   -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
163   -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
164   -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
165   -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
166   -
167   -/* BEG ENVIRONNEMENT FLASH: needs to be a whole FlashSector */
168   -#define CONFIG_ENV_OFFSET 0x3c8000
169   -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
170   -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment area */
171   -#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
172   -
173   -/* Memory tests: U-BOOT relocates itself to the top of Ram, so its at
174   - * 32meg-(128k+some_malloc_space+copy-of-ENV sector)..
175   - */
176   -#define CONFIG_SYS_SDRAM_SIZE 32 /* megs of ram */
177   -#define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */
178   - /* the exception vector table */
179   - /* to the end of the DRAM */
180   - /* less monitor and malloc area */
181   -#define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
182   -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* 128k for malloc space */
183   -#define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \
184   - + CONFIG_SYS_MALLOC_LEN \
185   - + CONFIG_ENV_SECT_SIZE \
186   - + CONFIG_SYS_STACK_USAGE )
187   -
188   -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 - CONFIG_SYS_MEM_END_USAGE)
189   -/* END ENVIRONNEMENT FLASH */
190   -
191   -/*
192   - * Init Memory Controller:
193   - *
194   - * BR0/1 and OR0/1 (FLASH)
195   - */
196   -
197   -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
198   -
199   -
200   -/*-----------------------------------------------------------------------
201   - * Definitions for initial stack pointer and data area (in OnChipMem )
202   - */
203   -#if 1
204   -/* On Chip Memory location */
205   -#define CONFIG_SYS_TEMP_STACK_OCM 1
206   -#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
207   -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
208   -
209   -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
210   -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
211   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
212   -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
213   -#else
214   -#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
215   -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
216   -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
217   -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */
218   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
219   -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
220   -#endif
221   -
222   -/*-----------------------------------------------------------------------
223   - * Definitions for Serial Presence Detect EEPROM address
224   - */
225   -#define EEPROM_WRITE_ADDRESS 0xA0
226   -#define EEPROM_READ_ADDRESS 0xA1
227   -
228   -#endif /* __CONFIG_H */