Commit 1535163a4e2dbc9c4a9b5c4b05cb8987f526885f
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bdcf5a4c14
Exists in
v2017.01-smarct4x
and in
37 other branches
ARM: UniPhier: enable xHCI and GIO cores for PH1-Pro4
This is necessary to use the USB 3.0 host controllers on PH1-Pro4. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Showing 2 changed files with 25 additions and 1 deletions Side-by-side Diff
arch/arm/mach-uniphier/include/mach/sc-regs.h
| 1 | 1 | /* |
| 2 | 2 | * UniPhier SC (System Control) block registers |
| 3 | 3 | * |
| 4 | - * Copyright (C) 2011-2014 Panasonic Corporation | |
| 4 | + * Copyright (C) 2011-2015 Panasonic Corporation | |
| 5 | 5 | * |
| 6 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | 7 | */ |
| 8 | 8 | |
| 9 | 9 | |
| 10 | 10 | |
| 11 | 11 | |
| ... | ... | @@ -38,19 +38,28 @@ |
| 38 | 38 | #define SC_VPLL27BCTRL3 (SC_BASE_ADDR | 0x1298) |
| 39 | 39 | |
| 40 | 40 | #define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) |
| 41 | +#define SC_RSTCTRL_NRST_USB3B0 (0x1 << 17) /* USB3 #0 bus */ | |
| 42 | +#define SC_RSTCTRL_NRST_USB3C0 (0x1 << 16) /* USB3 #0 core */ | |
| 41 | 43 | #define SC_RSTCTRL_NRST_ETHER (0x1 << 12) |
| 42 | 44 | #define SC_RSTCTRL_NRST_STDMAC (0x1 << 10) |
| 45 | +#define SC_RSTCTRL_NRST_GIO (0x1 << 6) | |
| 43 | 46 | #define SC_RSTCTRL_NRST_UMC1 (0x1 << 5) |
| 44 | 47 | #define SC_RSTCTRL_NRST_UMC0 (0x1 << 4) |
| 45 | 48 | #define SC_RSTCTRL_NRST_NAND (0x1 << 2) |
| 46 | 49 | |
| 47 | 50 | #define SC_RSTCTRL2 (SC_BASE_ADDR | 0x2004) |
| 51 | +#define SC_RSTCTRL2_NRST_USB3B1 (0x1 << 17) /* USB3 #1 bus */ | |
| 52 | +#define SC_RSTCTRL2_NRST_USB3C1 (0x1 << 16) /* USB3 #1 core */ | |
| 53 | + | |
| 48 | 54 | #define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008) |
| 49 | 55 | |
| 50 | 56 | #define SC_CLKCTRL (SC_BASE_ADDR | 0x2104) |
| 57 | +#define SC_CLKCTRL_CEN_USB31 (0x1 << 17) /* USB3 #1 */ | |
| 58 | +#define SC_CLKCTRL_CEN_USB30 (0x1 << 16) /* USB3 #0 */ | |
| 51 | 59 | #define SC_CLKCTRL_CEN_ETHER (0x1 << 12) |
| 52 | 60 | #define SC_CLKCTRL_CEN_MIO (0x1 << 11) |
| 53 | 61 | #define SC_CLKCTRL_CEN_STDMAC (0x1 << 10) |
| 62 | +#define SC_CLKCTRL_CEN_GIO (0x1 << 6) | |
| 54 | 63 | #define SC_CLKCTRL_CEN_UMC (0x1 << 4) |
| 55 | 64 | #define SC_CLKCTRL_CEN_NAND (0x1 << 2) |
| 56 | 65 | #define SC_CLKCTRL_CEN_SBC (0x1 << 1) |
arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c
| ... | ... | @@ -14,6 +14,10 @@ |
| 14 | 14 | |
| 15 | 15 | /* deassert reset */ |
| 16 | 16 | tmp = readl(SC_RSTCTRL); |
| 17 | +#ifdef CONFIG_USB_XHCI_UNIPHIER | |
| 18 | + tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 | | |
| 19 | + SC_RSTCTRL_NRST_GIO; | |
| 20 | +#endif | |
| 17 | 21 | #ifdef CONFIG_UNIPHIER_ETH |
| 18 | 22 | tmp |= SC_RSTCTRL_NRST_ETHER; |
| 19 | 23 | #endif |
| 20 | 24 | |
| ... | ... | @@ -26,8 +30,19 @@ |
| 26 | 30 | writel(tmp, SC_RSTCTRL); |
| 27 | 31 | readl(SC_RSTCTRL); /* dummy read */ |
| 28 | 32 | |
| 33 | +#ifdef CONFIG_USB_XHCI_UNIPHIER | |
| 34 | + tmp = readl(SC_RSTCTRL2); | |
| 35 | + tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1; | |
| 36 | + writel(tmp, SC_RSTCTRL2); | |
| 37 | + readl(SC_RSTCTRL2); /* dummy read */ | |
| 38 | +#endif | |
| 39 | + | |
| 29 | 40 | /* privide clocks */ |
| 30 | 41 | tmp = readl(SC_CLKCTRL); |
| 42 | +#ifdef CONFIG_USB_XHCI_UNIPHIER | |
| 43 | + tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | | |
| 44 | + SC_CLKCTRL_CEN_GIO; | |
| 45 | +#endif | |
| 31 | 46 | #ifdef CONFIG_UNIPHIER_ETH |
| 32 | 47 | tmp |= SC_CLKCTRL_CEN_ETHER; |
| 33 | 48 | #endif |