Commit 1544698816a32284947322d0f0fe1478a9b65ad3
ARM: armv7: move ARMV7_PSCI_NR_CPUS to Kconfig
Move this option to Kconfig and set its default value to 4; this increases the number of supported CPUs for some boards. It consumes 1KB memory per CPU for PSCI stack, but it should not be a big deal, given the amount of memory used for the modern OSes. Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Showing 12 changed files with 9 additions and 22 deletions Side-by-side Diff
- arch/arm/cpu/armv7/Kconfig
- include/configs/arndale.h
- include/configs/bcm_ep_board.h
- include/configs/jetson-tk1.h
- include/configs/ls1021aqds.h
- include/configs/ls1021atwr.h
- include/configs/mx7_common.h
- include/configs/sun6i.h
- include/configs/sun7i.h
- include/configs/sun8i.h
- include/configs/uniphier.h
- include/configs/vexpress_ca15_tc2.h
... | ... | @@ -41,6 +41,15 @@ |
41 | 41 | help |
42 | 42 | Say Y here to enable PSCI support. |
43 | 43 | |
44 | +config ARMV7_PSCI_NR_CPUS | |
45 | + int "Maximum supported CPUs for PSCI" | |
46 | + depends on ARMV7_NONSEC | |
47 | + default 4 | |
48 | + help | |
49 | + The maximum number of CPUs supported in the PSCI firmware. | |
50 | + It is no problem to set a larger value than the number of | |
51 | + CPUs in the actual hardware implementation. | |
52 | + | |
44 | 53 | config ARMV7_LPAE |
45 | 54 | bool "Use LPAE page table format" if EXPERT |
46 | 55 | depends on CPU_V7 |
... | ... | @@ -45,7 +45,6 @@ |
45 | 45 | |
46 | 46 | #define CONFIG_S5P_PA_SYSRAM 0x02020000 |
47 | 47 | #define CONFIG_SMP_PEN_ADDR CONFIG_S5P_PA_SYSRAM |
48 | -#define CONFIG_ARMV7_PSCI_NR_CPUS 4 | |
49 | 48 | |
50 | 49 | /* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */ |
51 | 50 | #define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000 |
... | ... | @@ -60,7 +60,6 @@ |
60 | 60 | #include "tegra-common-usb-gadget.h" |
61 | 61 | #include "tegra-common-post.h" |
62 | 62 | |
63 | -#define CONFIG_ARMV7_PSCI_NR_CPUS 4 | |
64 | 63 | /* Reserve top 1M for secure RAM */ |
65 | 64 | #define CONFIG_ARMV7_SECURE_BASE 0xfff00000 |
66 | 65 | #define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x00100000 |
... | ... | @@ -26,18 +26,6 @@ |
26 | 26 | #define CONFIG_SUNXI_USB_PHYS 2 |
27 | 27 | #endif |
28 | 28 | |
29 | -#ifndef CONFIG_MACH_SUN8I_A83T | |
30 | -#if defined(CONFIG_MACH_SUN8I_A23) | |
31 | -#define CONFIG_ARMV7_PSCI_NR_CPUS 2 | |
32 | -#elif defined(CONFIG_MACH_SUN8I_A33) | |
33 | -#define CONFIG_ARMV7_PSCI_NR_CPUS 4 | |
34 | -#elif defined(CONFIG_MACH_SUN8I_H3) | |
35 | -#define CONFIG_ARMV7_PSCI_NR_CPUS 4 | |
36 | -#else | |
37 | -#error Unsupported sun8i variant | |
38 | -#endif | |
39 | -#endif | |
40 | - | |
41 | 29 | /* |
42 | 30 | * Include common sunxi configuration where most the settings are |
43 | 31 | */ |
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