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Commit 15cc385e681c47851f32fc25c1cd95ab8efbd50c

Authored by Dirk Eibach
Committed by Stefan Roese
1 parent 97ca7b3b8e
Exists in master and in 56 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ppc4xx: Change DDR2 CL from 4 to 5 for intip 

Some intip boards don't seem to run stable with CL4, datasheets suggest that
CL5 is the safe value.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>

Showing 1 changed file with 6 additions and 6 deletions Side-by-side Diff

include/configs/intip.h
Diff comments   View file @ 15cc385
... ... @@ -37,10 +37,10 @@
37 37 #define CONFIG_460EX 1 /* Specific PPC460EX */
38 38 #ifdef CONFIG_DEVCONCENTER
39 39 #define CONFIG_HOSTNAME devconcenter
40   -#define CONFIG_IDENT_STRING " devconcenter 0.03"
  40 +#define CONFIG_IDENT_STRING " devconcenter 0.05"
41 41 #else
42 42 #define CONFIG_HOSTNAME intip
43   -#define CONFIG_IDENT_STRING " intip 0.03"
  43 +#define CONFIG_IDENT_STRING " intip 0.05"
44 44 #endif
45 45 #define CONFIG_440 1
46 46 #define CONFIG_4xx 1 /* ... PPC4xx family */
47 47  
... ... @@ -200,13 +200,13 @@
200 200 #define CONFIG_SYS_SDRAM0_INITPLR2 0x81020000
201 201 #define CONFIG_SYS_SDRAM0_INITPLR3 0x81030000
202 202 #define CONFIG_SYS_SDRAM0_INITPLR4 0x81010002
203   -#define CONFIG_SYS_SDRAM0_INITPLR5 0xE4000542
  203 +#define CONFIG_SYS_SDRAM0_INITPLR5 0xE4000552
204 204 #define CONFIG_SYS_SDRAM0_INITPLR6 0x81900400
205 205 #define CONFIG_SYS_SDRAM0_INITPLR7 0x8A880000
206 206 #define CONFIG_SYS_SDRAM0_INITPLR8 0x8A880000
207 207 #define CONFIG_SYS_SDRAM0_INITPLR9 0x8A880000
208 208 #define CONFIG_SYS_SDRAM0_INITPLR10 0x8A880000
209   -#define CONFIG_SYS_SDRAM0_INITPLR11 0x81000442
  209 +#define CONFIG_SYS_SDRAM0_INITPLR11 0x81000452
210 210 #define CONFIG_SYS_SDRAM0_INITPLR12 0x81010382
211 211 #define CONFIG_SYS_SDRAM0_INITPLR13 0x81010002
212 212 #define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000
213 213  
... ... @@ -216,11 +216,11 @@
216 216 #define CONFIG_SYS_SDRAM0_RDCC 0x40000000
217 217 #define CONFIG_SYS_SDRAM0_DLCR 0x00000000
218 218 #define CONFIG_SYS_SDRAM0_CLKTR 0x40000000
219   -#define CONFIG_SYS_SDRAM0_WRDTR 0x84000823
  219 +#define CONFIG_SYS_SDRAM0_WRDTR 0x86000823
220 220 #define CONFIG_SYS_SDRAM0_SDTR1 0x80201000
221 221 #define CONFIG_SYS_SDRAM0_SDTR2 0x32204232
222 222 #define CONFIG_SYS_SDRAM0_SDTR3 0x090C0D15
223   -#define CONFIG_SYS_SDRAM0_MMODE 0x00000442
  223 +#define CONFIG_SYS_SDRAM0_MMODE 0x00000452
224 224 #define CONFIG_SYS_SDRAM0_MEMODE 0x00000002
225 225  
226 226 #define CONFIG_SYS_MBYTES_SDRAM 256 /* 256MB */