Eric Lee / smarc-uboot

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Commit 16505f93f2f463df51b6c60656783a61fbf78612

Authored by Eric Lee
1 parent 6aac3db276
Exists in smarc-imx_v2014.04_3.14.28_1.0.0_ga and in 1 other branch smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga

Disable HDMI at U-Boot

Showing 1 changed file with 65 additions and 139 deletions Side-by-side Diff

board/embedian/smarcfimx6/smarcfimx6.c
Diff comments   View file @ 16505f9
... ... @@ -269,6 +269,12 @@
269 269 gpio_direction_input(IMX_GPIO_NR(1, 19));
270 270 }
271 271  
  272 +iomux_v3_cfg_t const di0_pads[] = {
  273 + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */
  274 + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */
  275 + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */
  276 +};
  277 +
272 278 /* CAN0/FLEXCAN1 */
273 279 iomux_v3_cfg_t const flexcan1_pads[] = {
274 280 MX6_PAD_GPIO_7__FLEXCAN1_TX | MUX_PAD_CTRL(WEAK_PULLUP),
... ... @@ -835,38 +841,6 @@
835 841 #define LCD_VDD_EN IMX_GPIO_NR(1, 02)
836 842 };
837 843  
838   -static iomux_v3_cfg_t const rgb_pads[] = {
839   - MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
840   - MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
841   - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
842   - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
843   - MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* DISP0_DRDY */
844   - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
845   - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
846   - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
847   - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
848   - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
849   - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
850   - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
851   - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
852   - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
853   - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
854   - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
855   - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
856   - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
857   - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
858   - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
859   - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
860   - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
861   - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
862   - MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
863   - MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
864   - MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
865   - MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
866   - MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
867   - MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
868   -};
869   -
870 844 struct display_info_t {
871 845 int bus;
872 846 int addr;
873 847  
874 848  
875 849  
876 850  
877 851  
878 852  
879 853  
880 854  
881 855  
882 856  
... ... @@ -876,67 +850,51 @@
876 850 struct fb_videomode mode;
877 851 };
878 852  
879   -
880   -static int detect_hdmi(struct display_info_t const *dev)
  853 +static void disable_lvds(struct display_info_t const *dev)
881 854 {
882   - struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
883   - return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
884   -}
  855 + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
885 856  
886   -static void do_enable_hdmi(struct display_info_t const *dev)
887   -{
888   - imx_enable_hdmi_phy();
889   -}
  857 + int reg = readl(&iomux->gpr[2]);
890 858  
891   -static int detect_i2c(struct display_info_t const *dev)
892   -{
893   - return ((0 == i2c_set_bus_num(dev->bus))
894   - &&
895   - (0 == i2c_probe(dev->addr)));
896   -}
  859 + reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
  860 + IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
897 861  
898   -static void enable_lvds(struct display_info_t const *dev)
899   -{
900   - struct iomuxc *iomux = (struct iomuxc *)
901   - IOMUXC_BASE_ADDR;
902   - u32 reg = readl(&iomux->gpr[2]);
903   - reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
904 862 writel(reg, &iomux->gpr[2]);
905 863 }
906 864  
907   -static void enable_rgb(struct display_info_t const *dev)
  865 +static void do_enable_hdmi(struct display_info_t const *dev)
908 866 {
909   - imx_iomux_v3_setup_multiple_pads(
910   - rgb_pads,
911   - ARRAY_SIZE(rgb_pads));
  867 + disable_lvds(dev);
  868 + imx_enable_hdmi_phy();
912 869 }
913 870  
914 871 static struct display_info_t const displays[] = {{
915 872 .bus = -1,
916 873 .addr = 0,
917 874 .pixfmt = IPU_PIX_FMT_RGB24,
918   - .detect = detect_hdmi,
919   - .enable = do_enable_hdmi,
  875 + .detect = NULL,
  876 + /*.enable = do_enable_hdmi,*/
  877 + .enable = NULL,
920 878 .mode = {
921 879 .name = "HDMI",
922 880 .refresh = 60,
923   - .xres = 1024,
924   - .yres = 768,
925   - .pixclock = 15385,
926   - .left_margin = 220,
927   - .right_margin = 40,
928   - .upper_margin = 21,
929   - .lower_margin = 7,
930   - .hsync_len = 60,
931   - .vsync_len = 10,
932   - .sync = FB_SYNC_EXT,
  881 + .xres = 640,
  882 + .yres = 480,
  883 + .pixclock = 39721,
  884 + .left_margin = 48,
  885 + .right_margin = 16,
  886 + .upper_margin = 33,
  887 + .lower_margin = 10,
  888 + .hsync_len = 96,
  889 + .vsync_len = 2,
  890 + .sync = 0,
933 891 .vmode = FB_VMODE_NONINTERLACED
934 892 } }, {
935   - .bus = 3,
936   - .addr = 0x4,
  893 + .bus = -1,
  894 + .addr = 0,
937 895 .pixfmt = IPU_PIX_FMT_LVDS666,
938   - .detect = detect_i2c,
939   - .enable = enable_lvds,
  896 + .detect = NULL,
  897 + .enable = NULL,
940 898 .mode = {
941 899 .name = "Hannstar-XGA",
942 900 .refresh = 60,
943 901  
... ... @@ -951,47 +909,8 @@
951 909 .vsync_len = 10,
952 910 .sync = FB_SYNC_EXT,
953 911 .vmode = FB_VMODE_NONINTERLACED
954   -} }, {
955   - .bus = 3,
956   - .addr = 0x38,
957   - .pixfmt = IPU_PIX_FMT_LVDS666,
958   - .detect = detect_i2c,
959   - .enable = enable_lvds,
960   - .mode = {
961   - .name = "wsvga-lvds",
962   - .refresh = 60,
963   - .xres = 1024,
964   - .yres = 600,
965   - .pixclock = 15385,
966   - .left_margin = 220,
967   - .right_margin = 40,
968   - .upper_margin = 21,
969   - .lower_margin = 7,
970   - .hsync_len = 60,
971   - .vsync_len = 10,
972   - .sync = FB_SYNC_EXT,
973   - .vmode = FB_VMODE_NONINTERLACED
974   -} }, {
975   - .bus = 4,
976   - .addr = 0x54,
977   - .pixfmt = IPU_PIX_FMT_RGB24,
978   - .detect = detect_i2c,
979   - .enable = enable_rgb,
980   - .mode = {
981   - .name = "wvga-rgb",
982   - .refresh = 57,
983   - .xres = 800,
984   - .yres = 480,
985   - .pixclock = 37037,
986   - .left_margin = 40,
987   - .right_margin = 60,
988   - .upper_margin = 10,
989   - .lower_margin = 10,
990   - .hsync_len = 20,
991   - .vsync_len = 10,
992   - .sync = 0,
993   - .vmode = FB_VMODE_NONINTERLACED
994 912 } } };
  913 +
995 914 int board_video_skip(void)
996 915 {
997 916 int i;
... ... @@ -1000,7 +919,7 @@
1000 919 if (!panel) {
1001 920 for (i = 0; i < ARRAY_SIZE(displays); i++) {
1002 921 struct display_info_t const *dev = displays+i;
1003   - if (dev->detect(dev)) {
  922 + if (dev->detect && dev->detect(dev)) {
1004 923 panel = dev->mode.name;
1005 924 printf("auto-detected panel %s\n", panel);
1006 925 break;
1007 926  
1008 927  
1009 928  
1010 929  
... ... @@ -1021,20 +940,21 @@
1021 940 ret = ipuv3_fb_init(&displays[i].mode, 0,
1022 941 displays[i].pixfmt);
1023 942 if (!ret) {
1024   - displays[i].enable(displays+i);
  943 + if (displays[i].enable)
  944 + displays[i].enable(displays+i);
1025 945 printf("Display: %s (%ux%u)\n",
1026 946 displays[i].mode.name,
1027 947 displays[i].mode.xres,
1028 948 displays[i].mode.yres);
1029   - } else {
  949 + } else
1030 950 printf("LCD %s cannot be configured: %d\n",
1031 951 displays[i].mode.name, ret);
1032   - }
1033 952 } else {
1034 953 printf("unsupported panel %s\n", panel);
1035   - ret = -EINVAL;
  954 + return -EINVAL;
1036 955 }
1037   - return (0 != ret);
  956 +
  957 + return 0;
1038 958 }
1039 959  
1040 960 static void setup_display(void)
1041 961  
1042 962  
1043 963  
1044 964  
1045 965  
1046 966  
1047 967  
1048 968  
1049 969  
... ... @@ -1043,49 +963,55 @@
1043 963 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
1044 964 int reg;
1045 965  
  966 + /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
  967 + imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));
  968 +
1046 969 enable_ipu_clock();
1047 970 imx_setup_hdmi();
1048   - /* Turn on LDB0,IPU,IPU DI0 clocks */
1049   - reg = __raw_readl(&mxc_ccm->CCGR3);
1050   - reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
  971 +
  972 + /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
  973 + reg = readl(&mxc_ccm->CCGR3);
  974 + reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
1051 975 writel(reg, &mxc_ccm->CCGR3);
1052 976  
1053 977 /* set LDB0, LDB1 clk select to 011/011 */
1054 978 reg = readl(&mxc_ccm->cs2cdr);
1055 979 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
1056   - |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
1057   - reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
1058   - |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  980 + | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  981 + reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
  982 + | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
1059 983 writel(reg, &mxc_ccm->cs2cdr);
1060 984  
1061 985 reg = readl(&mxc_ccm->cscmr2);
1062   - reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
  986 + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
1063 987 writel(reg, &mxc_ccm->cscmr2);
1064 988  
1065 989 reg = readl(&mxc_ccm->chsccdr);
1066 990 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
1067   - <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  991 + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  992 + reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  993 + << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
1068 994 writel(reg, &mxc_ccm->chsccdr);
1069 995  
1070 996 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
1071   - |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
1072   - |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
1073   - |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
1074   - |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
1075   - |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
1076   - |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
1077   - |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
1078   - |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  997 + | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
  998 + | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  999 + | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  1000 + | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
  1001 + | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  1002 + | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
  1003 + | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
  1004 + | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
1079 1005 writel(reg, &iomux->gpr[2]);
1080 1006  
1081 1007 reg = readl(&iomux->gpr[3]);
1082   - reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
1083   - |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
  1008 + reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
  1009 + | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
1084 1010 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
1085   - <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  1011 + << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
1086 1012 writel(reg, &iomux->gpr[3]);
1087   -
1088 1013 /* backlights off until needed */
  1014 +
1089 1015 /*imx_iomux_v3_setup_multiple_pads(backlight_pads,
1090 1016 ARRAY_SIZE(backlight_pads));
1091 1017 gpio_direction_input(BACKLIGHT_EN);*/