arm, am33x: make RTC32K OSC enable configurable

As http://www.denx.de/wiki/view/U-Boot/DesignPrinciples#2_Keep_it_Fast states: "Initialize devices only when they are needed within U-Boot" enable the RTC32K OSC only, if CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is enabled. Enable this in ti_am335x_common.h, so all boards in mainline should work as before. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com>

arm, am33x: make RTC32K OSC enable configurable
As http://www.denx.de/wiki/view/U-Boot/DesignPrinciples#2_Keep_it_Fast states: "Initialize devices only when they are needed within U-Boot" enable the RTC32K OSC only, if CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is enabled. Enable this in ti_am335x_common.h, so all boards in mainline should work as before. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com>
Heiko Schocher · Tom Rini
1 parent eda0ba38a8
Showing 3 changed files with 8 additions and 0 deletions Side-by-side Diff
README
arch/arm/cpu/armv7/am33xx/board.c
include/configs/ti_am335x_common.h
@@ -4319,6 +4319,9 @@
  
 		NOTE : currently only supported on AM335x platforms.
  
+- CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC:
+		Enables the RTC32K OSC on AM33xx based plattforms
+
 Freescale QE/FMAN Firmware Support:
 -----------------------------------
  
@@ -149,6 +149,7 @@
 	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 }
  
+#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
 static void rtc32k_enable(void)
 {
 	struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
@@ -164,6 +165,7 @@
 	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
 	writel((1 << 3) | (1 << 6), &rtc->osc);
 }
+#endif
  
 static void uart_soft_reset(void)
 {
  
@@ -232,8 +234,10 @@
 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
 	prcm_init();
 	set_mux_conf_regs();
+#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
 	/* Enable RTC32K clock */
 	rtc32k_enable();
+#endif
 	sdram_init();
 #endif
 }
@@ -18,6 +18,7 @@
 #define CONFIG_SYS_CACHELINE_SIZE       64
 #define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
 #define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
+#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
  
 #include <asm/arch/omap.h>
...	...	@@ -4319,6 +4319,9 @@
4319	4319
4320	4320	NOTE : currently only supported on AM335x platforms.
4321	4321
	4322	+- CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC:
	4323	+ Enables the RTC32K OSC on AM33xx based plattforms
	4324	+
4322	4325	Freescale QE/FMAN Firmware Support:
4323	4326	-----------------------------------
4324	4327
...	...	@@ -149,6 +149,7 @@
149	149	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
150	150	}
151	151
	152	+#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
152	153	static void rtc32k_enable(void)
153	154	{
154	155	struct davinci_rtc rtc = (struct davinci_rtc )RTC_BASE;
...	...	@@ -164,6 +165,7 @@
164	165	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
165	166	writel((1 << 3) \| (1 << 6), &rtc->osc);
166	167	}
	168	+#endif
167	169
168	170	static void uart_soft_reset(void)
169	171	{
170	172
...	...	@@ -232,8 +234,10 @@
232	234	#if defined(CONFIG_SPL_BUILD) \|\| defined(CONFIG_NOR_BOOT)
233	235	prcm_init();
234	236	set_mux_conf_regs();
	237	+#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
235	238	/* Enable RTC32K clock */
236	239	rtc32k_enable();
	240	+#endif
237	241	sdram_init();
238	242	#endif
239	243	}
...	...	@@ -18,6 +18,7 @@
18	18	#define CONFIG_SYS_CACHELINE_SIZE 64
19	19	#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
20	20	#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
	21	+#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
21	22
22	23	#include <asm/arch/omap.h>
23	24