EXYNOS5: Change parent clock of FIMD to MPLL

With VPLL as source clock to FIMD, Exynos DP Initializaton was failing sometimes with unstable clock. Changing FIMD source to MPLL resolves this issue. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

EXYNOS5: Change parent clock of FIMD to MPLL
With VPLL as source clock to FIMD, Exynos DP Initializaton was failing sometimes with unstable clock. Changing FIMD source to MPLL resolves this issue. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Ajay Kumar · Minkyu Kang
1 parent 9b572852c0
Showing 1 changed file with 1 additions and 1 deletions Side-by-side Diff
arch/arm/cpu/armv7/exynos/clock.c
@@ -741,7 +741,7 @@
 	 */
 	cfg = readl(&clk->src_disp1_0);
 	cfg &= ~(0xf);
-	cfg |= 0x8;
+	cfg |= 0x6;
 	writel(cfg, &clk->src_disp1_0);
  
 	/*
...	...	@@ -741,7 +741,7 @@
741	741	*/
742	742	cfg = readl(&clk->src_disp1_0);
743	743	cfg &= ~(0xf);
744		- cfg \|= 0x8;
	744	+ cfg \|= 0x6;
745	745	writel(cfg, &clk->src_disp1_0);
746	746
747	747	/*