Eric Lee / smarc-uboot

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Commit 169eb191355ec4c5b5b7335ddaf8b73a167a698b

Authored by Adam Ford
Committed by Tom Rini
1 parent 017d9819e4
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

ARM: omap3_logic.c: Optimize DDR timings based on OMAP35 or 36/37 

The default timings are assumming an OMAP36 / AM37 / DM37, but
the OMAP35 controller is a bit slower, so DDR may operate out of
spec when under stress.  This patch checks the processor type and
sets the DDR timings according to processor type.

Fixes: 5ad4212ce0d5 ("ARM: DTS: Add Logic PD OMAP35/DM37 SOM-LV
and OMAP35 Torpedo")

Signed-off-by: Adam Ford <aford173@gmail.com>

Showing 1 changed file with 15 additions and 5 deletions Side-by-side Diff

board/logicpd/omap3som/omap3logic.c
Diff comments   View file @ 169eb19
... ... @@ -89,11 +89,21 @@
89 89 void get_board_mem_timings(struct board_sdrc_timings *timings)
90 90 {
91 91 timings->mr = MICRON_V_MR_165;
92   - /* 256MB DDR */
93   - timings->mcfg = MICRON_V_MCFG_200(256 << 20);
94   - timings->ctrla = MICRON_V_ACTIMA_200;
95   - timings->ctrlb = MICRON_V_ACTIMB_200;
96   - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
  92 +
  93 + if (get_cpu_family() == CPU_OMAP36XX) {
  94 + /* 200 MHz works for OMAP36/DM37 */
  95 + /* 256MB DDR */
  96 + timings->mcfg = MICRON_V_MCFG_200(256 << 20);
  97 + timings->ctrla = MICRON_V_ACTIMA_200;
  98 + timings->ctrlb = MICRON_V_ACTIMB_200;
  99 + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
  100 + } else {
  101 + /* 165 MHz works for OMAP35 */
  102 + timings->mcfg = MICRON_V_MCFG_165(256 << 20);
  103 + timings->ctrla = MICRON_V_ACTIMA_165;
  104 + timings->ctrlb = MICRON_V_ACTIMB_165;
  105 + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
  106 + }
97 107 }
98 108  
99 109 #define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c)