usb: ehci: exynos: set/reset hsic phys

The controller has 3 ports. The port0 is for USB 2.0 Phy, port1 and port2 are for HSIC phys. The usb 2.0 phy is already being setup. This patch sets up the hsic phys. Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>

usb: ehci: exynos: set/reset hsic phys
The controller has 3 ports. The port0 is for USB 2.0 Phy, port1 and port2 are for HSIC phys. The usb 2.0 phy is already being setup. This patch sets up the hsic phys. Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
Inderpal Singh · Marek Vasut
1 parent dcad280056
Showing 2 changed files with 53 additions and 0 deletions Side-by-side Diff
arch/arm/include/asm/arch-exynos/ehci.h
drivers/usb/host/ehci-exynos.c
@@ -29,6 +29,20 @@
 #define EHCICTRL_ENAINCR8			(1 << 27)
 #define EHCICTRL_ENAINCR16			(1 << 26)
  
+#define HSIC_CTRL_REFCLKSEL                     (0x2)
+#define HSIC_CTRL_REFCLKSEL_MASK                (0x3)
+#define HSIC_CTRL_REFCLKSEL_SHIFT               (23)
+
+#define HSIC_CTRL_REFCLKDIV_12                  (0x24)
+#define HSIC_CTRL_REFCLKDIV_MASK                (0x7f)
+#define HSIC_CTRL_REFCLKDIV_SHIFT               (16)
+
+#define HSIC_CTRL_SIDDQ                         (0x1 << 6)
+#define HSIC_CTRL_FORCESLEEP                    (0x1 << 5)
+#define HSIC_CTRL_FORCESUSPEND                  (0x1 << 4)
+#define HSIC_CTRL_UTMISWRST                     (0x1 << 2)
+#define HSIC_CTRL_PHYSWRST                      (0x1 << 0)
+
 /* Register map for PHY control */
 struct exynos_usb_phy {
 	unsigned int usbphyctrl0;
@@ -88,6 +88,8 @@
 /* Setup the EHCI host controller. */
 static void setup_usb_phy(struct exynos_usb_phy *usb)
 {
+	u32 hsic_ctrl;
+
 	set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
  
 	set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
@@ -112,6 +114,32 @@
 	clrbits_le32(&usb->usbphyctrl0,
 			HOST_CTRL0_LINKSWRST |
 			HOST_CTRL0_UTMISWRST);
+
+	/* HSIC Phy Setting */
+	hsic_ctrl = (HSIC_CTRL_FORCESUSPEND |
+			HSIC_CTRL_FORCESLEEP |
+			HSIC_CTRL_SIDDQ);
+
+	clrbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
+	clrbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
+
+	hsic_ctrl = (((HSIC_CTRL_REFCLKDIV_12 & HSIC_CTRL_REFCLKDIV_MASK)
+				<< HSIC_CTRL_REFCLKDIV_SHIFT)
+			| ((HSIC_CTRL_REFCLKSEL & HSIC_CTRL_REFCLKSEL_MASK)
+				<< HSIC_CTRL_REFCLKSEL_SHIFT)
+			| HSIC_CTRL_UTMISWRST);
+
+	setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
+	setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
+
+	udelay(10);
+
+	clrbits_le32(&usb->hsicphyctrl1, HSIC_CTRL_PHYSWRST |
+					HSIC_CTRL_UTMISWRST);
+
+	clrbits_le32(&usb->hsicphyctrl2, HSIC_CTRL_PHYSWRST |
+					HSIC_CTRL_UTMISWRST);
+
 	udelay(20);
  
 	/* EHCI Ctrl setting */
@@ -125,6 +153,8 @@
 /* Reset the EHCI host controller. */
 static void reset_usb_phy(struct exynos_usb_phy *usb)
 {
+	u32 hsic_ctrl;
+
 	/* HOST_PHY reset */
 	setbits_le32(&usb->usbphyctrl0,
 			HOST_CTRL0_PHYSWRST |
@@ -132,6 +162,15 @@
 			HOST_CTRL0_SIDDQ |
 			HOST_CTRL0_FORCESUSPEND |
 			HOST_CTRL0_FORCESLEEP);
+
+	/* HSIC Phy reset */
+	hsic_ctrl = (HSIC_CTRL_FORCESUSPEND |
+			HSIC_CTRL_FORCESLEEP |
+			HSIC_CTRL_SIDDQ |
+			HSIC_CTRL_PHYSWRST);
+
+	setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
+	setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
  
 	set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE);
 }
...	...	@@ -29,6 +29,20 @@
29	29	#define EHCICTRL_ENAINCR8 (1 << 27)
30	30	#define EHCICTRL_ENAINCR16 (1 << 26)
31	31
	32	+#define HSIC_CTRL_REFCLKSEL (0x2)
	33	+#define HSIC_CTRL_REFCLKSEL_MASK (0x3)
	34	+#define HSIC_CTRL_REFCLKSEL_SHIFT (23)
	35	+
	36	+#define HSIC_CTRL_REFCLKDIV_12 (0x24)
	37	+#define HSIC_CTRL_REFCLKDIV_MASK (0x7f)
	38	+#define HSIC_CTRL_REFCLKDIV_SHIFT (16)
	39	+
	40	+#define HSIC_CTRL_SIDDQ (0x1 << 6)
	41	+#define HSIC_CTRL_FORCESLEEP (0x1 << 5)
	42	+#define HSIC_CTRL_FORCESUSPEND (0x1 << 4)
	43	+#define HSIC_CTRL_UTMISWRST (0x1 << 2)
	44	+#define HSIC_CTRL_PHYSWRST (0x1 << 0)
	45	+
32	46	/* Register map for PHY control */
33	47	struct exynos_usb_phy {
34	48	unsigned int usbphyctrl0;
...	...	@@ -88,6 +88,8 @@
88	88	/* Setup the EHCI host controller. */
89	89	static void setup_usb_phy(struct exynos_usb_phy *usb)
90	90	{
	91	+ u32 hsic_ctrl;
	92	+
91	93	set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
92	94
93	95	set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
...	...	@@ -112,6 +114,32 @@
112	114	clrbits_le32(&usb->usbphyctrl0,
113	115	HOST_CTRL0_LINKSWRST \|
114	116	HOST_CTRL0_UTMISWRST);
	117	+
	118	+ /* HSIC Phy Setting */
	119	+ hsic_ctrl = (HSIC_CTRL_FORCESUSPEND \|
	120	+ HSIC_CTRL_FORCESLEEP \|
	121	+ HSIC_CTRL_SIDDQ);
	122	+
	123	+ clrbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
	124	+ clrbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
	125	+
	126	+ hsic_ctrl = (((HSIC_CTRL_REFCLKDIV_12 & HSIC_CTRL_REFCLKDIV_MASK)
	127	+ << HSIC_CTRL_REFCLKDIV_SHIFT)
	128	+ \| ((HSIC_CTRL_REFCLKSEL & HSIC_CTRL_REFCLKSEL_MASK)
	129	+ << HSIC_CTRL_REFCLKSEL_SHIFT)
	130	+ \| HSIC_CTRL_UTMISWRST);
	131	+
	132	+ setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
	133	+ setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
	134	+
	135	+ udelay(10);
	136	+
	137	+ clrbits_le32(&usb->hsicphyctrl1, HSIC_CTRL_PHYSWRST \|
	138	+ HSIC_CTRL_UTMISWRST);
	139	+
	140	+ clrbits_le32(&usb->hsicphyctrl2, HSIC_CTRL_PHYSWRST \|
	141	+ HSIC_CTRL_UTMISWRST);
	142	+
115	143	udelay(20);
116	144
117	145	/* EHCI Ctrl setting */
...	...	@@ -125,6 +153,8 @@
125	153	/* Reset the EHCI host controller. */
126	154	static void reset_usb_phy(struct exynos_usb_phy *usb)
127	155	{
	156	+ u32 hsic_ctrl;
	157	+
128	158	/* HOST_PHY reset */
129	159	setbits_le32(&usb->usbphyctrl0,
130	160	HOST_CTRL0_PHYSWRST \|
...	...	@@ -132,6 +162,15 @@
132	162	HOST_CTRL0_SIDDQ \|
133	163	HOST_CTRL0_FORCESUSPEND \|
134	164	HOST_CTRL0_FORCESLEEP);
	165	+
	166	+ /* HSIC Phy reset */
	167	+ hsic_ctrl = (HSIC_CTRL_FORCESUSPEND \|
	168	+ HSIC_CTRL_FORCESLEEP \|
	169	+ HSIC_CTRL_SIDDQ \|
	170	+ HSIC_CTRL_PHYSWRST);
	171	+
	172	+ setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
	173	+ setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
135	174
136	175	set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE);
137	176	}