Eric Lee / smarc-uboot

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Commit 17bef68097ab3692500a36fb31115bff7910aa99

Authored by Niklaus Giger
Committed by Stefan Roese
1 parent 5dd372a23d
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ppc_4xx: Fix post spr.c for PPC405 

post/cpu/ppc4xx/spr.c contained a few checks for registers only present
for PPC440 and derivates processor.

Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>

Showing 1 changed file with 6 additions and 0 deletions Side-by-side Diff

post/cpu/ppc4xx/spr.c
Diff comments   View file @ 17bef68
... ... @@ -80,7 +80,9 @@
80 80 {0x107, "SPRG7", 0x00000000, 0x00000000},
81 81 {0x10c, "TBL", 0x00000000, 0x00000000},
82 82 {0x10d, "TBU", 0x00000000, 0x00000000},
  83 +#ifdef CONFIG_440
83 84 {0x11e, "PIR", 0x0000000f, 0x00000000},
  85 +#endif
84 86 {0x130, "DBSR", 0x00000000, 0x00000000},
85 87 {0x134, "DBCR0", 0x00000000, 0x00000000},
86 88 {0x135, "DBCR1", 0x00000000, 0x00000000},
... ... @@ -95,6 +97,7 @@
95 97 {0x13f, "DVC2", 0x00000000, 0x00000000},
96 98 {0x150, "TSR", 0x00000000, 0x00000000},
97 99 {0x154, "TCR", 0x00000000, 0x00000000},
  100 +#ifdef CONFIG_440
98 101 {0x190, "IVOR0", 0x0000fff0, 0x00000100},
99 102 {0x191, "IVOR1", 0x0000fff0, 0x00000200},
100 103 {0x192, "IVOR2", 0x0000fff0, 0x00000300},
... ... @@ -111,6 +114,7 @@
111 114 {0x19d, "IVOR13", 0x0000fff0, 0x00001300},
112 115 {0x19e, "IVOR14", 0x0000fff0, 0x00001400},
113 116 {0x19f, "IVOR15", 0x0000fff0, 0x00002000},
  117 +#endif
114 118 {0x23a, "MCSRR0", 0x00000000, 0x00000000},
115 119 {0x23b, "MCSRR1", 0x00000000, 0x00000000},
116 120 {0x23c, "MCSR", 0x00000000, 0x00000000},
117 121  
... ... @@ -131,8 +135,10 @@
131 135 {0x395, "DTV1", 0x00000000, 0x00000000},
132 136 {0x396, "DTV2", 0x00000000, 0x00000000},
133 137 {0x397, "DTV3", 0x00000000, 0x00000000},
  138 +#ifdef CONFIG_440
134 139 {0x398, "DVLIM", 0x0fc1f83f, 0x0001f800},
135 140 {0x399, "IVLIM", 0x0fc1f83f, 0x0001f800},
  141 +#endif
136 142 {0x39b, "RSTCFG", 0x00000000, 0x00000000},
137 143 {0x39c, "DCDBTRL", 0x00000000, 0x00000000},
138 144 {0x39d, "DCDBTRH", 0x00000000, 0x00000000},