Eric Lee / smarc-uboot

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Commit 17f50f22bc3f2d17258523f2ef3074e6ce1f7ffa

Authored by Stefan Roese
1 parent 3e0bc4473a
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Add support for AMCC Bamboo PPC440EP eval board 

Patch by Stefan Roese, 04 Aug 2005

Showing 17 changed files with 3005 additions and 322 deletions Side-by-side Diff

... ... @@ -2,11 +2,14 @@
2 2 Changes for U-Boot 1.1.3:
3 3 ======================================================================
4 4  
  5 +* Add support for AMCC Bamboo PPC440EP eval board
  6 + Patch by Stefan Roese, 04 Aug 2005
  7 +
5 8 * Fix typos in cpu/85xx/start.S which caused DataTLB exception to be
6 9 routed to the Watchdog handler
7 10 Patch by Eugene Surovegin, 18 Jun 2005
8 11  
9   -* (re)enabled scsi commands do_scsi() and do_scsiboot()
  12 +* (re)enabled scsi commands do_scsi() and do_scsiboot()
10 13 Patch by Denis Peter, 06 Dec 2004
11 14  
12 15 * Fix endianess problem in TFTP / NFS default filenames
board/amcc/bamboo/Makefile
Diff comments   View file @ 17f50f2
... ... @@ -26,7 +26,7 @@
26 26 LIB = lib$(BOARD).a
27 27  
28 28 OBJS = $(BOARD).o
29   -#OBJS += flash.o
  29 +OBJS += flash.o
30 30 SOBJS = init.o
31 31  
32 32 $(LIB): $(OBJS) $(SOBJS)
board/amcc/bamboo/bamboo.c
Diff comments   View file @ 17f50f2
Changes suppressed. Click to show
... ... @@ -24,41 +24,194 @@
24 24 #include <common.h>
25 25 #include <asm/processor.h>
26 26 #include <spd_sdram.h>
  27 +#include <ppc440.h>
  28 +#include "bamboo.h"
27 29  
28   -int board_early_init_f(void)
29   -{
30   - register uint reg;
  30 +void ext_bus_cntlr_init(void);
  31 +void configure_ppc440ep_pins(void);
31 32  
32   - /*--------------------------------------------------------------------
33   - * Setup the external bus controller/chip selects
34   - *-------------------------------------------------------------------*/
35   - mtdcr(ebccfga, xbcfg);
36   - reg = mfdcr(ebccfgd);
37   - mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
  33 +gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
  34 +#if 0
  35 +{ /* GPIO Alternate1 Alternate2 Alternate3 */
  36 + {
  37 + /* GPIO Core 0 */
  38 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */
  39 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */
  40 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */
  41 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */
  42 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */
  43 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
  44 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */
  45 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */
  46 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */
  47 + { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */
  48 + { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
  49 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
  50 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
  51 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
  52 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
  53 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
  54 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
  55 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
  56 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
  57 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
  58 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
  59 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
  60 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
  61 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
  62 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
  63 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
  64 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */
  65 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */
  66 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */
  67 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */
  68 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */
  69 + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */
  70 + },
  71 + {
  72 + /* GPIO Core 1 */
  73 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */
  74 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */
  75 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */
  76 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */
  77 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */
  78 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */
  79 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */
  80 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */
  81 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */
  82 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */
  83 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
  84 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
  85 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */
  86 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */
  87 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */
  88 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */
  89 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */
  90 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
  91 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */
  92 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */
  93 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */
  94 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */
  95 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */
  96 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */
  97 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */
  98 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */
  99 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */
  100 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */
  101 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */
  102 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */
  103 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */
  104 + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
  105 + }
  106 +};
  107 +#endif
38 108  
39   -#if 0 /* test-only */
40   - mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
41   - mtebc(pb0cr, 0xfe0ba000); /* BAS=0xfe0 32MB r/w 16-bit */
  109 +/*----------------------------------------------------------------------------+
  110 + | EBC Devices Characteristics
  111 + | Peripheral Bank Access Parameters - EBC0_BnAP
  112 + | Peripheral Bank Configuration Register - EBC0_BnCR
  113 + +----------------------------------------------------------------------------*/
  114 +/* Small Flash */
  115 +#define EBC0_BNAP_SMALL_FLASH EBC0_BNAP_BME_DISABLED | \
  116 + EBC0_BNAP_TWT_ENCODE(6) | \
  117 + EBC0_BNAP_CSN_ENCODE(0) | \
  118 + EBC0_BNAP_OEN_ENCODE(1) | \
  119 + EBC0_BNAP_WBN_ENCODE(1) | \
  120 + EBC0_BNAP_WBF_ENCODE(3) | \
  121 + EBC0_BNAP_TH_ENCODE(1) | \
  122 + EBC0_BNAP_RE_ENABLED | \
  123 + EBC0_BNAP_SOR_DELAYED | \
  124 + EBC0_BNAP_BEM_WRITEONLY | \
  125 + EBC0_BNAP_PEN_DISABLED
42 126  
43   - mtebc(pb1ap, 0x00000000);
44   - mtebc(pb1cr, 0x00000000);
  127 +#define EBC0_BNCR_SMALL_FLASH_CS0 EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \
  128 + EBC0_BNCR_BS_1MB | \
  129 + EBC0_BNCR_BU_RW | \
  130 + EBC0_BNCR_BW_8BIT
45 131  
46   - mtebc(pb2ap, 0x04814500);
47   - /*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */
48   -#else
49   - mtebc(pb0ap, 0x04055200); /* FLASH/SRAM */
50   - mtebc(pb0cr, 0xfff18000); /* BAS=0xfe0 1MB r/w 8-bit */
51   -#endif
  132 +#define EBC0_BNCR_SMALL_FLASH_CS4 EBC0_BNCR_BAS_ENCODE(0x87800000) | \
  133 + EBC0_BNCR_BS_8MB | \
  134 + EBC0_BNCR_BU_RW | \
  135 + EBC0_BNCR_BW_16BIT
52 136  
53   - mtebc(pb3ap, 0x00000000);
54   - mtebc(pb3cr, 0x00000000);
  137 +/* Large Flash or SRAM */
  138 +#define EBC0_BNAP_LARGE_FLASH_OR_SRAM EBC0_BNAP_BME_DISABLED | \
  139 + EBC0_BNAP_TWT_ENCODE(8) | \
  140 + EBC0_BNAP_CSN_ENCODE(0) | \
  141 + EBC0_BNAP_OEN_ENCODE(1) | \
  142 + EBC0_BNAP_WBN_ENCODE(1) | \
  143 + EBC0_BNAP_WBF_ENCODE(1) | \
  144 + EBC0_BNAP_TH_ENCODE(2) | \
  145 + EBC0_BNAP_SOR_DELAYED | \
  146 + EBC0_BNAP_BEM_RW | \
  147 + EBC0_BNAP_PEN_DISABLED
55 148  
56   - mtebc(pb4ap, 0x00000000);
57   - mtebc(pb4cr, 0x00000000);
  149 +#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 EBC0_BNCR_BAS_ENCODE(0xFF800000) | \
  150 + EBC0_BNCR_BS_8MB | \
  151 + EBC0_BNCR_BU_RW | \
  152 + EBC0_BNCR_BW_16BIT
58 153  
59   - mtebc(pb5ap, 0x00000000);
60   - mtebc(pb5cr, 0x00000000);
61 154  
  155 +#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 EBC0_BNCR_BAS_ENCODE(0x87800000) | \
  156 + EBC0_BNCR_BS_8MB | \
  157 + EBC0_BNCR_BU_RW | \
  158 + EBC0_BNCR_BW_16BIT
  159 +
  160 +/* NVRAM - FPGA */
  161 +#define EBC0_BNAP_NVRAM_FPGA EBC0_BNAP_BME_DISABLED | \
  162 + EBC0_BNAP_TWT_ENCODE(9) | \
  163 + EBC0_BNAP_CSN_ENCODE(0) | \
  164 + EBC0_BNAP_OEN_ENCODE(1) | \
  165 + EBC0_BNAP_WBN_ENCODE(1) | \
  166 + EBC0_BNAP_WBF_ENCODE(0) | \
  167 + EBC0_BNAP_TH_ENCODE(2) | \
  168 + EBC0_BNAP_RE_ENABLED | \
  169 + EBC0_BNAP_SOR_DELAYED | \
  170 + EBC0_BNAP_BEM_WRITEONLY | \
  171 + EBC0_BNAP_PEN_DISABLED
  172 +
  173 +#define EBC0_BNCR_NVRAM_FPGA_CS5 EBC0_BNCR_BAS_ENCODE(0x80000000) | \
  174 + EBC0_BNCR_BS_1MB | \
  175 + EBC0_BNCR_BU_RW | \
  176 + EBC0_BNCR_BW_8BIT
  177 +
  178 +/* Nand Flash */
  179 +#define EBC0_BNAP_NAND_FLASH EBC0_BNAP_BME_DISABLED | \
  180 + EBC0_BNAP_TWT_ENCODE(3) | \
  181 + EBC0_BNAP_CSN_ENCODE(0) | \
  182 + EBC0_BNAP_OEN_ENCODE(0) | \
  183 + EBC0_BNAP_WBN_ENCODE(0) | \
  184 + EBC0_BNAP_WBF_ENCODE(0) | \
  185 + EBC0_BNAP_TH_ENCODE(1) | \
  186 + EBC0_BNAP_RE_ENABLED | \
  187 + EBC0_BNAP_SOR_NOT_DELAYED | \
  188 + EBC0_BNAP_BEM_RW | \
  189 + EBC0_BNAP_PEN_DISABLED
  190 +
  191 +
  192 +#define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000
  193 +
  194 +/* NAND0 */
  195 +#define EBC0_BNCR_NAND_FLASH_CS1 EBC0_BNCR_BAS_ENCODE(0x90000000) | \
  196 + EBC0_BNCR_BS_1MB | \
  197 + EBC0_BNCR_BU_RW | \
  198 + EBC0_BNCR_BW_32BIT
  199 +/* NAND1 - Bank2 */
  200 +#define EBC0_BNCR_NAND_FLASH_CS2 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
  201 + EBC0_BNCR_BS_1MB | \
  202 + EBC0_BNCR_BU_RW | \
  203 + EBC0_BNCR_BW_32BIT
  204 +
  205 +/* NAND1 - Bank3 */
  206 +#define EBC0_BNCR_NAND_FLASH_CS3 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
  207 + EBC0_BNCR_BS_1MB | \
  208 + EBC0_BNCR_BU_RW | \
  209 + EBC0_BNCR_BW_32BIT
  210 +
  211 +int board_early_init_f(void)
  212 +{
  213 + ext_bus_cntlr_init();
  214 +
62 215 /*--------------------------------------------------------------------
63 216 * Setup the interrupt controller polarities, triggers, etc.
64 217 *-------------------------------------------------------------------*/
65 218  
66 219  
67 220  
... ... @@ -81,53 +234,30 @@
81 234 /*--------------------------------------------------------------------
82 235 * Setup the GPIO pins
83 236 *-------------------------------------------------------------------*/
84   - /*CPLD cs */
85   - /*setup Address lines for flash sizes larger than 16Meg. */
86   - out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
87   - out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
88   - out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);
  237 + out32(GPIO0_OSRL, 0x00000400);
  238 + out32(GPIO0_OSRH, 0x00000000);
  239 + out32(GPIO0_TSRL, 0x00000400);
  240 + out32(GPIO0_TSRH, 0x00000000);
  241 + out32(GPIO0_ISR1L, 0x00000000);
  242 + out32(GPIO0_ISR1H, 0x00000000);
  243 + out32(GPIO0_ISR2L, 0x00000000);
  244 + out32(GPIO0_ISR2H, 0x00000000);
  245 + out32(GPIO0_ISR3L, 0x00000000);
  246 + out32(GPIO0_ISR3H, 0x00000000);
89 247  
90   - /*setup emac */
91   - out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
92   - out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
93   - out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
94   - out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
95   - out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
  248 + out32(GPIO1_OSRL, 0x0C380000);
  249 + out32(GPIO1_OSRH, 0x00000000);
  250 + out32(GPIO1_TSRL, 0x0C380000);
  251 + out32(GPIO1_TSRH, 0x00000000);
  252 + out32(GPIO1_ISR1L, 0x0FC30000);
  253 + out32(GPIO1_ISR1H, 0x00000000);
  254 + out32(GPIO1_ISR2L, 0x0C010000);
  255 + out32(GPIO1_ISR2H, 0x00000000);
  256 + out32(GPIO1_ISR3L, 0x01400000);
  257 + out32(GPIO1_ISR3H, 0x00000000);
96 258  
97   - /*UART1 */
98   - out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
99   - out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
100   - out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
  259 + configure_ppc440ep_pins();
101 260  
102   - /*setup USB 2.0 */
103   - out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
104   - out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
105   - out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
106   - out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
107   - out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
108   -
109   - /*--------------------------------------------------------------------
110   - * Setup other serial configuration
111   - *-------------------------------------------------------------------*/
112   - mfsdr(sdr_pci0, reg);
113   - mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
114   - mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
115   - mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
116   -
117   -#if 0 /* test-only */
118   - /*clear tmrclk divisor */
119   - *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
120   -
121   - /*enable ethernet */
122   - *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
123   -
124   - /*enable usb 1.1 fs device and remove usb 2.0 reset */
125   - *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
126   -
127   - /*get rid of flash write protect */
128   - *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;
129   -#endif
130   -
131 261 return 0;
132 262 }
133 263  
134 264  
135 265  
136 266  
137 267  
... ... @@ -150,31 +280,35 @@
150 280 printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
151 281 printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
152 282 printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
  283 +
153 284 return (0);
154 285 }
155 286  
156 287 /*************************************************************************
157   - * sdram_init -- doesn't use serial presence detect.
158 288 *
159   - * Assumes: 256 MB, ECC, non-registered
  289 + * fixed_sdram_init -- Bamboo has one bank onboard sdram (plus DIMM)
  290 + *
  291 + * Fixed memory is composed of :
  292 + * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
  293 + * 13 row add bits, 10 column add bits (but 12 row used only).
  294 + * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
  295 + * 12 row add bits, 10 column add bits.
  296 + * Prepare a subset (only the used ones) of SPD data
  297 + *
  298 + * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
  299 + * the corresponding bank is divided by 2 due to number of Row addresses
  300 + * 12 in the ECC module
  301 + *
  302 + * Assumes: 64 MB, ECC, non-registered
160 303 * PLB @ 133 MHz
161 304 *
162 305 ************************************************************************/
163   -void sdram_init(void)
  306 +void fixed_sdram_init(void)
164 307 {
165   - register uint reg;
166   -
167   - /*--------------------------------------------------------------------
168   - * Setup some default
169   - *------------------------------------------------------------------*/
170   - mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
171   - mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
172   - mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
173   - mtsdram(mem_clktr, 0x40000000); /* ?? */
174   - mtsdram(mem_wddctr, 0x40000000); /* ?? */
175   -
176   - /*clear this first, if the DDR is enabled by a debugger
177   - then you can not make changes. */
  308 + /*
  309 + * clear this first, if the DDR is enabled by a debugger
  310 + * then you can not make changes.
  311 + */
178 312 mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
179 313  
180 314 /*--------------------------------------------------------------------
181 315  
182 316  
183 317  
184 318  
... ... @@ -183,38 +317,25 @@
183 317 /*
184 318 * Following for CAS Latency = 2.5 @ 133 MHz PLB
185 319 */
186   - mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
187   - mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
  320 + mtsdram(mem_b0cr, 0x00082001);
  321 + mtsdram(mem_b1cr, 0x00000000);
  322 + mtsdram(mem_b2cr, 0x00000000);
  323 + mtsdram(mem_b3cr, 0x00000000);
  324 +}
188 325  
189   - mtsdram(mem_tr0, 0x410a4012); /* ?? */
190   - mtsdram(mem_tr1, 0x8080080b); /* ?? */
191   - mtsdram(mem_rtr, 0x04080000); /* ?? */
192   - mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
193   - mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
194   - udelay(400); /* Delay 200 usecs (min) */
  326 +long int initdram (int board_type)
  327 +{
  328 + long dram_size = 0;
195 329  
196   - /*--------------------------------------------------------------------
197   - * Enable the controller, then wait for DCEN to complete
198   - *------------------------------------------------------------------*/
199   - mtsdram(mem_cfg0, 0x84000000); /* Enable */
  330 + /*
  331 + * First init bank0 (onboard sdram) and then configure the DIMM-slots
  332 + */
  333 + fixed_sdram_init();
  334 + dram_size = spd_sdram (0);
200 335  
201   - for (;;) {
202   - mfsdram(mem_mcsts, reg);
203   - if (reg & 0x80000000)
204   - break;
205   - }
  336 + return dram_size;
206 337 }
207 338  
208   -/*************************************************************************
209   - * long int initdram
210   - *
211   - ************************************************************************/
212   -long int initdram(int board)
213   -{
214   - sdram_init();
215   - return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */
216   -}
217   -
218 339 #if defined(CFG_DRAM_TEST)
219 340 int testdram(void)
220 341 {
221 342  
222 343  
223 344  
224 345  
... ... @@ -425,16 +546,1451 @@
425 546 }
426 547 #endif /* defined(CONFIG_PCI) */
427 548  
428   -/*************************************************************************
429   - * hw_watchdog_reset
430   - *
431   - * This routine is called to reset (keep alive) the watchdog timer
432   - *
433   - ************************************************************************/
434   -#if defined(CONFIG_HW_WATCHDOG)
435   -void hw_watchdog_reset(void)
  549 +/*----------------------------------------------------------------------------+
  550 + | is_powerpc440ep_pass1.
  551 + +----------------------------------------------------------------------------*/
  552 +int is_powerpc440ep_pass1(void)
436 553 {
  554 + unsigned long pvr;
437 555  
  556 + pvr = get_pvr();
  557 +
  558 + if (pvr == PVR_POWERPC_440EP_PASS1)
  559 + return TRUE;
  560 + else if (pvr == PVR_POWERPC_440EP_PASS2)
  561 + return FALSE;
  562 + else {
  563 + printf("brdutil error 3\n");
  564 + for (;;)
  565 + ;
  566 + }
  567 +
  568 + return(FALSE);
438 569 }
  570 +
  571 +/*----------------------------------------------------------------------------+
  572 + | is_nand_selected.
  573 + +----------------------------------------------------------------------------*/
  574 +int is_nand_selected(void)
  575 +{
  576 + return FALSE; /* test-only */
  577 +}
  578 +
  579 +/*----------------------------------------------------------------------------+
  580 + | config_on_ebc_cs4_is_small_flash => from EPLD
  581 + +----------------------------------------------------------------------------*/
  582 +unsigned char config_on_ebc_cs4_is_small_flash(void)
  583 +{
  584 + /* Not implemented yet => returns constant value */
  585 + return TRUE;
  586 +}
  587 +
  588 +/*----------------------------------------------------------------------------+
  589 + | Ext_bus_cntlr_init.
  590 + | Initialize the external bus controller
  591 + +----------------------------------------------------------------------------*/
  592 +void ext_bus_cntlr_init(void)
  593 +{
  594 + unsigned long sdr0_pstrp0, sdr0_sdstp1;
  595 + unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
  596 + int computed_boot_device = BOOT_DEVICE_UNKNOWN;
  597 + unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
  598 + unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
  599 + unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
  600 + unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
  601 + unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
  602 +
  603 +
  604 + /*-------------------------------------------------------------------------+
  605 + |
  606 + | PART 1 : Initialize EBC Bank 5
  607 + | ==============================
  608 + | Bank5 is always associated to the NVRAM/EPLD.
  609 + | It has to be initialized prior to other banks settings computation since
  610 + | some board registers values may be needed
  611 + |
  612 + +-------------------------------------------------------------------------*/
  613 + /* NVRAM - FPGA */
  614 + mtebc(pb5ap, EBC0_BNAP_NVRAM_FPGA);
  615 + mtebc(pb5cr, EBC0_BNCR_NVRAM_FPGA_CS5);
  616 +
  617 + /*-------------------------------------------------------------------------+
  618 + |
  619 + | PART 2 : Determine which boot device was selected
  620 + | =========================================
  621 + |
  622 + | Read Pin Strap Register in PPC440EP
  623 + | In case of boot from IIC, read Serial Device Strap Register1
  624 + |
  625 + | Result can either be :
  626 + | - Boot from EBC 8bits => SMALL FLASH
  627 + | - Boot from EBC 16bits => Large Flash or SRAM
  628 + | - Boot from NAND Flash
  629 + | - Boot from PCI
  630 + |
  631 + +-------------------------------------------------------------------------*/
  632 + /* Read Pin Strap Register in PPC440EP */
  633 + mfsdr(sdr_pstrp0, sdr0_pstrp0);
  634 + bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
  635 +
  636 + /*-------------------------------------------------------------------------+
  637 + | PPC440EP Pass1
  638 + +-------------------------------------------------------------------------*/
  639 + if (is_powerpc440ep_pass1() == TRUE) {
  640 + switch(bootstrap_settings) {
  641 + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
  642 + /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
  643 + /* Boot from Small Flash */
  644 + computed_boot_device = BOOT_FROM_SMALL_FLASH;
  645 + break;
  646 + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
  647 + /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
  648 + /* Boot from PCI */
  649 + computed_boot_device = BOOT_FROM_PCI;
  650 + break;
  651 +
  652 + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
  653 + /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
  654 + /* Boot from Nand Flash */
  655 + computed_boot_device = BOOT_FROM_NAND_FLASH0;
  656 + break;
  657 +
  658 + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
  659 + /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
  660 + /* Boot from Small Flash */
  661 + computed_boot_device = BOOT_FROM_SMALL_FLASH;
  662 + break;
  663 +
  664 + case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
  665 + case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
  666 + /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
  667 + /* Read Serial Device Strap Register1 in PPC440EP */
  668 + mfsdr(sdr_sdstp1, sdr0_sdstp1);
  669 + boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
  670 + ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
  671 +
  672 + switch(boot_selection) {
  673 + case SDR0_SDSTP1_BOOT_SEL_EBC:
  674 + switch(ebc_boot_size) {
  675 + case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
  676 + computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
  677 + break;
  678 + case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
  679 + computed_boot_device = BOOT_FROM_SMALL_FLASH;
  680 + break;
  681 + }
  682 + break;
  683 +
  684 + case SDR0_SDSTP1_BOOT_SEL_PCI:
  685 + computed_boot_device = BOOT_FROM_PCI;
  686 + break;
  687 +
  688 + case SDR0_SDSTP1_BOOT_SEL_NDFC:
  689 + computed_boot_device = BOOT_FROM_NAND_FLASH0;
  690 + break;
  691 + }
  692 + break;
  693 + }
  694 + }
  695 +
  696 + /*-------------------------------------------------------------------------+
  697 + | PPC440EP Pass2
  698 + +-------------------------------------------------------------------------*/
  699 + else {
  700 + switch(bootstrap_settings) {
  701 + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
  702 + /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
  703 + /* Boot from Small Flash */
  704 + computed_boot_device = BOOT_FROM_SMALL_FLASH;
  705 + break;
  706 + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
  707 + /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
  708 + /* Boot from PCI */
  709 + computed_boot_device = BOOT_FROM_PCI;
  710 + break;
  711 +
  712 + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
  713 + /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
  714 + /* Boot from Nand Flash */
  715 + computed_boot_device = BOOT_FROM_NAND_FLASH0;
  716 + break;
  717 +
  718 + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
  719 + /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
  720 + /* Boot from Large Flash or SRAM */
  721 + computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
  722 + break;
  723 +
  724 + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
  725 + /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
  726 + /* Boot from Large Flash or SRAM */
  727 + computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
  728 + break;
  729 +
  730 + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
  731 + /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
  732 + /* Boot from PCI */
  733 + computed_boot_device = BOOT_FROM_PCI;
  734 + break;
  735 +
  736 + case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
  737 + case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
  738 + /* Default Strap Settings 5-7 */
  739 + /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
  740 + /* Read Serial Device Strap Register1 in PPC440EP */
  741 + mfsdr(sdr_sdstp1, sdr0_sdstp1);
  742 + boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
  743 + ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
  744 +
  745 + switch(boot_selection) {
  746 + case SDR0_SDSTP1_BOOT_SEL_EBC:
  747 + switch(ebc_boot_size) {
  748 + case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
  749 + computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
  750 + break;
  751 + case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
  752 + computed_boot_device = BOOT_FROM_SMALL_FLASH;
  753 + break;
  754 + }
  755 + break;
  756 +
  757 + case SDR0_SDSTP1_BOOT_SEL_PCI:
  758 + computed_boot_device = BOOT_FROM_PCI;
  759 + break;
  760 +
  761 + case SDR0_SDSTP1_BOOT_SEL_NDFC:
  762 + computed_boot_device = BOOT_FROM_NAND_FLASH0;
  763 + break;
  764 + }
  765 + break;
  766 + }
  767 + }
  768 +
  769 + /*-------------------------------------------------------------------------+
  770 + |
  771 + | PART 3 : Compute EBC settings depending on selected boot device
  772 + | ====== ======================================================
  773 + |
  774 + | Resulting EBC init will be among following configurations :
  775 + |
  776 + | - Boot from EBC 8bits => boot from SMALL FLASH selected
  777 + | EBC-CS0 = Small Flash
  778 + | EBC-CS1,2,3 = NAND Flash or
  779 + | Exp.Slot depending on Soft Config
  780 + | EBC-CS4 = SRAM/Large Flash or
  781 + | Large Flash/SRAM depending on jumpers
  782 + | EBC-CS5 = NVRAM / EPLD
  783 + |
  784 + | - Boot from EBC 16bits => boot from Large Flash or SRAM selected
  785 + | EBC-CS0 = SRAM/Large Flash or
  786 + | Large Flash/SRAM depending on jumpers
  787 + | EBC-CS1,2,3 = NAND Flash or
  788 + | Exp.Slot depending on Software Configuration
  789 + | EBC-CS4 = Small Flash
  790 + | EBC-CS5 = NVRAM / EPLD
  791 + |
  792 + | - Boot from NAND Flash
  793 + | EBC-CS0 = NAND Flash0
  794 + | EBC-CS1,2,3 = NAND Flash1
  795 + | EBC-CS4 = SRAM/Large Flash or
  796 + | Large Flash/SRAM depending on jumpers
  797 + | EBC-CS5 = NVRAM / EPLD
  798 + |
  799 + | - Boot from PCI
  800 + | EBC-CS0 = ...
  801 + | EBC-CS1,2,3 = NAND Flash or
  802 + | Exp.Slot depending on Software Configuration
  803 + | EBC-CS4 = SRAM/Large Flash or
  804 + | Large Flash/SRAM or
  805 + | Small Flash depending on jumpers
  806 + | EBC-CS5 = NVRAM / EPLD
  807 + |
  808 + +-------------------------------------------------------------------------*/
  809 +
  810 + switch(computed_boot_device) {
  811 + /*------------------------------------------------------------------------- */
  812 + case BOOT_FROM_SMALL_FLASH:
  813 + /*------------------------------------------------------------------------- */
  814 + ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
  815 + ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
  816 + if ((is_nand_selected()) == TRUE) {
  817 + /* NAND Flash */
  818 + ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
  819 + ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
  820 + /*ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
  821 + ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
  822 + ebc0_cs3_bnap_value = EBC0_BNAP_NAND_FLASH;
  823 + ebc0_cs3_bncr_value = EBC0_BNCR_NAND_FLASH_CS3;*/
  824 + ebc0_cs2_bnap_value = 0;
  825 + ebc0_cs2_bncr_value = 0;
  826 + ebc0_cs3_bnap_value = 0;
  827 + ebc0_cs3_bncr_value = 0;
  828 + } else {
  829 + /* Expansion Slot */
  830 + ebc0_cs1_bnap_value = 0;
  831 + ebc0_cs1_bncr_value = 0;
  832 + ebc0_cs2_bnap_value = 0;
  833 + ebc0_cs2_bncr_value = 0;
  834 + ebc0_cs3_bnap_value = 0;
  835 + ebc0_cs3_bncr_value = 0;
  836 + }
  837 + ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
  838 + ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
  839 +
  840 + break;
  841 +
  842 + /*------------------------------------------------------------------------- */
  843 + case BOOT_FROM_LARGE_FLASH_OR_SRAM:
  844 + /*------------------------------------------------------------------------- */
  845 + ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
  846 + ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
  847 + if ((is_nand_selected()) == TRUE) {
  848 + /* NAND Flash */
  849 + ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
  850 + ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
  851 + ebc0_cs2_bnap_value = 0;
  852 + ebc0_cs2_bncr_value = 0;
  853 + ebc0_cs3_bnap_value = 0;
  854 + ebc0_cs3_bncr_value = 0;
  855 + } else {
  856 + /* Expansion Slot */
  857 + ebc0_cs1_bnap_value = 0;
  858 + ebc0_cs1_bncr_value = 0;
  859 + ebc0_cs2_bnap_value = 0;
  860 + ebc0_cs2_bncr_value = 0;
  861 + ebc0_cs3_bnap_value = 0;
  862 + ebc0_cs3_bncr_value = 0;
  863 + }
  864 + ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
  865 + ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
  866 +
  867 + break;
  868 +
  869 + /*------------------------------------------------------------------------- */
  870 + case BOOT_FROM_NAND_FLASH0:
  871 + /*------------------------------------------------------------------------- */
  872 + ebc0_cs0_bnap_value = 0;
  873 + ebc0_cs0_bncr_value = 0;
  874 +
  875 + ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
  876 + ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
  877 + ebc0_cs2_bnap_value = 0;
  878 + ebc0_cs2_bncr_value = 0;
  879 + ebc0_cs3_bnap_value = 0;
  880 + ebc0_cs3_bncr_value = 0;
  881 +
  882 + /* Large Flash or SRAM */
  883 + ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
  884 + ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
  885 +
  886 + break;
  887 +
  888 + /*------------------------------------------------------------------------- */
  889 + case BOOT_FROM_PCI:
  890 + /*------------------------------------------------------------------------- */
  891 + ebc0_cs0_bnap_value = 0;
  892 + ebc0_cs0_bncr_value = 0;
  893 +
  894 + if ((is_nand_selected()) == TRUE) {
  895 + /* NAND Flash */
  896 + ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
  897 + ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
  898 + ebc0_cs2_bnap_value = 0;
  899 + ebc0_cs2_bncr_value = 0;
  900 + ebc0_cs3_bnap_value = 0;
  901 + ebc0_cs3_bncr_value = 0;
  902 + } else {
  903 + /* Expansion Slot */
  904 + ebc0_cs1_bnap_value = 0;
  905 + ebc0_cs1_bncr_value = 0;
  906 + ebc0_cs2_bnap_value = 0;
  907 + ebc0_cs2_bncr_value = 0;
  908 + ebc0_cs3_bnap_value = 0;
  909 + ebc0_cs3_bncr_value = 0;
  910 + }
  911 +
  912 + if ((config_on_ebc_cs4_is_small_flash()) == TRUE) {
  913 + /* Small Flash */
  914 + ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
  915 + ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
  916 + } else {
  917 + /* Large Flash or SRAM */
  918 + ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
  919 + ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
  920 + }
  921 +
  922 + break;
  923 +
  924 + /*------------------------------------------------------------------------- */
  925 + case BOOT_DEVICE_UNKNOWN:
  926 + /*------------------------------------------------------------------------- */
  927 + /* Error */
  928 + break;
  929 +
  930 + }
  931 +
  932 +
  933 + /*-------------------------------------------------------------------------+
  934 + | Initialize EBC CONFIG
  935 + +-------------------------------------------------------------------------*/
  936 + mtdcr(ebccfga, xbcfg);
  937 + mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN |
  938 + EBC0_CFG_PTD_ENABLED |
  939 + EBC0_CFG_RTC_2048PERCLK |
  940 + EBC0_CFG_EMPL_LOW |
  941 + EBC0_CFG_EMPH_LOW |
  942 + EBC0_CFG_CSTC_DRIVEN |
  943 + EBC0_CFG_BPF_ONEDW |
  944 + EBC0_CFG_EMS_8BIT |
  945 + EBC0_CFG_PME_DISABLED |
  946 + EBC0_CFG_PMT_ENCODE(0) );
  947 +
  948 + /*-------------------------------------------------------------------------+
  949 + | Initialize EBC Bank 0-4
  950 + +-------------------------------------------------------------------------*/
  951 + /* EBC Bank0 */
  952 + mtebc(pb0ap, ebc0_cs0_bnap_value);
  953 + mtebc(pb0cr, ebc0_cs0_bncr_value);
  954 + /* EBC Bank1 */
  955 + mtebc(pb1ap, ebc0_cs1_bnap_value);
  956 + mtebc(pb1cr, ebc0_cs1_bncr_value);
  957 + /* EBC Bank2 */
  958 + mtebc(pb2ap, ebc0_cs2_bnap_value);
  959 + mtebc(pb2cr, ebc0_cs2_bncr_value);
  960 + /* EBC Bank3 */
  961 + mtebc(pb3ap, ebc0_cs3_bnap_value);
  962 + mtebc(pb3cr, ebc0_cs3_bncr_value);
  963 + /* EBC Bank4 */
  964 + mtebc(pb4ap, ebc0_cs4_bnap_value);
  965 + mtebc(pb4cr, ebc0_cs4_bncr_value);
  966 +
  967 + return;
  968 +}
  969 +
  970 +
  971 +/*----------------------------------------------------------------------------+
  972 + | get_uart_configuration.
  973 + +----------------------------------------------------------------------------*/
  974 +uart_config_nb_t get_uart_configuration(void)
  975 +{
  976 + return (L4); /* test-only */
  977 +}
  978 +
  979 +/*----------------------------------------------------------------------------+
  980 + | set_phy_configuration_through_fpga => to EPLD
  981 + +----------------------------------------------------------------------------*/
  982 +void set_phy_configuration_through_fpga(zmii_config_t config)
  983 +{
  984 +
  985 + unsigned long fpga_selection_reg;
  986 +
  987 + fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
  988 +
  989 + switch(config)
  990 + {
  991 + case ZMII_CONFIGURATION_IS_MII:
  992 + fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
  993 + break;
  994 + case ZMII_CONFIGURATION_IS_RMII:
  995 + fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
  996 + break;
  997 + case ZMII_CONFIGURATION_IS_SMII:
  998 + fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
  999 + break;
  1000 + case ZMII_CONFIGURATION_UNKNOWN:
  1001 + default:
  1002 + break;
  1003 + }
  1004 + out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
  1005 +
  1006 +}
  1007 +
  1008 +/*----------------------------------------------------------------------------+
  1009 + | scp_selection_in_fpga.
  1010 + +----------------------------------------------------------------------------*/
  1011 +void scp_selection_in_fpga(void)
  1012 +{
  1013 + unsigned long fpga_selection_2_reg;
  1014 +
  1015 + fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
  1016 + fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
  1017 + out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
  1018 +}
  1019 +
  1020 +/*----------------------------------------------------------------------------+
  1021 + | iic1_selection_in_fpga.
  1022 + +----------------------------------------------------------------------------*/
  1023 +void iic1_selection_in_fpga(void)
  1024 +{
  1025 + unsigned long fpga_selection_2_reg;
  1026 +
  1027 + fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
  1028 + fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
  1029 + out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
  1030 +}
  1031 +
  1032 +/*----------------------------------------------------------------------------+
  1033 + | dma_a_b_selection_in_fpga.
  1034 + +----------------------------------------------------------------------------*/
  1035 +void dma_a_b_selection_in_fpga(void)
  1036 +{
  1037 + unsigned long fpga_selection_2_reg;
  1038 +
  1039 + fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
  1040 + out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
  1041 +}
  1042 +
  1043 +/*----------------------------------------------------------------------------+
  1044 + | dma_a_b_unselect_in_fpga.
  1045 + +----------------------------------------------------------------------------*/
  1046 +void dma_a_b_unselect_in_fpga(void)
  1047 +{
  1048 + unsigned long fpga_selection_2_reg;
  1049 +
  1050 + fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
  1051 + out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
  1052 +}
  1053 +
  1054 +/*----------------------------------------------------------------------------+
  1055 + | dma_c_d_selection_in_fpga.
  1056 + +----------------------------------------------------------------------------*/
  1057 +void dma_c_d_selection_in_fpga(void)
  1058 +{
  1059 + unsigned long fpga_selection_2_reg;
  1060 +
  1061 + fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
  1062 + out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
  1063 +}
  1064 +
  1065 +/*----------------------------------------------------------------------------+
  1066 + | dma_c_d_unselect_in_fpga.
  1067 + +----------------------------------------------------------------------------*/
  1068 +void dma_c_d_unselect_in_fpga(void)
  1069 +{
  1070 + unsigned long fpga_selection_2_reg;
  1071 +
  1072 + fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
  1073 + out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
  1074 +}
  1075 +
  1076 +/*----------------------------------------------------------------------------+
  1077 + | usb2_device_selection_in_fpga.
  1078 + +----------------------------------------------------------------------------*/
  1079 +void usb2_device_selection_in_fpga(void)
  1080 +{
  1081 + unsigned long fpga_selection_1_reg;
  1082 +
  1083 + fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
  1084 + out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
  1085 +}
  1086 +
  1087 +/*----------------------------------------------------------------------------+
  1088 + | usb2_device_reset_through_fpga.
  1089 + +----------------------------------------------------------------------------*/
  1090 +void usb2_device_reset_through_fpga(void)
  1091 +{
  1092 + /* Perform soft Reset pulse */
  1093 + unsigned long fpga_reset_reg;
  1094 + int i;
  1095 +
  1096 + fpga_reset_reg = in8(FPGA_RESET_REG);
  1097 + out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
  1098 + for (i=0; i<500; i++)
  1099 + udelay(1000);
  1100 + out8(FPGA_RESET_REG,fpga_reset_reg);
  1101 +}
  1102 +
  1103 +/*----------------------------------------------------------------------------+
  1104 + | usb2_host_selection_in_fpga.
  1105 + +----------------------------------------------------------------------------*/
  1106 +void usb2_host_selection_in_fpga(void)
  1107 +{
  1108 + unsigned long fpga_selection_1_reg;
  1109 +
  1110 + fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
  1111 + out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
  1112 +}
  1113 +
  1114 +/*----------------------------------------------------------------------------+
  1115 + | ndfc_selection_in_fpga.
  1116 + +----------------------------------------------------------------------------*/
  1117 +void ndfc_selection_in_fpga(void)
  1118 +{
  1119 + unsigned long fpga_selection_1_reg;
  1120 +
  1121 + fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
  1122 + fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
  1123 + /*fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2; */
  1124 + /*fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3; */
  1125 + out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
  1126 +}
  1127 +
  1128 +/*----------------------------------------------------------------------------+
  1129 + | uart_selection_in_fpga.
  1130 + +----------------------------------------------------------------------------*/
  1131 +void uart_selection_in_fpga(uart_config_nb_t uart_config)
  1132 +{
  1133 + /* FPGA register */
  1134 + unsigned char fpga_selection_3_reg;
  1135 +
  1136 + /* Read FPGA Reagister */
  1137 + fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
  1138 +
  1139 + switch (uart_config)
  1140 + {
  1141 + case L1:
  1142 + /* ----------------------------------------------------------------------- */
  1143 + /* L1 configuration: UART0 = 8 pins */
  1144 + /* ----------------------------------------------------------------------- */
  1145 + /* Configure FPGA */
  1146 + fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
  1147 + fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
  1148 + out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
  1149 +
  1150 + break;
  1151 +
  1152 + case L2:
  1153 + /* ----------------------------------------------------------------------- */
  1154 + /* L2 configuration: UART0 = 4 pins */
  1155 + /* UART1 = 4 pins */
  1156 + /* ----------------------------------------------------------------------- */
  1157 + /* Configure FPGA */
  1158 + fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
  1159 + fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
  1160 + out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
  1161 +
  1162 + break;
  1163 +
  1164 + case L3:
  1165 + /* ----------------------------------------------------------------------- */
  1166 + /* L3 configuration: UART0 = 4 pins */
  1167 + /* UART1 = 2 pins */
  1168 + /* UART2 = 2 pins */
  1169 + /* ----------------------------------------------------------------------- */
  1170 + /* Configure FPGA */
  1171 + fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
  1172 + fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
  1173 + out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
  1174 + break;
  1175 +
  1176 + case L4:
  1177 + /* Configure FPGA */
  1178 + fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
  1179 + fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
  1180 + out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
  1181 +
  1182 + break;
  1183 +
  1184 + default:
  1185 + /* Unsupported UART configuration number */
  1186 + for (;;)
  1187 + ;
  1188 + break;
  1189 +
  1190 + }
  1191 +}
  1192 +
  1193 +
  1194 +/*----------------------------------------------------------------------------+
  1195 + | init_default_gpio
  1196 + +----------------------------------------------------------------------------*/
  1197 +void init_default_gpio(void)
  1198 +{
  1199 + int i;
  1200 +
  1201 + /* Init GPIO0 */
  1202 + for(i=0; i<GPIO_MAX; i++)
  1203 + {
  1204 + gpio_tab[GPIO0][i].add = GPIO0_BASE;
  1205 + gpio_tab[GPIO0][i].in_out = GPIO_DIS;
  1206 + gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
  1207 + }
  1208 +
  1209 + /* Init GPIO1 */
  1210 + for(i=0; i<GPIO_MAX; i++)
  1211 + {
  1212 + gpio_tab[GPIO1][i].add = GPIO1_BASE;
  1213 + gpio_tab[GPIO1][i].in_out = GPIO_DIS;
  1214 + gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
  1215 + }
  1216 +
  1217 + /* EBC_CS_N(5) - GPIO0_10 */
  1218 + gpio_tab[GPIO0][10].in_out = GPIO_OUT;
  1219 + gpio_tab[GPIO0][10].alt_nb = GPIO_ALT1;
  1220 +
  1221 + /* EBC_CS_N(4) - GPIO0_9 */
  1222 + gpio_tab[GPIO0][9].in_out = GPIO_OUT;
  1223 + gpio_tab[GPIO0][9].alt_nb = GPIO_ALT1;
  1224 +}
  1225 +
  1226 +/*----------------------------------------------------------------------------+
  1227 + | update_uart_ios
  1228 + +------------------------------------------------------------------------------
  1229 + |
  1230 + | Set UART Configuration in PowerPC440EP
  1231 + |
  1232 + | +---------------------------------------------------------------------+
  1233 + | | Configuartion | Connector | Nb of pins | Pins | Associated |
  1234 + | | Number | Port Name | available | naming | CORE |
  1235 + | +-----------------+---------------+------------+--------+-------------+
  1236 + | | L1 | Port_A | 8 | UART | UART core 0 |
  1237 + | +-----------------+---------------+------------+--------+-------------+
  1238 + | | L2 | Port_A | 4 | UART1 | UART core 0 |
  1239 + | | (L2D) | Port_B | 4 | UART2 | UART core 1 |
  1240 + | +-----------------+---------------+------------+--------+-------------+
  1241 + | | L3 | Port_A | 4 | UART1 | UART core 0 |
  1242 + | | (L3D) | Port_B | 2 | UART2 | UART core 1 |
  1243 + | | | Port_C | 2 | UART3 | UART core 2 |
  1244 + | +-----------------+---------------+------------+--------+-------------+
  1245 + | | | Port_A | 2 | UART1 | UART core 0 |
  1246 + | | L4 | Port_B | 2 | UART2 | UART core 1 |
  1247 + | | (L4D) | Port_C | 2 | UART3 | UART core 2 |
  1248 + | | | Port_D | 2 | UART4 | UART core 3 |
  1249 + | +-----------------+---------------+------------+--------+-------------+
  1250 + |
  1251 + | Involved GPIOs
  1252 + |
  1253 + | +------------------------------------------------------------------------------+
  1254 + | | GPIO | Aternate 1 | I/O | Alternate 2 | I/O | Alternate 3 | I/O |
  1255 + | +---------+------------------+-----+-----------------+-----+-------------+-----+
  1256 + | | GPIO1_2 | UART0_DCD_N | I | UART1_DSR_CTS_N | I | UART2_SOUT | O |
  1257 + | | GPIO1_3 | UART0_8PIN_DSR_N | I | UART1_RTS_DTR_N | O | UART2_SIN | I |
  1258 + | | GPIO1_4 | UART0_8PIN_CTS_N | I | NA | NA | UART3_SIN | I |
  1259 + | | GPIO1_5 | UART0_RTS_N | O | NA | NA | UART3_SOUT | O |
  1260 + | | GPIO1_6 | UART0_DTR_N | O | UART1_SOUT | O | NA | NA |
  1261 + | | GPIO1_7 | UART0_RI_N | I | UART1_SIN | I | NA | NA |
  1262 + | +------------------------------------------------------------------------------+
  1263 + |
  1264 + |
  1265 + +----------------------------------------------------------------------------*/
  1266 +
  1267 +void update_uart_ios(uart_config_nb_t uart_config)
  1268 +{
  1269 + switch (uart_config)
  1270 + {
  1271 + case L1:
  1272 + /* ----------------------------------------------------------------------- */
  1273 + /* L1 configuration: UART0 = 8 pins */
  1274 + /* ----------------------------------------------------------------------- */
  1275 + /* Update GPIO Configuration Table */
  1276 + gpio_tab[GPIO1][2].in_out = GPIO_IN;
  1277 + gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
  1278 +
  1279 + gpio_tab[GPIO1][3].in_out = GPIO_IN;
  1280 + gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
  1281 +
  1282 + gpio_tab[GPIO1][4].in_out = GPIO_IN;
  1283 + gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
  1284 +
  1285 + gpio_tab[GPIO1][5].in_out = GPIO_OUT;
  1286 + gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
  1287 +
  1288 + gpio_tab[GPIO1][6].in_out = GPIO_OUT;
  1289 + gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
  1290 +
  1291 + gpio_tab[GPIO1][7].in_out = GPIO_IN;
  1292 + gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
  1293 +
  1294 + break;
  1295 +
  1296 + case L2:
  1297 + /* ----------------------------------------------------------------------- */
  1298 + /* L2 configuration: UART0 = 4 pins */
  1299 + /* UART1 = 4 pins */
  1300 + /* ----------------------------------------------------------------------- */
  1301 + /* Update GPIO Configuration Table */
  1302 + gpio_tab[GPIO1][2].in_out = GPIO_IN;
  1303 + gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
  1304 +
  1305 + gpio_tab[GPIO1][3].in_out = GPIO_OUT;
  1306 + gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
  1307 +
  1308 + gpio_tab[GPIO1][4].in_out = GPIO_IN;
  1309 + gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
  1310 +
  1311 + gpio_tab[GPIO1][5].in_out = GPIO_OUT;
  1312 + gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
  1313 +
  1314 + gpio_tab[GPIO1][6].in_out = GPIO_OUT;
  1315 + gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
  1316 +
  1317 + gpio_tab[GPIO1][7].in_out = GPIO_IN;
  1318 + gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
  1319 +
  1320 + break;
  1321 +
  1322 + case L3:
  1323 + /* ----------------------------------------------------------------------- */
  1324 + /* L3 configuration: UART0 = 4 pins */
  1325 + /* UART1 = 2 pins */
  1326 + /* UART2 = 2 pins */
  1327 + /* ----------------------------------------------------------------------- */
  1328 + /* Update GPIO Configuration Table */
  1329 + gpio_tab[GPIO1][2].in_out = GPIO_OUT;
  1330 + gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
  1331 +
  1332 + gpio_tab[GPIO1][3].in_out = GPIO_IN;
  1333 + gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
  1334 +
  1335 + gpio_tab[GPIO1][4].in_out = GPIO_IN;
  1336 + gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
  1337 +
  1338 + gpio_tab[GPIO1][5].in_out = GPIO_OUT;
  1339 + gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
  1340 +
  1341 + gpio_tab[GPIO1][6].in_out = GPIO_OUT;
  1342 + gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
  1343 +
  1344 + gpio_tab[GPIO1][7].in_out = GPIO_IN;
  1345 + gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
  1346 +
  1347 + break;
  1348 +
  1349 + case L4:
  1350 + /* ----------------------------------------------------------------------- */
  1351 + /* L4 configuration: UART0 = 2 pins */
  1352 + /* UART1 = 2 pins */
  1353 + /* UART2 = 2 pins */
  1354 + /* UART3 = 2 pins */
  1355 + /* ----------------------------------------------------------------------- */
  1356 + /* Update GPIO Configuration Table */
  1357 + gpio_tab[GPIO1][2].in_out = GPIO_OUT;
  1358 + gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
  1359 +
  1360 + gpio_tab[GPIO1][3].in_out = GPIO_IN;
  1361 + gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
  1362 +
  1363 + gpio_tab[GPIO1][4].in_out = GPIO_IN;
  1364 + gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
  1365 +
  1366 + gpio_tab[GPIO1][5].in_out = GPIO_OUT;
  1367 + gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
  1368 +
  1369 + gpio_tab[GPIO1][6].in_out = GPIO_OUT;
  1370 + gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
  1371 +
  1372 + gpio_tab[GPIO1][7].in_out = GPIO_IN;
  1373 + gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
  1374 +
  1375 + break;
  1376 +
  1377 + default:
  1378 + /* Unsupported UART configuration number */
  1379 + printf("ERROR - Unsupported UART configuration number.\n\n");
  1380 + for (;;)
  1381 + ;
  1382 + break;
  1383 +
  1384 + }
  1385 +
  1386 + /* Set input Selection Register on Alt_Receive for UART Input Core */
  1387 + out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
  1388 + out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
  1389 + out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
  1390 +}
  1391 +
  1392 +/*----------------------------------------------------------------------------+
  1393 + | update_ndfc_ios(void).
  1394 + +----------------------------------------------------------------------------*/
  1395 +void update_ndfc_ios(void)
  1396 +{
  1397 + /* Update GPIO Configuration Table */
  1398 + gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */
  1399 + gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
  1400 +
  1401 +#if 0
  1402 + gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */
  1403 + gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
  1404 +
  1405 + gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */
  1406 + gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
439 1407 #endif
  1408 +}
  1409 +
  1410 +/*----------------------------------------------------------------------------+
  1411 + | update_zii_ios(void).
  1412 + +----------------------------------------------------------------------------*/
  1413 +void update_zii_ios(void)
  1414 +{
  1415 + /* Update GPIO Configuration Table */
  1416 + gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */
  1417 + gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
  1418 +
  1419 + gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */
  1420 + gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
  1421 +
  1422 + gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */
  1423 + gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
  1424 +
  1425 + gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */
  1426 + gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
  1427 +
  1428 + gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */
  1429 + gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
  1430 +
  1431 + gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */
  1432 + gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
  1433 +
  1434 + gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */
  1435 + gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
  1436 +
  1437 + gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */
  1438 + gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
  1439 +
  1440 + gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */
  1441 + gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
  1442 +
  1443 + gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */
  1444 + gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
  1445 +
  1446 + gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */
  1447 + gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
  1448 +
  1449 + gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */
  1450 + gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
  1451 +
  1452 + gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */
  1453 + gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
  1454 +
  1455 + gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */
  1456 + gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
  1457 +
  1458 +}
  1459 +
  1460 +/*----------------------------------------------------------------------------+
  1461 + | update_uic_0_3_irq_ios().
  1462 + +----------------------------------------------------------------------------*/
  1463 +void update_uic_0_3_irq_ios(void)
  1464 +{
  1465 + gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */
  1466 + gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
  1467 +
  1468 + gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */
  1469 + gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
  1470 +
  1471 + gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */
  1472 + gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
  1473 +
  1474 + gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */
  1475 + gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
  1476 +}
  1477 +
  1478 +/*----------------------------------------------------------------------------+
  1479 + | update_uic_4_9_irq_ios().
  1480 + +----------------------------------------------------------------------------*/
  1481 +void update_uic_4_9_irq_ios(void)
  1482 +{
  1483 + gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */
  1484 + gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
  1485 +
  1486 + gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */
  1487 + gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
  1488 +
  1489 + gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */
  1490 + gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
  1491 +
  1492 + gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */
  1493 + gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
  1494 +
  1495 + gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */
  1496 + gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
  1497 +}
  1498 +
  1499 +/*----------------------------------------------------------------------------+
  1500 + | update_dma_a_b_ios().
  1501 + +----------------------------------------------------------------------------*/
  1502 +void update_dma_a_b_ios(void)
  1503 +{
  1504 + gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */
  1505 + gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
  1506 +
  1507 + gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */
  1508 + gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
  1509 +
  1510 + gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */
  1511 + gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
  1512 +
  1513 + gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */
  1514 + gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
  1515 +
  1516 + gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */
  1517 + gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
  1518 +}
  1519 +
  1520 +/*----------------------------------------------------------------------------+
  1521 + | update_dma_c_d_ios().
  1522 + +----------------------------------------------------------------------------*/
  1523 +void update_dma_c_d_ios(void)
  1524 +{
  1525 + gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */
  1526 + gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
  1527 +
  1528 + gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */
  1529 + gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
  1530 +
  1531 + gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */
  1532 + gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
  1533 +
  1534 + gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */
  1535 + gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
  1536 +
  1537 + gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */
  1538 + gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
  1539 +
  1540 + gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */
  1541 + gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
  1542 +
  1543 +}
  1544 +
  1545 +/*----------------------------------------------------------------------------+
  1546 + | update_ebc_master_ios().
  1547 + +----------------------------------------------------------------------------*/
  1548 +void update_ebc_master_ios(void)
  1549 +{
  1550 + gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */
  1551 + gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
  1552 +
  1553 + gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
  1554 + gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
  1555 +
  1556 + gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */
  1557 + gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
  1558 +
  1559 + gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */
  1560 + gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
  1561 +}
  1562 +
  1563 +/*----------------------------------------------------------------------------+
  1564 + | update_usb2_device_ios().
  1565 + +----------------------------------------------------------------------------*/
  1566 +void update_usb2_device_ios(void)
  1567 +{
  1568 + gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */
  1569 + gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
  1570 +
  1571 + gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */
  1572 + gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
  1573 +
  1574 + gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */
  1575 + gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
  1576 +
  1577 + gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */
  1578 + gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
  1579 +
  1580 + gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */
  1581 + gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
  1582 +
  1583 + gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */
  1584 + gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
  1585 +
  1586 + gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */
  1587 + gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
  1588 +
  1589 + gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */
  1590 + gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
  1591 +
  1592 +}
  1593 +
  1594 +/*----------------------------------------------------------------------------+
  1595 + | update_pci_patch_ios().
  1596 + +----------------------------------------------------------------------------*/
  1597 +void update_pci_patch_ios(void)
  1598 +{
  1599 + gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
  1600 + gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
  1601 +}
  1602 +
  1603 +/*----------------------------------------------------------------------------+
  1604 + | set_chip_gpio_configuration(unsigned char gpio_core)
  1605 + | Put the core impacted by clock modification and sharing in reset.
  1606 + | Config the select registers to resolve the sharing depending of the config.
  1607 + | Configure the GPIO registers.
  1608 + |
  1609 + +----------------------------------------------------------------------------*/
  1610 +void set_chip_gpio_configuration(unsigned char gpio_core)
  1611 +{
  1612 + unsigned char i=0, j=0, reg_offset = 0;
  1613 + unsigned long gpio_reg, gpio_core_add;
  1614 +
  1615 + /* GPIO config of the GPIOs 0 to 31 */
  1616 + for (i=0; i<GPIO_MAX; i++, j++)
  1617 + {
  1618 + if (i == GPIO_MAX/2)
  1619 + {
  1620 + reg_offset = 4;
  1621 + j = i-16;
  1622 + }
  1623 +
  1624 + gpio_core_add = gpio_tab[gpio_core][i].add;
  1625 +
  1626 + if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
  1627 + (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
  1628 + {
  1629 + switch (gpio_tab[gpio_core][i].alt_nb)
  1630 + {
  1631 + case GPIO_SEL:
  1632 + break;
  1633 +
  1634 + case GPIO_ALT1:
  1635 + gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
  1636 + gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
  1637 + out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
  1638 + break;
  1639 +
  1640 + case GPIO_ALT2:
  1641 + gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
  1642 + gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
  1643 + out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
  1644 + break;
  1645 +
  1646 + case GPIO_ALT3:
  1647 + gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
  1648 + gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
  1649 + out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
  1650 + break;
  1651 + }
  1652 + }
  1653 + if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
  1654 + (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
  1655 + {
  1656 +
  1657 + switch (gpio_tab[gpio_core][i].alt_nb)
  1658 + {
  1659 + case GPIO_SEL:
  1660 + break;
  1661 + case GPIO_ALT1:
  1662 + gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
  1663 + gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
  1664 + out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
  1665 + gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
  1666 + gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
  1667 + out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
  1668 + break;
  1669 + case GPIO_ALT2:
  1670 + gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
  1671 + gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
  1672 + out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
  1673 + gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
  1674 + gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
  1675 + out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
  1676 + break;
  1677 + case GPIO_ALT3:
  1678 + gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
  1679 + gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
  1680 + out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
  1681 + gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
  1682 + gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
  1683 + out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
  1684 + break;
  1685 + }
  1686 + }
  1687 + }
  1688 +}
  1689 +
  1690 +/*----------------------------------------------------------------------------+
  1691 + | force_bup_core_selection.
  1692 + +----------------------------------------------------------------------------*/
  1693 +void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
  1694 +{
  1695 + /* Pointer invalid */
  1696 + if (core_select_P == NULL)
  1697 + {
  1698 + printf("Configuration invalid pointer 1\n");
  1699 + for (;;)
  1700 + ;
  1701 + }
  1702 +
  1703 + /* L4 Selection */
  1704 + *(core_select_P+UART_CORE0) = CORE_SELECTED;
  1705 + *(core_select_P+UART_CORE1) = CORE_SELECTED;
  1706 + *(core_select_P+UART_CORE2) = CORE_SELECTED;
  1707 + *(core_select_P+UART_CORE3) = CORE_SELECTED;
  1708 +
  1709 + /* RMII Selection */
  1710 + *(core_select_P+RMII_SEL) = CORE_SELECTED;
  1711 +
  1712 + /* External Interrupt 0-9 selection */
  1713 + *(core_select_P+UIC_0_3) = CORE_SELECTED;
  1714 + *(core_select_P+UIC_4_9) = CORE_SELECTED;
  1715 +
  1716 + *(core_select_P+SCP_CORE) = CORE_SELECTED;
  1717 + *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED;
  1718 + *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED;
  1719 + *(core_select_P+USB1_DEVICE) = CORE_SELECTED;
  1720 +
  1721 + *config_val_P = CONFIG_IS_VALID;
  1722 +
  1723 +}
  1724 +
  1725 +/*----------------------------------------------------------------------------+
  1726 + | configure_ppc440ep_pins.
  1727 + +----------------------------------------------------------------------------*/
  1728 +void configure_ppc440ep_pins(void)
  1729 +{
  1730 + uart_config_nb_t uart_configuration;
  1731 + config_validity_t config_val = CONFIG_IS_INVALID;
  1732 +
  1733 + /* Create Core Selection Table */
  1734 + core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
  1735 + {
  1736 + CORE_NOT_SELECTED, /* IIC_CORE, */
  1737 + CORE_NOT_SELECTED, /* SPC_CORE, */
  1738 + CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */
  1739 + CORE_NOT_SELECTED, /* UIC_4_9, */
  1740 + CORE_NOT_SELECTED, /* USB2_HOST, */
  1741 + CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */
  1742 + CORE_NOT_SELECTED, /* USB2_DEVICE, */
  1743 + CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */
  1744 + CORE_NOT_SELECTED, /* USB1_DEVICE, */
  1745 + CORE_NOT_SELECTED, /* EBC_MASTER, */
  1746 + CORE_NOT_SELECTED, /* NAND_FLASH, */
  1747 + CORE_NOT_SELECTED, /* UART_CORE0, */
  1748 + CORE_NOT_SELECTED, /* UART_CORE1, */
  1749 + CORE_NOT_SELECTED, /* UART_CORE2, */
  1750 + CORE_NOT_SELECTED, /* UART_CORE3, */
  1751 + CORE_NOT_SELECTED, /* MII_SEL, */
  1752 + CORE_NOT_SELECTED, /* RMII_SEL, */
  1753 + CORE_NOT_SELECTED, /* SMII_SEL, */
  1754 + CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */
  1755 + CORE_NOT_SELECTED, /* UIC_0_3 */
  1756 + CORE_NOT_SELECTED, /* USB1_HOST */
  1757 + CORE_NOT_SELECTED /* PCI_PATCH */
  1758 + };
  1759 +
  1760 +
  1761 + /* Table Default Initialisation + FPGA Access */
  1762 + init_default_gpio();
  1763 + set_chip_gpio_configuration(GPIO0);
  1764 + set_chip_gpio_configuration(GPIO1);
  1765 +
  1766 + /* Update Table */
  1767 + force_bup_core_selection(ppc440ep_core_selection, &config_val);
  1768 +#if 0 /* test-only */
  1769 + /* If we are running PIBS 1, force known configuration */
  1770 + update_core_selection_table(ppc440ep_core_selection, &config_val);
  1771 +#endif
  1772 +
  1773 + /*----------------------------------------------------------------------------+
  1774 + | SDR + ios table update + fpga initialization
  1775 + +----------------------------------------------------------------------------*/
  1776 + unsigned long sdr0_pfc1 = 0;
  1777 + unsigned long sdr0_usb0 = 0;
  1778 + unsigned long sdr0_mfr = 0;
  1779 +
  1780 + /* PCI Always selected */
  1781 +
  1782 + /* I2C Selection */
  1783 + if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
  1784 + {
  1785 + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
  1786 + iic1_selection_in_fpga();
  1787 + }
  1788 +
  1789 + /* SCP Selection */
  1790 + if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
  1791 + {
  1792 + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
  1793 + scp_selection_in_fpga();
  1794 + }
  1795 +
  1796 + /* UIC 0:3 Selection */
  1797 + if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
  1798 + {
  1799 + update_uic_0_3_irq_ios();
  1800 + dma_a_b_unselect_in_fpga();
  1801 + }
  1802 +
  1803 + /* UIC 4:9 Selection */
  1804 + if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
  1805 + {
  1806 + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
  1807 + update_uic_4_9_irq_ios();
  1808 + }
  1809 +
  1810 + /* DMA AB Selection */
  1811 + if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
  1812 + {
  1813 + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
  1814 + update_dma_a_b_ios();
  1815 + dma_a_b_selection_in_fpga();
  1816 + }
  1817 +
  1818 + /* DMA CD Selection */
  1819 + if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
  1820 + {
  1821 + update_dma_c_d_ios();
  1822 + dma_c_d_selection_in_fpga();
  1823 + }
  1824 +
  1825 + /* EBC Master Selection */
  1826 + if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
  1827 + {
  1828 + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
  1829 + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
  1830 + update_ebc_master_ios();
  1831 + }
  1832 +
  1833 + /* PCI Patch Enable */
  1834 + if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
  1835 + {
  1836 + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
  1837 + update_pci_patch_ios();
  1838 + }
  1839 +
  1840 + /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
  1841 + if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
  1842 + {
  1843 + /* Not Implemented in PowerPC 440EP Pass1-Pass2 */
  1844 + printf("Invalid configuration => USB2 Host selected\n");
  1845 + for (;;)
  1846 + ;
  1847 + /*usb2_host_selection_in_fpga(); */
  1848 + }
  1849 +
  1850 + /* USB2.0 Device Selection */
  1851 + if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
  1852 + {
  1853 + update_usb2_device_ios();
  1854 + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
  1855 + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
  1856 +
  1857 + mfsdr(sdr_usb0, sdr0_usb0);
  1858 + sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
  1859 + sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
  1860 + mtsdr(sdr_usb0, sdr0_usb0);
  1861 +
  1862 + usb2_device_selection_in_fpga();
  1863 + }
  1864 +
  1865 + /* USB1.1 Device Selection */
  1866 + if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
  1867 + {
  1868 + mfsdr(sdr_usb0, sdr0_usb0);
  1869 + sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
  1870 + sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
  1871 + mtsdr(sdr_usb0, sdr0_usb0);
  1872 + }
  1873 +
  1874 + /* USB1.1 Host Selection */
  1875 + if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
  1876 + {
  1877 + mfsdr(sdr_usb0, sdr0_usb0);
  1878 + sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
  1879 + sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
  1880 + mtsdr(sdr_usb0, sdr0_usb0);
  1881 + }
  1882 +
  1883 + /* NAND Flash Selection */
  1884 + if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
  1885 + {
  1886 + update_ndfc_ios();
  1887 +
  1888 + mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL |
  1889 + SDR0_CUST0_NDFC_ENABLE |
  1890 + SDR0_CUST0_NDFC_BW_8_BIT |
  1891 + SDR0_CUST0_NDFC_ARE_MASK |
  1892 + SDR0_CUST0_CHIPSELGAT_EN1 );
  1893 + /*SDR0_CUST0_CHIPSELGAT_EN2 ); */
  1894 + /*SDR0_CUST0_CHIPSELGAT_EN3 ); */
  1895 +
  1896 + ndfc_selection_in_fpga();
  1897 + }
  1898 + else
  1899 + {
  1900 + /* Set Mux on EMAC */
  1901 + mtsdr(sdr_cust0, SDR0_CUST0_MUX_EMAC_SEL);
  1902 + }
  1903 +
  1904 + /* MII Selection */
  1905 + if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
  1906 + {
  1907 + update_zii_ios();
  1908 + mfsdr(sdr_mfr, sdr0_mfr);
  1909 + sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
  1910 + mtsdr(sdr_mfr, sdr0_mfr);
  1911 +
  1912 + set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
  1913 + }
  1914 +
  1915 + /* RMII Selection */
  1916 + if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
  1917 + {
  1918 + update_zii_ios();
  1919 + mfsdr(sdr_mfr, sdr0_mfr);
  1920 + sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
  1921 + mtsdr(sdr_mfr, sdr0_mfr);
  1922 +
  1923 + set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
  1924 + }
  1925 +
  1926 + /* SMII Selection */
  1927 + if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
  1928 + {
  1929 + update_zii_ios();
  1930 + mfsdr(sdr_mfr, sdr0_mfr);
  1931 + sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
  1932 + mtsdr(sdr_mfr, sdr0_mfr);
  1933 +
  1934 + set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
  1935 + }
  1936 +
  1937 + /* UART Selection */
  1938 + uart_configuration = get_uart_configuration();
  1939 + switch (uart_configuration)
  1940 + {
  1941 + case L1: /* L1 Selection */
  1942 + /* UART0 8 pins Only */
  1943 + /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
  1944 + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */
  1945 + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
  1946 + break;
  1947 + case L2: /* L2 Selection */
  1948 + /* UART0 and UART1 4 pins */
  1949 + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
  1950 + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
  1951 + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
  1952 + break;
  1953 + case L3: /* L3 Selection */
  1954 + /* UART0 4 pins, UART1 and UART2 2 pins */
  1955 + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
  1956 + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
  1957 + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
  1958 + break;
  1959 + case L4: /* L4 Selection */
  1960 + /* UART0, UART1, UART2 and UART3 2 pins */
  1961 + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
  1962 + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
  1963 + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
  1964 + break;
  1965 + }
  1966 + update_uart_ios(uart_configuration);
  1967 +
  1968 + /* UART Selection in all cases */
  1969 + uart_selection_in_fpga(uart_configuration);
  1970 +
  1971 + /* Packet Reject Function Available */
  1972 + if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
  1973 + {
  1974 + /* Set UPR Bit in SDR0_PFC1 Register */
  1975 + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
  1976 + }
  1977 +
  1978 + /* Packet Reject Function Enable */
  1979 + if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
  1980 + {
  1981 + mfsdr(sdr_mfr, sdr0_mfr);
  1982 + sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
  1983 + mtsdr(sdr_mfr, sdr0_mfr);
  1984 + }
  1985 +
  1986 + /* Perform effective access to hardware */
  1987 + mtsdr(sdr_pfc1, sdr0_pfc1);
  1988 + set_chip_gpio_configuration(GPIO0);
  1989 + set_chip_gpio_configuration(GPIO1);
  1990 +
  1991 + /* USB2.0 Device Reset must be done after GPIO setting */
  1992 + if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
  1993 + usb2_device_reset_through_fpga();
  1994 +
  1995 +}
board/amcc/bamboo/bamboo.h
Diff comments   View file @ 17f50f2
  1 +/*
  2 + * (C) Copyright 2005
  3 + * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +/*----------------------------------------------------------------------------+
  25 + | FPGA registers and bit definitions
  26 + +----------------------------------------------------------------------------*/
  27 +/*
  28 + * PowerPC 440EP Board FPGA is reached with physical address 0x80001FF0.
  29 + * TLB initialization makes it correspond to logical address 0x80001FF0.
  30 + * => Done init_chip.s in bootlib
  31 + */
  32 +#define FPGA_BASE_ADDR 0x80002000
  33 +
  34 +/*----------------------------------------------------------------------------+
  35 + | Board Jumpers Setting Register
  36 + | Board Settings provided by jumpers
  37 + +----------------------------------------------------------------------------*/
  38 +#define FPGA_SETTING_REG (FPGA_BASE_ADDR+0x3)
  39 +/* Boot from small flash */
  40 +#define FPGA_SET_REG_BOOT_SMALL_FLASH 0x80
  41 +/* Operational Flash versus SRAM position in Memory Map */
  42 +#define FPGA_SET_REG_OP_CODE_SRAM_SEL_MASK 0x40
  43 +#define FPGA_SET_REG_OP_CODE_FLASH_ABOVE 0x40
  44 +#define FPGA_SET_REG_SRAM_ABOVE 0x00
  45 +/* Boot From NAND Flash */
  46 +#define FPGA_SET_REG_BOOT_NAND_FLASH_MASK 0x40
  47 +#define FPGA_SET_REG_BOOT_NAND_FLASH_SELECT 0x00
  48 +/* On Board PCI Arbiter Select */
  49 +#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL_MASK 0x10
  50 +#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL 0x00
  51 +
  52 +/*----------------------------------------------------------------------------+
  53 + | Functions Selection Register 1
  54 + +----------------------------------------------------------------------------*/
  55 +#define FPGA_SELECTION_1_REG (FPGA_BASE_ADDR+0x4)
  56 +#define FPGA_SEL_1_REG_PHY_MASK 0xE0
  57 +#define FPGA_SEL_1_REG_MII 0x80
  58 +#define FPGA_SEL_1_REG_RMII 0x40
  59 +#define FPGA_SEL_1_REG_SMII 0x20
  60 +#define FPGA_SEL_1_REG_USB2_DEV_SEL 0x10 /* USB2 Device Selection */
  61 +#define FPGA_SEL_1_REG_USB2_HOST_SEL 0x08 /* USB2 Host Selection */
  62 +#define FPGA_SEL_1_REG_NF_SELEC_MASK 0x07 /* NF Selection Mask */
  63 +#define FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1 0x04 /* NF0 Selected by NF_CS1 */
  64 +#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2 0x02 /* NF1 Selected by NF_CS2 */
  65 +#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3 0x01 /* NF1 Selected by NF_CS3 */
  66 +
  67 +/*----------------------------------------------------------------------------+
  68 + | Functions Selection Register 2
  69 + +----------------------------------------------------------------------------*/
  70 +#define FPGA_SELECTION_2_REG (FPGA_BASE_ADDR+0x5)
  71 +#define FPGA_SEL2_REG_IIC1_SCP_SEL_MASK 0x80 /* IIC1 / SCP Selection */
  72 +#define FPGA_SEL2_REG_SEL_FRAM 0x80 /* FRAM on IIC1 bus selected - SCP Select */
  73 +#define FPGA_SEL2_REG_SEL_SCP 0x80 /* Identical to SCP Selection */
  74 +#define FPGA_SEL2_REG_SEL_IIC1 0x00 /* IIC1 Selection - Default Value */
  75 +#define FPGA_SEL2_REG_SEL_DMA_A_B 0x40 /* DMA A & B channels selected */
  76 +#define FPGA_SEL2_REG_SEL_DMA_C_D 0x20 /* DMA C & D channels selected */
  77 +#define FPGA_SEL2_REG_DMA_EOT_TC_3_SEL 0x10 /* 0 = EOT - input to 440EP */
  78 + /* 1 = TC - output from 440EP */
  79 +#define FPGA_SEL2_REG_DMA_EOT_TC_2_SEL 0x08 /* 0 = EOT (input to 440EP) */
  80 + /* 1 = TC (output from 440EP) */
  81 +#define FPGA_SEL2_REG_SEL_GPIO_1 0x04 /* EBC_GPIO & USB2_GPIO selected */
  82 +#define FPGA_SEL2_REG_SEL_GPIO_2 0x02 /* Ether._GPIO & UART_GPIO selected */
  83 +#define FPGA_SEL2_REG_SEL_GPIO_3 0x01 /* DMA_GPIO & Trace_GPIO selected */
  84 +
  85 +/*----------------------------------------------------------------------------+
  86 + | Functions Selection Register 3
  87 + +----------------------------------------------------------------------------*/
  88 +#define FPGA_SELECTION_3_REG (FPGA_BASE_ADDR+0x6)
  89 +#define FPGA_SEL3_REG_EXP_SLOT_EN 0x80 /* Expansion Slot enabled */
  90 +#define FPGA_SEL3_REG_SEL_UART_CONFIG_MASK 0x70
  91 +#define FPGA_SEL3_REG_SEL_UART_CONFIG1 0x40 /* one 8_pin UART */
  92 +#define FPGA_SEL3_REG_SEL_UART_CONFIG2 0x20 /* two 4_pin UARTs */
  93 +#define FPGA_SEL3_REG_SEL_UART_CONFIG3 0x10 /* one 4_pin & two 2_pin UARTs */
  94 +#define FPGA_SEL3_REG_SEL_UART_CONFIG4 0x08 /* four 2_pin UARTs */
  95 +#define FPGA_SEL3_REG_DTR_DSR_MODE_4_PIN_UART 0x00 /* DTR/DSR mode for 4_pin_UART */
  96 +#define FPGA_SEL3_REG_RTS_CTS_MODE_4_PIN_UART 0x04 /* RTS/CTS mode for 4_pin_UART */
  97 +
  98 +/*----------------------------------------------------------------------------+
  99 + | Soft Reset Register
  100 + +----------------------------------------------------------------------------*/
  101 +#define FPGA_RESET_REG (FPGA_BASE_ADDR+0x7)
  102 +#define FPGA_RESET_REG_RESET_USB20_DEV 0x80 /* Hard Reset of the GT3200 */
  103 +#define FPGA_RESET_REG_RESET_DISPLAY 0x40 /* Hard Reset on Display Device */
  104 +#define FPGA_RESET_REG_STATUS_LED_0 0x08 /* 1 = Led On */
  105 +#define FPGA_RESET_REG_STATUS_LED_1 0x04 /* 1 = Led On */
  106 +#define FPGA_RESET_REG_STATUS_LED_2 0x02 /* 1 = Led On */
  107 +#define FPGA_RESET_REG_STATUS_LED_3 0x01 /* 1 = Led On */
  108 +
  109 +
  110 +/*----------------------------------------------------------------------------+
  111 +| SDR Configuration registers
  112 ++----------------------------------------------------------------------------*/
  113 +/* Serial Device Strap Reg 0 */
  114 +#define SDR0_SDSTP0 0x0020
  115 +/* Serial Device Strap Reg 1 */
  116 +#define SDR0_SDSTP1 0x0021
  117 +/* Serial Device Strap Reg 2 */
  118 +#define SDR0_SDSTP2 SDR0_STRP2
  119 +/* Serial Device Strap Reg 3 */
  120 +#define SDR0_SDSTP3 SDR0_STRP3
  121 +
  122 +#define sdr_pstrp0 0x0040
  123 +
  124 +#define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00006000 /* EBC Boot Size Mask */
  125 +#define SDR0_SDSTP1_EBC_ROM_BS_32BIT 0x00004000 /* EBC 32 bits */
  126 +#define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00002000 /* EBC 16 Bits */
  127 +#define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */
  128 +
  129 +#define SDR0_SDSTP1_BOOT_SEL_MASK 0x00001800 /* Boot device Selection Mask */
  130 +#define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */
  131 +#define SDR0_SDSTP1_BOOT_SEL_PCI 0x00000800 /* PCI */
  132 +#define SDR0_SDSTP1_BOOT_SEL_NDFC 0x00001000 /* NDFC */
  133 +
  134 +/* Serial Device Enabled - Addr = 0xA8 */
  135 +#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
  136 +/* Serial Device Enabled - Addr = 0xA4 */
  137 +#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7
  138 +
  139 +/* Pin Straps Reg */
  140 +#define SDR0_PSTRP0 0x0040
  141 +#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */
  142 +
  143 +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */
  144 +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */
  145 +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */
  146 +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */
  147 +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */
  148 +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */
  149 +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */
  150 +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */
  151 +
  152 +/*----------------------------------------------------------------------------+
  153 +| EBC Configuration Register - EBC0_CFG
  154 ++----------------------------------------------------------------------------*/
  155 +/* External Bus Three-State Control */
  156 +#define EBC0_CFG_EBTC_DRIVEN 0x80000000
  157 +/* Device-Paced Time-out Disable */
  158 +#define EBC0_CFG_PTD_ENABLED 0x00000000
  159 +/* Ready Timeout Count */
  160 +#define EBC0_CFG_RTC_MASK 0x38000000
  161 +#define EBC0_CFG_RTC_16PERCLK 0x00000000
  162 +#define EBC0_CFG_RTC_32PERCLK 0x08000000
  163 +#define EBC0_CFG_RTC_64PERCLK 0x10000000
  164 +#define EBC0_CFG_RTC_128PERCLK 0x18000000
  165 +#define EBC0_CFG_RTC_256PERCLK 0x20000000
  166 +#define EBC0_CFG_RTC_512PERCLK 0x28000000
  167 +#define EBC0_CFG_RTC_1024PERCLK 0x30000000
  168 +#define EBC0_CFG_RTC_2048PERCLK 0x38000000
  169 +/* External Master Priority Low */
  170 +#define EBC0_CFG_EMPL_LOW 0x00000000
  171 +#define EBC0_CFG_EMPL_MEDIUM_LOW 0x02000000
  172 +#define EBC0_CFG_EMPL_MEDIUM_HIGH 0x04000000
  173 +#define EBC0_CFG_EMPL_HIGH 0x06000000
  174 +/* External Master Priority High */
  175 +#define EBC0_CFG_EMPH_LOW 0x00000000
  176 +#define EBC0_CFG_EMPH_MEDIUM_LOW 0x00800000
  177 +#define EBC0_CFG_EMPH_MEDIUM_HIGH 0x01000000
  178 +#define EBC0_CFG_EMPH_HIGH 0x01800000
  179 +/* Chip Select Three-State Control */
  180 +#define EBC0_CFG_CSTC_DRIVEN 0x00400000
  181 +/* Burst Prefetch */
  182 +#define EBC0_CFG_BPF_ONEDW 0x00000000
  183 +#define EBC0_CFG_BPF_TWODW 0x00100000
  184 +#define EBC0_CFG_BPF_FOURDW 0x00200000
  185 +/* External Master Size */
  186 +#define EBC0_CFG_EMS_8BIT 0x00000000
  187 +/* Power Management Enable */
  188 +#define EBC0_CFG_PME_DISABLED 0x00000000
  189 +#define EBC0_CFG_PME_ENABLED 0x00020000
  190 +/* Power Management Timer */
  191 +#define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
  192 +
  193 +/*----------------------------------------------------------------------------+
  194 +| Peripheral Bank Configuration Register - EBC0_BnCR
  195 ++----------------------------------------------------------------------------*/
  196 +/* BAS - Base Address Select */
  197 +#define EBC0_BNCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0)
  198 +/* BS - Bank Size */
  199 +#define EBC0_BNCR_BS_MASK 0x000E0000
  200 +#define EBC0_BNCR_BS_1MB 0x00000000
  201 +#define EBC0_BNCR_BS_2MB 0x00020000
  202 +#define EBC0_BNCR_BS_4MB 0x00040000
  203 +#define EBC0_BNCR_BS_8MB 0x00060000
  204 +#define EBC0_BNCR_BS_16MB 0x00080000
  205 +#define EBC0_BNCR_BS_32MB 0x000A0000
  206 +#define EBC0_BNCR_BS_64MB 0x000C0000
  207 +#define EBC0_BNCR_BS_128MB 0x000E0000
  208 +/* BU - Bank Usage */
  209 +#define EBC0_BNCR_BU_MASK 0x00018000
  210 +#define EBC0_BNCR_BU_RO 0x00008000
  211 +#define EBC0_BNCR_BU_WO 0x00010000
  212 +#define EBC0_BNCR_BU_RW 0x00018000
  213 +/* BW - Bus Width */
  214 +#define EBC0_BNCR_BW_MASK 0x00006000
  215 +#define EBC0_BNCR_BW_8BIT 0x00000000
  216 +#define EBC0_BNCR_BW_16BIT 0x00002000
  217 +#define EBC0_BNCR_BW_32BIT 0x00004000
  218 +
  219 +/*----------------------------------------------------------------------------+
  220 +| Peripheral Bank Access Parameters - EBC0_BnAP
  221 ++----------------------------------------------------------------------------*/
  222 +/* Burst Mode Enable */
  223 +#define EBC0_BNAP_BME_ENABLED 0x80000000
  224 +#define EBC0_BNAP_BME_DISABLED 0x00000000
  225 +/* Transfert Wait */
  226 +#define EBC0_BNAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23) /* Bits 1:8 */
  227 +/* Chip Select On Timing */
  228 +#define EBC0_BNAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18) /* Bits 12:13 */
  229 +/* Output Enable On Timing */
  230 +#define EBC0_BNAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) /* Bits 14:15 */
  231 +/* Write Back Enable On Timing */
  232 +#define EBC0_BNAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14) /* Bits 16:17 */
  233 +/* Write Back Enable Off Timing */
  234 +#define EBC0_BNAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12) /* Bits 18:19 */
  235 +/* Transfert Hold */
  236 +#define EBC0_BNAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9) /* Bits 20:22 */
  237 +/* PerReady Enable */
  238 +#define EBC0_BNAP_RE_ENABLED 0x00000100
  239 +#define EBC0_BNAP_RE_DISABLED 0x00000000
  240 +/* Sample On Ready */
  241 +#define EBC0_BNAP_SOR_DELAYED 0x00000000
  242 +#define EBC0_BNAP_SOR_NOT_DELAYED 0x00000080
  243 +/* Byte Enable Mode */
  244 +#define EBC0_BNAP_BEM_WRITEONLY 0x00000000
  245 +#define EBC0_BNAP_BEM_RW 0x00000040
  246 +/* Parity Enable */
  247 +#define EBC0_BNAP_PEN_DISABLED 0x00000000
  248 +#define EBC0_BNAP_PEN_ENABLED 0x00000020
  249 +
  250 +/*----------------------------------------------------------------------------+
  251 +| Define Boot devices
  252 ++----------------------------------------------------------------------------*/
  253 +/* */
  254 +#define BOOT_FROM_SMALL_FLASH 0x00
  255 +#define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01
  256 +#define BOOT_FROM_NAND_FLASH0 0x02
  257 +#define BOOT_FROM_PCI 0x03
  258 +#define BOOT_DEVICE_UNKNOWN 0x04
  259 +
  260 +
  261 +#define PVR_POWERPC_440EP_PASS1 0x42221850
  262 +#define PVR_POWERPC_440EP_PASS2 0x422218D3
  263 +
  264 +#define TRUE 1
  265 +#define FALSE 0
  266 +
  267 +#define GPIO_GROUP_MAX 2
  268 +#define GPIO_MAX 32
  269 +#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */
  270 +#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */
  271 +#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */
  272 +#define GPIO_MASK 0xC0000000 /* GPIO_MASK */
  273 +#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
  274 + /* For the other GPIO number, you must shift */
  275 +
  276 +#define GPIO0 0
  277 +#define GPIO1 1
  278 +
  279 +
  280 +/*#define MAX_SELECTION_NB CORE_NB */
  281 +#define MAX_CORE_SELECT_NB 22
  282 +
  283 +/*----------------------------------------------------------------------------+
  284 + | PPC440EP GPIOs addresses.
  285 + +----------------------------------------------------------------------------*/
  286 +#define GPIO0_BASE 0xEF600B00
  287 +#define GPIO0_REAL 0xEF600B00
  288 +
  289 +#define GPIO1_BASE 0xEF600C00
  290 +#define GPIO1_REAL 0xEF600C00
  291 +
  292 +/* Offsets */
  293 +#define GPIOx_OR 0x00 /* GPIO Output Register */
  294 +#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
  295 +#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */
  296 +#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */
  297 +#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */
  298 +#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */
  299 +#define GPIOx_ODR 0x18 /* GPIO Open drain Register */
  300 +#define GPIOx_IR 0x1C /* GPIO Input Register */
  301 +#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */
  302 +#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */
  303 +#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */
  304 +#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */
  305 +#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */
  306 +#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */
  307 +#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */
  308 +#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */
  309 +#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */
  310 +
  311 +/* GPIO0 */
  312 +#define GPIO0_IS1L (GPIO0_BASE+GPIOx_IS1L)
  313 +#define GPIO0_IS1H (GPIO0_BASE+GPIOx_IS1H)
  314 +#define GPIO0_IS2L (GPIO0_BASE+GPIOx_IS2L)
  315 +#define GPIO0_IS2H (GPIO0_BASE+GPIOx_IS2H)
  316 +#define GPIO0_IS3L (GPIO0_BASE+GPIOx_IS3L)
  317 +#define GPIO0_IS3H (GPIO0_BASE+GPIOx_IS3L)
  318 +
  319 +/* GPIO1 */
  320 +#define GPIO1_IS1L (GPIO1_BASE+GPIOx_IS1L)
  321 +#define GPIO1_IS1H (GPIO1_BASE+GPIOx_IS1H)
  322 +#define GPIO1_IS2L (GPIO1_BASE+GPIOx_IS2L)
  323 +#define GPIO1_IS2H (GPIO1_BASE+GPIOx_IS2H)
  324 +#define GPIO1_IS3L (GPIO1_BASE+GPIOx_IS3L)
  325 +#define GPIO1_IS3H (GPIO1_BASE+GPIOx_IS3L)
  326 +
  327 +#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */
  328 +#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */
  329 +#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */
  330 +#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */
  331 +#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
  332 +
  333 +
  334 +/*----------------------------------------------------------------------------+
  335 + | Declare Configuration values
  336 + +----------------------------------------------------------------------------*/
  337 +typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
  338 +typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
  339 +
  340 +typedef struct { unsigned long add; /* gpio core base address */
  341 + gpio_driver_t in_out; /* Driver Setting */
  342 + gpio_select_t alt_nb; /* Selected Alternate */
  343 +} gpio_param_s;
  344 +
  345 +/*----------------------------------------------------------------------------+
  346 + | XX XX
  347 + |
  348 + | XXXXXX XXX XX XXX XXX
  349 + | XX XX X XX XX XX
  350 + | XX XX X XX XX XX
  351 + | XX XX XX XX XX
  352 + | XXXXXX XXX XXX XXXX XXXX
  353 + +----------------------------------------------------------------------------*/
  354 +/*----------------------------------------------------------------------------+
  355 + | Defines
  356 + +----------------------------------------------------------------------------*/
  357 +typedef enum zmii_config { ZMII_CONFIGURATION_UNKNOWN,
  358 + ZMII_CONFIGURATION_IS_MII,
  359 + ZMII_CONFIGURATION_IS_RMII,
  360 + ZMII_CONFIGURATION_IS_SMII
  361 +} zmii_config_t;
  362 +
  363 +/*----------------------------------------------------------------------------+
  364 + | Declare Configuration values
  365 + +----------------------------------------------------------------------------*/
  366 +typedef enum uart_config_nb { L1, L2, L3, L4 } uart_config_nb_t;
  367 +typedef enum core_selection { CORE_NOT_SELECTED, CORE_SELECTED} core_selection_t;
  368 +typedef enum config_list { IIC_CORE,
  369 + SCP_CORE,
  370 + DMA_CHANNEL_AB,
  371 + UIC_4_9,
  372 + USB2_HOST,
  373 + DMA_CHANNEL_CD,
  374 + USB2_DEVICE,
  375 + PACKET_REJ_FUNC_AVAIL,
  376 + USB1_DEVICE,
  377 + EBC_MASTER,
  378 + NAND_FLASH,
  379 + UART_CORE0,
  380 + UART_CORE1,
  381 + UART_CORE2,
  382 + UART_CORE3,
  383 + MII_SEL,
  384 + RMII_SEL,
  385 + SMII_SEL,
  386 + PACKET_REJ_FUNC_EN,
  387 + UIC_0_3,
  388 + USB1_HOST,
  389 + PCI_PATCH,
  390 + CORE_NB
  391 +} core_list_t;
  392 +
  393 +typedef enum block3_value { B3_V1, B3_V2, B3_V3, B3_V4, B3_V5,
  394 + B3_V6, B3_V7, B3_V8, B3_V9, B3_V10,
  395 + B3_V11, B3_V12, B3_V13, B3_V14, B3_V15,
  396 + B3_V16, B3_VALUE_UNKNOWN
  397 +} block3_value_t;
  398 +
  399 +typedef enum config_validity { CONFIG_IS_VALID,
  400 + CONFIG_IS_INVALID
  401 +} config_validity_t;
board/amcc/bamboo/config.mk
Diff comments   View file @ 17f50f2
... ... @@ -21,17 +21,7 @@
21 21 # MA 02111-1307 USA
22 22 #
23 23  
24   -#
25   -# esd ADCIOP boards
26   -#
27   -
28   -#TEXT_BASE = 0x00001000
29   -
30   -ifeq ($(ramsym),1)
31   -TEXT_BASE = 0xFBD00000
32   -else
33 24 TEXT_BASE = 0xFFF80000
34   -endif
35 25  
36 26 PLATFORM_CPPFLAGS += -DCONFIG_440=1
37 27  
board/amcc/bamboo/flash.c
Diff comments   View file @ 17f50f2
  1 +/*
  2 + * (C) Copyright 2004-2005
  3 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 + *
  5 + * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
  6 + * Add support for Am29F016D and dynamic switch setting.
  7 + *
  8 + * See file CREDITS for list of people who contributed to this
  9 + * project.
  10 + *
  11 + * This program is free software; you can redistribute it and/or
  12 + * modify it under the terms of the GNU General Public License as
  13 + * published by the Free Software Foundation; either version 2 of
  14 + * the License, or (at your option) any later version.
  15 + *
  16 + * This program is distributed in the hope that it will be useful,
  17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19 + * GNU General Public License for more details.
  20 + *
  21 + * You should have received a copy of the GNU General Public License
  22 + * along with this program; if not, write to the Free Software
  23 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 + * MA 02111-1307 USA
  25 + */
  26 +
  27 +/*
  28 + * Modified 4/5/2001
  29 + * Wait for completion of each sector erase command issued
  30 + * 4/5/2001
  31 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
  32 + */
  33 +
  34 +#include <common.h>
  35 +#include <ppc4xx.h>
  36 +#include <asm/processor.h>
  37 +#include <ppc440.h>
  38 +#include "bamboo.h"
  39 +
  40 +#undef DEBUG
  41 +
  42 +#ifdef DEBUG
  43 +#define DEBUGF(x...) printf(x)
  44 +#else
  45 +#define DEBUGF(x...)
  46 +#endif /* DEBUG */
  47 +
  48 +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
  49 +
  50 +/*
  51 + * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0
  52 + */
  53 +static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
  54 + {0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
  55 + {0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66 */
  56 + {0x00000000, 0x00000000, 0x00000000}, /* 2:boot from nand flash */
  57 + {0x87800000, 0x87880000, 0xFF800001}, /* 3:boot from big flash 33*/
  58 + {0x87800000, 0x87880000, 0xFF800001}, /* 4:boot from big flash 66*/
  59 + {0x00000000, 0x00000000, 0x00000000}, /* 5:boot from */
  60 + {0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66 */
  61 + {0x00000000, 0x00000000, 0x00000000}, /* 7:boot from */
  62 +};
  63 +
  64 +/*
  65 + * include common flash code (for amcc boards)
  66 + */
  67 +#include "../common/flash.c"
  68 +
  69 +/*-----------------------------------------------------------------------
  70 + * Functions
  71 + */
  72 +static ulong flash_get_size(vu_long * addr, flash_info_t * info);
  73 +static int write_word(flash_info_t * info, ulong dest, ulong data);
  74 +
  75 +/*-----------------------------------------------------------------------
  76 + */
  77 +
  78 +unsigned long flash_init(void)
  79 +{
  80 + unsigned long total_b = 0;
  81 + unsigned long size_b[CFG_MAX_FLASH_BANKS];
  82 + unsigned short index = 0;
  83 + int i;
  84 + unsigned long val;
  85 + unsigned long ebc_boot_size;
  86 + unsigned long boot_selection;
  87 +
  88 + mfsdr(sdr_pstrp0, val);
  89 + index = (val & SDR0_PSTRP0_BOOTSTRAP_MASK) >> 29;
  90 +
  91 + if ((index == 5) || (index == 7)) {
  92 + /*
  93 + * Boot Settings in IIC EEprom address 0xA8 or 0xA4
  94 + * Read Serial Device Strap Register1 in PPC440EP
  95 + */
  96 + mfsdr(sdr_sdstp1, val);
  97 + boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK;
  98 + ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK;
  99 +
  100 + switch(boot_selection) {
  101 + case SDR0_SDSTP1_BOOT_SEL_EBC:
  102 + switch(ebc_boot_size) {
  103 + case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
  104 + index = 3;
  105 + break;
  106 + case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
  107 + index = 0;
  108 + break;
  109 + }
  110 + break;
  111 +
  112 + case SDR0_SDSTP1_BOOT_SEL_PCI:
  113 + index = 1;
  114 + break;
  115 +
  116 + case SDR0_SDSTP1_BOOT_SEL_NDFC:
  117 + index = 2;
  118 + break;
  119 + }
  120 + }
  121 +
  122 + DEBUGF("\n");
  123 + DEBUGF("FLASH: Index: %d\n", index);
  124 +
  125 + /* Init: no FLASHes known */
  126 + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
  127 + flash_info[i].flash_id = FLASH_UNKNOWN;
  128 + flash_info[i].sector_count = -1;
  129 + flash_info[i].size = 0;
  130 +
  131 + /* check whether the address is 0 */
  132 + if (flash_addr_table[index][i] == 0) {
  133 + continue;
  134 + }
  135 +
  136 + /* call flash_get_size() to initialize sector address */
  137 + size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
  138 + &flash_info[i]);
  139 + flash_info[i].size = size_b[i];
  140 + if (flash_info[i].flash_id == FLASH_UNKNOWN) {
  141 + printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
  142 + i, size_b[i], size_b[i] << 20);
  143 + flash_info[i].sector_count = -1;
  144 + flash_info[i].size = 0;
  145 + }
  146 +
  147 + /* Monitor protection ON by default */
  148 + (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
  149 + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
  150 + &flash_info[i]);
  151 +#if defined(CFG_ENV_IS_IN_FLASH)
  152 + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
  153 + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
  154 + &flash_info[i]);
  155 +#if defined(CFG_ENV_IS_IN_FLASH) && defined(CFG_ENV_ADDR_REDUND)
  156 + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
  157 + CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
  158 + &flash_info[i]);
  159 +#endif
  160 +#endif
  161 +
  162 + total_b += flash_info[i].size;
  163 + }
  164 +
  165 + return total_b;
  166 +}
board/amcc/bamboo/init.S
Diff comments   View file @ 17f50f2
... ... @@ -93,7 +93,7 @@
93 93 tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
94 94 tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
95 95 tlbentry( CFG_PCI_BASE, SZ_256M, 0xE0000000, 0, AC_R|AC_W|SA_G|SA_I )
96   - tlbentry( CFG_NVRAM_BASE_ADDR, SZ_16K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
  96 + tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, 0x80000000, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
97 97  
98 98 /* PCI */
99 99 tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
board/amcc/bamboo/u-boot.lds
Diff comments   View file @ 17f50f2
... ... @@ -74,7 +74,7 @@
74 74 cpu/ppc4xx/serial.o (.text)
75 75 cpu/ppc4xx/cpu_init.o (.text)
76 76 cpu/ppc4xx/speed.o (.text)
77   - cpu/ppc4xx/405gp_enet.o (.text)
  77 + cpu/ppc4xx/440gx_enet.o (.text)
78 78 common/dlmalloc.o (.text)
79 79 lib_generic/crc32.o (.text)
80 80 lib_ppc/extable.o (.text)
... ... @@ -150,6 +150,9 @@
150 150 *(.bss)
151 151 *(COMMON)
152 152 }
  153 +
  154 + ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
  155 +
153 156 _end = . ;
154 157 PROVIDE (end = .);
155 158 }
board/amcc/common/flash.c
Diff comments   View file @ 17f50f2
... ... @@ -41,6 +41,14 @@
41 41 * Functions
42 42 */
43 43 static int write_word(flash_info_t * info, ulong dest, ulong data);
  44 +#ifdef CFG_FLASH_2ND_16BIT_DEV
  45 +static int write_word_1(flash_info_t * info, ulong dest, ulong data);
  46 +static int write_word_2(flash_info_t * info, ulong dest, ulong data);
  47 +static int flash_erase_1(flash_info_t * info, int s_first, int s_last);
  48 +static int flash_erase_2(flash_info_t * info, int s_first, int s_last);
  49 +static ulong flash_get_size_1(vu_long * addr, flash_info_t * info);
  50 +static ulong flash_get_size_2(vu_long * addr, flash_info_t * info);
  51 +#endif
44 52  
45 53 void flash_print_info(flash_info_t * info)
46 54 {
... ... @@ -113,6 +121,9 @@
113 121 case FLASH_SST160A:
114 122 printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
115 123 break;
  124 + case FLASH_STMW320DT:
  125 + printf ("M29W320DT (32 M, top sector)\n");
  126 + break;
116 127 default:
117 128 printf("Unknown Chip Type\n");
118 129 break;
119 130  
... ... @@ -154,8 +165,22 @@
154 165 /*
155 166 * The following code cannot be run from FLASH!
156 167 */
  168 +#ifdef CFG_FLASH_2ND_16BIT_DEV
157 169 static ulong flash_get_size(vu_long * addr, flash_info_t * info)
158 170 {
  171 + /* bit 0 used for big flash marking */
  172 + if ((ulong)addr & 0x1) {
  173 + return flash_get_size_2((vu_long *)((ulong)addr & 0xfffffffe), info);
  174 + } else {
  175 + return flash_get_size_1(addr, info);
  176 + }
  177 +}
  178 +
  179 +static ulong flash_get_size_1(vu_long * addr, flash_info_t * info)
  180 +#else
  181 +static ulong flash_get_size(vu_long * addr, flash_info_t * info)
  182 +#endif
  183 +{
159 184 short i;
160 185 CFG_FLASH_WORD_SIZE value;
161 186 ulong base = (ulong) addr;
... ... @@ -193,7 +218,6 @@
193 218 }
194 219  
195 220 value = addr2[1]; /* device ID */
196   -
197 221 DEBUGF("\nFLASH DEVICEID: %x\n", value);
198 222  
199 223 switch (value) {
... ... @@ -323,7 +347,7 @@
323 347 return (info->size);
324 348 }
325 349  
326   -int wait_for_DQ7(flash_info_t * info, int sect)
  350 +static int wait_for_DQ7_1(flash_info_t * info, int sect)
327 351 {
328 352 ulong start, now, last;
329 353 volatile CFG_FLASH_WORD_SIZE *addr =
330 354  
... ... @@ -346,8 +370,23 @@
346 370 return 0;
347 371 }
348 372  
  373 +#ifdef CFG_FLASH_2ND_16BIT_DEV
349 374 int flash_erase(flash_info_t * info, int s_first, int s_last)
350 375 {
  376 + if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
  377 + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
  378 + ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
  379 + return flash_erase_2(info, s_first, s_last);
  380 + } else {
  381 + return flash_erase_1(info, s_first, s_last);
  382 + }
  383 +}
  384 +
  385 +static int flash_erase_1(flash_info_t * info, int s_first, int s_last)
  386 +#else
  387 +int flash_erase(flash_info_t * info, int s_first, int s_last)
  388 +#endif
  389 +{
351 390 volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
352 391 volatile CFG_FLASH_WORD_SIZE *addr2;
353 392 int flag, prot, sect, l_sect;
... ... @@ -416,7 +455,7 @@
416 455 * timeout. This has been seen to fail, especially
417 456 * if printf()s are included (for debug)!!
418 457 */
419   - wait_for_DQ7(info, sect);
  458 + wait_for_DQ7_1(info, sect);
420 459 }
421 460 }
422 461  
423 462  
424 463  
... ... @@ -506,13 +545,28 @@
506 545 }
507 546  
508 547 /*-----------------------------------------------------------------------
509   - * Write a word to Flash, returns:
  548 + * Copy memory to flash, returns:
510 549 * 0 - OK
511 550 * 1 - write timeout
512 551 * 2 - Flash not erased
513 552 */
  553 +#ifdef CFG_FLASH_2ND_16BIT_DEV
514 554 static int write_word(flash_info_t * info, ulong dest, ulong data)
515 555 {
  556 + if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
  557 + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
  558 + ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
  559 + return write_word_2(info, dest, data);
  560 + } else {
  561 + return write_word_1(info, dest, data);
  562 + }
  563 +}
  564 +
  565 +static int write_word_1(flash_info_t * info, ulong dest, ulong data)
  566 +#else
  567 +static int write_word(flash_info_t * info, ulong dest, ulong data)
  568 +#endif
  569 +{
516 570 volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
517 571 volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
518 572 volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
... ... @@ -553,4 +607,312 @@
553 607  
554 608 return (0);
555 609 }
  610 +
  611 +#ifdef CFG_FLASH_2ND_16BIT_DEV
  612 +
  613 +#undef CFG_FLASH_WORD_SIZE
  614 +#define CFG_FLASH_WORD_SIZE unsigned short
  615 +
  616 +/*
  617 + * The following code cannot be run from FLASH!
  618 + */
  619 +static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
  620 +{
  621 + short i;
  622 + int n;
  623 + CFG_FLASH_WORD_SIZE value;
  624 + ulong base = (ulong) addr;
  625 + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
  626 +
  627 + DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
  628 +
  629 + /* Write auto select command: read Manufacturer ID */
  630 + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
  631 + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
  632 + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
  633 + udelay(1000);
  634 +
  635 + value = addr2[0];
  636 + DEBUGF("FLASH MANUFACT: %x\n", value);
  637 +
  638 + switch (value) {
  639 + case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
  640 + info->flash_id = FLASH_MAN_AMD;
  641 + break;
  642 + case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
  643 + info->flash_id = FLASH_MAN_FUJ;
  644 + break;
  645 + case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
  646 + info->flash_id = FLASH_MAN_SST;
  647 + break;
  648 + case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
  649 + info->flash_id = FLASH_MAN_STM;
  650 + break;
  651 + default:
  652 + info->flash_id = FLASH_UNKNOWN;
  653 + info->sector_count = 0;
  654 + info->size = 0;
  655 + return (0); /* no or unknown flash */
  656 + }
  657 +
  658 + value = addr2[1]; /* device ID */
  659 +
  660 + DEBUGF("\nFLASH DEVICEID: %x\n", value);
  661 +
  662 + switch (value) {
  663 +
  664 + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
  665 + info->flash_id += FLASH_AM320T;
  666 + info->sector_count = 71;
  667 + info->size = 0x00400000; break; /* => 4 MB */
  668 +
  669 + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
  670 + info->flash_id += FLASH_AM320B;
  671 + info->sector_count = 71;
  672 + info->size = 0x00400000; break; /* => 4 MB */
  673 +
  674 + case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT:
  675 + info->flash_id += FLASH_STMW320DT;
  676 + info->sector_count = 67;
  677 + info->size = 0x00400000; break; /* => 4 MB */
  678 +
  679 + default:
  680 + info->flash_id = FLASH_UNKNOWN;
  681 + return (0); /* => no or unknown flash */
  682 + }
  683 +
  684 + /* set up sector start address table */
  685 + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
  686 + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
  687 + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
  688 + for (i = 0; i < info->sector_count; i++)
  689 + info->start[i] = base + (i * 0x00010000);
  690 + } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
  691 + /* set sector offsets for top boot block type */
  692 + base += info->size;
  693 + i = info->sector_count;
  694 + /* 1 x 16k boot sector */
  695 + base -= 16 << 10;
  696 + --i;
  697 + info->start[i] = base;
  698 + /* 2 x 8k boot sectors */
  699 + for (n=0; n<2; ++n) {
  700 + base -= 8 << 10;
  701 + --i;
  702 + info->start[i] = base;
  703 + }
  704 + /* 1 x 32k boot sector */
  705 + base -= 32 << 10;
  706 + --i;
  707 + info->start[i] = base;
  708 +
  709 + while (i > 0) { /* 64k regular sectors */
  710 + base -= 64 << 10;
  711 + --i;
  712 + info->start[i] = base;
  713 + }
  714 + } else {
  715 + if (info->flash_id & FLASH_BTYPE) {
  716 + /* set sector offsets for bottom boot block type */
  717 + info->start[0] = base + 0x00000000;
  718 + info->start[1] = base + 0x00004000;
  719 + info->start[2] = base + 0x00006000;
  720 + info->start[3] = base + 0x00008000;
  721 + for (i = 4; i < info->sector_count; i++) {
  722 + info->start[i] =
  723 + base + (i * 0x00010000) - 0x00030000;
  724 + }
  725 + } else {
  726 + /* set sector offsets for top boot block type */
  727 + i = info->sector_count - 1;
  728 + info->start[i--] = base + info->size - 0x00004000;
  729 + info->start[i--] = base + info->size - 0x00006000;
  730 + info->start[i--] = base + info->size - 0x00008000;
  731 + for (; i >= 0; i--) {
  732 + info->start[i] = base + i * 0x00010000;
  733 + }
  734 + }
  735 + }
  736 +
  737 + /* check for protected sectors */
  738 + for (i = 0; i < info->sector_count; i++) {
  739 + /* read sector protection at sector address, (A7 .. A0) = 0x02 */
  740 + /* D0 = 1 if protected */
  741 + addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
  742 +
  743 + /* For AMD29033C flash we need to resend the command of *
  744 + * reading flash protection for upper 8 Mb of flash */
  745 + if (i == 32) {
  746 + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
  747 + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
  748 + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
  749 + }
  750 +
  751 + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
  752 + info->protect[i] = 0;
  753 + else
  754 + info->protect[i] = addr2[2] & 1;
  755 + }
  756 +
  757 + /* issue bank reset to return to read mode */
  758 + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
  759 +
  760 + return (info->size);
  761 +}
  762 +
  763 +static int wait_for_DQ7_2(flash_info_t * info, int sect)
  764 +{
  765 + ulong start, now, last;
  766 + volatile CFG_FLASH_WORD_SIZE *addr =
  767 + (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
  768 +
  769 + start = get_timer(0);
  770 + last = start;
  771 + while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
  772 + (CFG_FLASH_WORD_SIZE) 0x00800080) {
  773 + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
  774 + printf("Timeout\n");
  775 + return -1;
  776 + }
  777 + /* show that we're waiting */
  778 + if ((now - last) > 1000) { /* every second */
  779 + putc('.');
  780 + last = now;
  781 + }
  782 + }
  783 + return 0;
  784 +}
  785 +
  786 +static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
  787 +{
  788 + volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
  789 + volatile CFG_FLASH_WORD_SIZE *addr2;
  790 + int flag, prot, sect, l_sect;
  791 + int i;
  792 +
  793 + if ((s_first < 0) || (s_first > s_last)) {
  794 + if (info->flash_id == FLASH_UNKNOWN) {
  795 + printf("- missing\n");
  796 + } else {
  797 + printf("- no sectors to erase\n");
  798 + }
  799 + return 1;
  800 + }
  801 +
  802 + if (info->flash_id == FLASH_UNKNOWN) {
  803 + printf("Can't erase unknown flash type - aborted\n");
  804 + return 1;
  805 + }
  806 +
  807 + prot = 0;
  808 + for (sect = s_first; sect <= s_last; ++sect) {
  809 + if (info->protect[sect]) {
  810 + prot++;
  811 + }
  812 + }
  813 +
  814 + if (prot) {
  815 + printf("- Warning: %d protected sectors will not be erased!\n",
  816 + prot);
  817 + } else {
  818 + printf("\n");
  819 + }
  820 +
  821 + l_sect = -1;
  822 +
  823 + /* Disable interrupts which might cause a timeout here */
  824 + flag = disable_interrupts();
  825 +
  826 + /* Start erase on unprotected sectors */
  827 + for (sect = s_first; sect <= s_last; sect++) {
  828 + if (info->protect[sect] == 0) { /* not protected */
  829 + addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
  830 +
  831 + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
  832 + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
  833 + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
  834 + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
  835 + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
  836 + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
  837 + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */
  838 + for (i = 0; i < 50; i++)
  839 + udelay(1000); /* wait 1 ms */
  840 + } else {
  841 + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
  842 + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
  843 + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
  844 + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
  845 + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
  846 + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
  847 + }
  848 + l_sect = sect;
  849 + /*
  850 + * Wait for each sector to complete, it's more
  851 + * reliable. According to AMD Spec, you must
  852 + * issue all erase commands within a specified
  853 + * timeout. This has been seen to fail, especially
  854 + * if printf()s are included (for debug)!!
  855 + */
  856 + wait_for_DQ7_2(info, sect);
  857 + }
  858 + }
  859 +
  860 + /* re-enable interrupts if necessary */
  861 + if (flag)
  862 + enable_interrupts();
  863 +
  864 + /* wait at least 80us - let's wait 1 ms */
  865 + udelay(1000);
  866 +
  867 + /* reset to read mode */
  868 + addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
  869 + addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
  870 +
  871 + printf(" done\n");
  872 + return 0;
  873 +}
  874 +
  875 +static int write_word_2(flash_info_t * info, ulong dest, ulong data)
  876 +{
  877 + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
  878 + volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
  879 + volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
  880 + ulong start;
  881 + int i;
  882 +
  883 + /* Check if Flash is (sufficiently) erased */
  884 + if ((*((vu_long *)dest) & data) != data) {
  885 + return (2);
  886 + }
  887 +
  888 + for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
  889 + int flag;
  890 +
  891 + /* Disable interrupts which might cause a timeout here */
  892 + flag = disable_interrupts();
  893 +
  894 + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
  895 + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
  896 + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
  897 +
  898 + dest2[i] = data2[i];
  899 +
  900 + /* re-enable interrupts if necessary */
  901 + if (flag)
  902 + enable_interrupts();
  903 +
  904 + /* data polling for D7 */
  905 + start = get_timer(0);
  906 + while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
  907 + (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
  908 +
  909 + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
  910 + return (1);
  911 + }
  912 + }
  913 + }
  914 +
  915 + return (0);
  916 +}
  917 +#endif /* CFG_FLASH_2ND_16BIT_DEV */
cpu/ppc4xx/405gp_enet.c
Diff comments   View file @ 17f50f2
... ... @@ -166,7 +166,6 @@
166 166 failsafe--;
167 167 if (failsafe == 0)
168 168 break;
169   -
170 169 }
171 170  
172 171 /* EMAC RESET */
173 172  
... ... @@ -223,18 +222,19 @@
223 222 #endif
224 223  
225 224 /* MAL RESET */
226   - mtdcr (malmcr, MAL_CR_MMSR);
227   - /* wait for reset */
228   - while (mfdcr (malmcr) & MAL_CR_MMSR) {
229   - };
  225 + mtdcr (malmcr, MAL_CR_MMSR);
  226 + /* wait for reset */
  227 + while (mfdcr (malmcr) & MAL_CR_MMSR) {
  228 + };
  229 +
230 230 #if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
231 231 out32 (ZMII_FER, 0);
232 232 udelay(100);
233 233 /* set RII mode */
234 234 out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
235 235 #elif defined(CONFIG_440)
236   - /* set RMII mode */
237   - out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
  236 + /* set RMII mode */
  237 + out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
238 238 #endif /* CONFIG_440 */
239 239  
240 240 /* MAL Channel RESET */
241 241  
... ... @@ -324,14 +324,11 @@
324 324 (int) speed, (duplex == HALF) ? "HALF" : "FULL");
325 325 }
326 326  
327   -#if defined(CONFIG_440)
328   - /* Errata 1.12: MAL_1 -- Disable MAL bursting */
329   - if( get_pvr() == PVR_440GP_RB)
330   - mtdcr (malmcr, MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
331   - else
332   -#else
333 327 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
334   -#endif
  328 + /* Errata 1.12: MAL_1 -- Disable MAL bursting */
  329 + if (get_pvr() == PVR_440GP_RB) {
  330 + mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
  331 + }
335 332  
336 333 /* Free "old" buffers */
337 334 if (hw_p->alloc_tx_buf)
... ... @@ -418,6 +415,7 @@
418 415 reg |= dev->enetaddr[5];
419 416  
420 417 out32 (EMAC_IAL + hw_p->hw_addr, reg);
  418 +
421 419 switch (devnum) {
422 420 #if defined(CONFIG_NET_MULTI)
423 421 case 1:
... ... @@ -497,7 +495,6 @@
497 495 /* 405s have a 16 byte burst length */
498 496 out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
499 497 #endif
500   -
501 498  
502 499 /* Frame gap set */
503 500 out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
cpu/ppc4xx/440gx_enet.c
Diff comments   View file @ 17f50f2
... ... @@ -391,6 +391,7 @@
391 391 failsafe--;
392 392 }
393 393  
  394 +#if defined(CONFIG_440_GX)
394 395 /* Whack the M1 register */
395 396 mode_reg = 0x0;
396 397 mode_reg &= ~0x00000038;
397 398  
... ... @@ -405,8 +406,8 @@
405 406 mode_reg |= EMAC_M1_OBCI_GT100;
406 407  
407 408 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
  409 +#endif /* defined(CONFIG_440_GX) */
408 410  
409   -
410 411 /* wait for PHY to complete auto negotiation */
411 412 reg_short = 0;
412 413 #ifndef CONFIG_CS8952_PHY
... ... @@ -432,6 +433,7 @@
432 433  
433 434 bis->bi_phynum[devnum] = reg;
434 435  
  436 +#ifndef CONFIG_NO_PHY_RESET
435 437 /*
436 438 * Reset the phy, only if its the first time through
437 439 * otherwise, just check the speeds & feeds
438 440  
439 441  
440 442  
... ... @@ -441,35 +443,36 @@
441 443  
442 444 #if defined(CONFIG_440_GX)
443 445 #if defined(CONFIG_CIS8201_PHY)
444   - /*
445   - * Cicada 8201 PHY needs to have an extended register whacked
446   - * for RGMII mode.
447   - */
448   - if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) {
449   - miiphy_write (reg, 23, 0x1200);
450 446 /*
451   - * Vitesse VSC8201/Cicada CIS8201 errata:
452   - * Interoperability problem with Intel 82547EI phys
453   - * This work around (provided by Vitesse) changes
454   - * the default timer convergence from 8ms to 12ms
  447 + * Cicada 8201 PHY needs to have an extended register whacked
  448 + * for RGMII mode.
455 449 */
456   - miiphy_write (reg, 0x1f, 0x2a30);
457   - miiphy_write (reg, 0x08, 0x0200);
458   - miiphy_write (reg, 0x1f, 0x52b5);
459   - miiphy_write (reg, 0x02, 0x0004);
460   - miiphy_write (reg, 0x01, 0x0671);
461   - miiphy_write (reg, 0x00, 0x8fae);
462   - miiphy_write (reg, 0x1f, 0x2a30);
463   - miiphy_write (reg, 0x08, 0x0000);
464   - miiphy_write (reg, 0x1f, 0x0000);
465   - /* end Vitesse/Cicada errata */
466   - }
  450 + if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) {
  451 + miiphy_write (reg, 23, 0x1200);
  452 + /*
  453 + * Vitesse VSC8201/Cicada CIS8201 errata:
  454 + * Interoperability problem with Intel 82547EI phys
  455 + * This work around (provided by Vitesse) changes
  456 + * the default timer convergence from 8ms to 12ms
  457 + */
  458 + miiphy_write (reg, 0x1f, 0x2a30);
  459 + miiphy_write (reg, 0x08, 0x0200);
  460 + miiphy_write (reg, 0x1f, 0x52b5);
  461 + miiphy_write (reg, 0x02, 0x0004);
  462 + miiphy_write (reg, 0x01, 0x0671);
  463 + miiphy_write (reg, 0x00, 0x8fae);
  464 + miiphy_write (reg, 0x1f, 0x2a30);
  465 + miiphy_write (reg, 0x08, 0x0000);
  466 + miiphy_write (reg, 0x1f, 0x0000);
  467 + /* end Vitesse/Cicada errata */
  468 + }
467 469 #endif
468 470 #endif
469 471 /* Start/Restart autonegotiation */
470 472 phy_setup_aneg (reg);
471 473 udelay (1000);
472 474 }
  475 +#endif /* CONFIG_NO_PHY_RESET */
473 476  
474 477 miiphy_read (reg, PHY_BMSR, &reg_short);
475 478  
476 479  
... ... @@ -538,14 +541,16 @@
538 541 }
539 542  
540 543 /* set the Mal configuration reg */
  544 +#if defined(CONFIG_440_GX)
  545 + mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
  546 + MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
  547 +#else
  548 + mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
541 549 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
542   - if (get_pvr () == PVR_440GP_RB)
543   - mtdcr (malmcr,
544   - MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
545   - else
546   - mtdcr (malmcr,
547   - MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
548   - MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
  550 + if (get_pvr() == PVR_440GP_RB) {
  551 + mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
  552 + }
  553 +#endif
549 554  
550 555 /* Free "old" buffers */
551 556 if (hw_p->alloc_tx_buf)
... ... @@ -152,7 +152,7 @@
152 152 #endif
153 153  
154 154 #if defined(CONFIG_440)
155   - puts ("AMCC PowerPC 440 ");
  155 + puts ("AMCC PowerPC 440");
156 156 switch(pvr) {
157 157 case PVR_440GP_RB:
158 158 puts("GP Rev. B");
... ... @@ -195,7 +195,7 @@
195 195 #endif
196 196  
197 197 default:
198   - printf ("UNKNOWN (PVR=%08x)", pvr);
  198 + printf (" UNKNOWN (PVR=%08x)", pvr);
199 199 break;
200 200 }
201 201 #endif
cpu/ppc4xx/spd_sdram.c
Diff comments   View file @ 17f50f2
... ... @@ -1590,7 +1590,6 @@
1590 1590 unsigned long num_dimm_banks)
1591 1591 {
1592 1592 unsigned long dimm_num;
1593   - unsigned long bxcr_num;
1594 1593 unsigned long bank_base_addr;
1595 1594 unsigned long bank_size_bytes;
1596 1595 unsigned long cr;
... ... @@ -1601,6 +1600,8 @@
1601 1600 unsigned char num_banks;
1602 1601 unsigned char bank_size_id;
1603 1602  
  1603 +#ifndef CONFIG_BAMBOO
  1604 + unsigned long bxcr_num;
1604 1605  
1605 1606 /*
1606 1607 * Set the BxCR regs. First, wipe out the bank config registers.
1607 1608  
1608 1609  
... ... @@ -1609,11 +1610,16 @@
1609 1610 mtdcr(memcfga, mem_b0cr + (bxcr_num << 2));
1610 1611 mtdcr(memcfgd, 0x00000000);
1611 1612 }
  1613 +#endif
1612 1614  
1613 1615 /*
1614 1616 * reset the bank_base address
1615 1617 */
  1618 +#ifndef CONFIG_BAMBOO
1616 1619 bank_base_addr = CFG_SDRAM_BASE;
  1620 +#else
  1621 + bank_base_addr = CFG_SDRAM_ONBOARD_SIZE;
  1622 +#endif
1617 1623  
1618 1624 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1619 1625 if (dimm_populated[dimm_num] == TRUE) {
1620 1626  
... ... @@ -1691,7 +1697,11 @@
1691 1697 +-----------------------------------------------------------------*/
1692 1698 if (dimm_num == 0) {
1693 1699 for (i = 0; i < num_banks; i++) {
  1700 +#ifndef CONFIG_BAMBOO
1694 1701 mtdcr(memcfga, mem_b0cr + (i << 2));
  1702 +#else
  1703 + mtdcr(memcfga, mem_b1cr + (i << 2));
  1704 +#endif
1695 1705 temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
1696 1706 SDRAM_BXCR_SDSZ_MASK |
1697 1707 SDRAM_BXCR_SDAM_MASK |
1698 1708  
... ... @@ -1703,7 +1713,11 @@
1703 1713 }
1704 1714 } else {
1705 1715 for (i = 0; i < num_banks; i++) {
  1716 +#ifndef CONFIG_BAMBOO
1706 1717 mtdcr(memcfga, mem_b2cr + (i << 2));
  1718 +#else
  1719 + mtdcr(memcfga, mem_b3cr + (i << 2));
  1720 +#endif
1707 1721 temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
1708 1722 SDRAM_BXCR_SDSZ_MASK |
1709 1723 SDRAM_BXCR_SDAM_MASK |
... ... @@ -379,11 +379,13 @@
379 379 li r0,0
380 380 #if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
381 381 /* Clear Dcache to use as RAM */
382   - lis r3,CFG_INIT_RAM_ADDR@h
383   - li r4,CFG_INIT_RAM_END@l
  382 + addis r3,r0,CFG_INIT_RAM_ADDR@h
  383 + ori r3,r3,CFG_INIT_RAM_ADDR@l
  384 + addis r4,r0,CFG_INIT_RAM_END@h
  385 + ori r4,r4,CFG_INIT_RAM_END@l
384 386 rlwinm. r5,r4,0,27,31
385 387 rlwinm r5,r4,27,5,31
386   - beq ..d_ran
  388 + beq ..d_ran
387 389 addi r5,r5,0x0001
388 390 ..d_ran:
389 391 mtctr r5
include/440gx_enet.h
Diff comments   View file @ 17f50f2
... ... @@ -318,6 +318,8 @@
318 318 #define EMAC_M0_RXE (0x08000000)
319 319 #define EMAC_M0_WKE (0x04000000)
320 320  
  321 +/* on 440GX EMAC_MR1 has a different layout! */
  322 +#if defined(CONFIG_440_GX)
321 323 /* MODE Reg 1 */
322 324 #define EMAC_M1_FDE (0x80000000)
323 325 #define EMAC_M1_ILE (0x40000000)
... ... @@ -347,6 +349,31 @@
347 349 #define EMAC_M1_OBCI_83 (0x00000010)
348 350 #define EMAC_M1_OBCI_66 (0x00000008)
349 351 #define EMAC_M1_RSVD1 (0x00000007)
  352 +#else /* defined(CONFIG_440_GX) */
  353 +/* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */
  354 +#define EMAC_M1_FDE 0x80000000
  355 +#define EMAC_M1_ILE 0x40000000
  356 +#define EMAC_M1_VLE 0x20000000
  357 +#define EMAC_M1_EIFC 0x10000000
  358 +#define EMAC_M1_APP 0x08000000
  359 +#define EMAC_M1_AEMI 0x02000000
  360 +#define EMAC_M1_IST 0x01000000
  361 +#define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */
  362 +#define EMAC_M1_MF_100MBPS 0x00400000
  363 +#define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */
  364 +#define EMAC_M1_RFS_2K 0x00200000
  365 +#define EMAC_M1_RFS_1K 0x00100000
  366 +#define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */
  367 +#define EMAC_M1_TX_FIFO_1K 0x00040000
  368 +#define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
  369 +#define EMAC_M1_TR0_MULTI 0x00008000
  370 +#define EMAC_M1_TR1_DEPEND 0x00004000
  371 +#define EMAC_M1_TR1_MULTI 0x00002000
  372 +#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
  373 +#define EMAC_M1_JUMBO_ENABLE 0x00001000
  374 +#endif /* defined(CONFIG_440_EP) || defined(CONFIG_440_GR) */
  375 +#endif /* defined(CONFIG_440_GX) */
  376 +
350 377 /* Transmit Mode Register 0 */
351 378 #define EMAC_TXM0_GNP0 (0x80000000)
352 379 #define EMAC_TXM0_GNP1 (0x40000000)
include/configs/bamboo.h
Diff comments   View file @ 17f50f2
... ... @@ -30,59 +30,52 @@
30 30 /*-----------------------------------------------------------------------
31 31 * High Level Configuration Options
32 32 *----------------------------------------------------------------------*/
33   -#define CONFIG_BAMBOO 1 /* Board is BAMBOO */
34   -#define CONFIG_440_EP 1 /* Specific PPC440EP support */
  33 +#define CONFIG_BAMBOO 1 /* Board is BAMBOO */
  34 +#define CONFIG_440_EP 1 /* Specific PPC440EP support */
35 35  
36   -#define CONFIG_4xx 1 /* ... PPC4xx family */
37   -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
38   -#undef CFG_DRAM_TEST /* disable - takes long time! */
39   -/*#define CONFIG_SYS_CLK_FREQ 66666666 /X* external freq to pll */
  36 +#define CONFIG_4xx 1 /* ... PPC4xx family */
  37 +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
40 38 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
41 39  
42 40 /*-----------------------------------------------------------------------
43 41 * Base addresses -- Note these are effective addresses where the
44 42 * actual resources get mapped (not physical addresses)
45 43 *----------------------------------------------------------------------*/
46   -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
47   -#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH */
48   -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
49   -#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory */
50   -#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
51   -#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
52   -#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
  44 +#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
  45 +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
  46 +#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
  47 +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
  48 +#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */
  49 +#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
  50 +#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
  51 +#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
  52 +#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
53 53  
54   -
55 54 /*Don't change either of these*/
56   -#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
57   -#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs */
  55 +#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/
  56 +#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/
58 57 /*Don't change either of these*/
59 58  
60   -#define CFG_USB_DEVICE 0x50000000
61   -#define CFG_NVRAM_BASE_ADDR 0x80000000
62   -#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000)
  59 +#define CFG_USB_DEVICE 0x50000000
  60 +#define CFG_NVRAM_BASE_ADDR 0x80000000
  61 +#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000)
63 62  
64 63 /*-----------------------------------------------------------------------
65 64 * Initial RAM & stack pointer (placed in SDRAM)
66 65 *----------------------------------------------------------------------*/
67   -#define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */
68   -#define CFG_INIT_RAM_END 0x2000
69   -#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
  66 +#define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */
  67 +#define CFG_INIT_RAM_END 0x1000
  68 +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
70 69 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
71 70 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
72 71  
73   -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
74   -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
75   -#define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */
76   -/*#define CFG_SDRAM_BANKS (2) */
77   -#define CFG_SDRAM_BANKS (1)
78   -
79 72 /*-----------------------------------------------------------------------
80 73 * Serial Port
81 74 *----------------------------------------------------------------------*/
82 75 #define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
83 76 #define CONFIG_BAUDRATE 115200
84   -#define CONFIG_SERIAL_MULTI 1
85   -/*define this if you want console on UART1*/
  77 +#define CONFIG_SERIAL_MULTI 1
  78 +/* define this if you want console on UART1 */
86 79 #undef CONFIG_UART1_CONSOLE
87 80  
88 81 #define CFG_BAUDRATE_TABLE \
89 82  
90 83  
91 84  
92 85  
93 86  
94 87  
95 88  
96 89  
... ... @@ -95,37 +88,57 @@
95 88 * The DS1558 code assumes this condition
96 89 *
97 90 *----------------------------------------------------------------------*/
98   -#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
99   -#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
  91 +#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
  92 +#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
100 93  
101 94 /*-----------------------------------------------------------------------
  95 + * Environment
  96 + *----------------------------------------------------------------------*/
  97 +/*
  98 + * Define here the location of the environment variables (FLASH or EEPROM).
  99 + * Note: DENX encourages to use redundant environment in FLASH.
  100 + */
  101 +#if 1
  102 +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
  103 +#else
  104 +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
  105 +#endif
  106 +
  107 +/*-----------------------------------------------------------------------
102 108 * FLASH related
103 109 *----------------------------------------------------------------------*/
104   -#if 0 /* test-only */
105   -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
  110 +#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
106 111 #define CFG_MAX_FLASH_SECT 256 /* sectors per device */
107 112  
108 113 #undef CFG_FLASH_CHECKSUM
109 114 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
110   -#define CFG_FLASH_WRITE_TOUT 120000 /* Timeout for Flash Write (in ms) */
111   -#else
112   -#define CFG_FLASH_CFI /* The flash is CFI compatible */
113   -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
114   -#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
  115 +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
115 116  
116   -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
117   -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  117 +#define CFG_FLASH_ADDR0 0x555
  118 +#define CFG_FLASH_ADDR1 0x2aa
  119 +#define CFG_FLASH_WORD_SIZE unsigned char
118 120  
119   -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
120   -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  121 +#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
  122 +#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
121 123  
122   -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
  124 +#ifdef CFG_ENV_IS_IN_FLASH
  125 +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
  126 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
  127 +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
  128 +
  129 +#if 0 /* test-only */
  130 +/* Address and size of Redundant Environment Sector */
  131 +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
  132 +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
123 133 #endif
  134 +#endif /* CFG_ENV_IS_IN_FLASH */
124 135  
125 136 /*-----------------------------------------------------------------------
126 137 * DDR SDRAM
127   - *----------------------------------------------------------------------*/
128   -#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
  138 + *----------------------------------------------------------------------------- */
  139 +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
  140 +#define SPD_EEPROM_ADDRESS {0x50,0x51} /* SPD i2c spd addresses */
  141 +#define CFG_SDRAM_ONBOARD_SIZE (64 << 20) /* Bamboo has onboard and DIMM-slots!*/
129 142  
130 143 /*-----------------------------------------------------------------------
131 144 * I2C
132 145  
133 146  
134 147  
135 148  
136 149  
137 150  
... ... @@ -135,44 +148,71 @@
135 148 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
136 149 #define CFG_I2C_SLAVE 0x7F
137 150  
138   -
139   -/*-----------------------------------------------------------------------
140   - * Environment
141   - *----------------------------------------------------------------------*/
142   -#undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/
143   -#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
144   -#define CFG_ENV_IS_IN_EEPROM 1
145   -
146   -/* Define to allow the user to overwrite serial and ethaddr */
147   -#define CONFIG_ENV_OVERWRITE
148   -
149 151 #define CFG_I2C_MULTI_EEPROMS
150   -#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
151   -#define CFG_ENV_OFFSET 0x0
152 152 #define CFG_I2C_EEPROM_ADDR (0xa8>>1)
153 153 #define CFG_I2C_EEPROM_ADDR_LEN 1
154 154 #define CFG_EEPROM_PAGE_WRITE_ENABLE
155 155 #define CFG_EEPROM_PAGE_WRITE_BITS 3
156 156 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
157 157  
158   -#define CONFIG_BOOTCOMMAND "bootm 0xfe000000" /* autoboot command */
159   -#define CONFIG_BOOTDELAY 3 /* disable autoboot */
  158 +#ifdef CFG_ENV_IS_IN_EEPROM
  159 +#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
  160 +#define CFG_ENV_OFFSET 0x0
  161 +#endif /* CFG_ENV_IS_IN_EEPROM */
160 162  
  163 +#define CONFIG_PREBOOT "echo;" \
  164 + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
  165 + "echo"
  166 +
  167 +#undef CONFIG_BOOTARGS
  168 +
  169 +#define CONFIG_EXTRA_ENV_SETTINGS \
  170 + "netdev=eth0\0" \
  171 + "hostname=bamboo\0" \
  172 + "nfsargs=setenv bootargs root=/dev/nfs rw " \
  173 + "nfsroot=$(serverip):$(rootpath)\0" \
  174 + "ramargs=setenv bootargs root=/dev/ram rw\0" \
  175 + "addip=setenv bootargs $(bootargs) " \
  176 + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
  177 + ":$(hostname):$(netdev):off panic=1\0" \
  178 + "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
  179 + "flash_nfs=run nfsargs addip addtty;" \
  180 + "bootm $(kernel_addr)\0" \
  181 + "flash_self=run ramargs addip addtty;" \
  182 + "bootm $(kernel_addr) $(ramdisk_addr)\0" \
  183 + "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
  184 + "bootm\0" \
  185 + "rootpath=/opt/eldk/ppc_4xx\0" \
  186 + "bootfile=/tftpboot/bamboo/uImage\0" \
  187 + "kernel_addr=fff00000\0" \
  188 + "ramdisk_addr=fff10000\0" \
  189 + "load=tftp 100000 /tftpboot/bamboo/u-boot.bin\0" \
  190 + "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \
  191 + "cp.b 100000 fff80000 80000;" \
  192 + "setenv filesize;saveenv\0" \
  193 + "upd=run load;run update\0" \
  194 + ""
  195 +#define CONFIG_BOOTCOMMAND "run flash_self"
  196 +
  197 +#if 0
  198 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
  199 +#else
  200 +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  201 +#endif
  202 +
  203 +#define CONFIG_BAUDRATE 115200
  204 +
161 205 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
162 206 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
163 207  
164 208 #define CONFIG_MII 1 /* MII PHY management */
165   -#define CONFIG_NET_MULTI 1 /* required for netconsole */
166   -#define CONFIG_PHY1_ADDR 3
  209 +#define CONFIG_NET_MULTI 1 /* required for netconsole */
  210 +#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
  211 +#define CONFIG_PHY1_ADDR 1
167 212 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
168   -#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
169   -#define CONFIG_NETMASK 255.255.255.0
170   -#define CONFIG_IPADDR 10.0.4.251
171   -#define CONFIG_ETHADDR 00:10:EC:00:12:34
172   -#define CONFIG_ETH1ADDR 00:10:EC:00:12:35
  213 +#define CONFIG_NO_PHY_RESET 1 /* no PHY reset on bamboo!!! */
173 214  
174   -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
175   -#define CONFIG_SERVERIP 10.0.4.115
  215 +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
176 216  
177 217 /* Partitions */
178 218 #define CONFIG_MAC_PARTITION
179 219  
... ... @@ -188,60 +228,24 @@
188 228 #define USB_2_0_DEVICE
189 229 #endif /*CONFIG_440_EP*/
190 230  
191   -#ifdef DEBUG
192   -#define CONFIG_PANIC_HANG
193   -#else
194   -#define CONFIG_HW_WATCHDOG /* watchdog */
195   -#endif
  231 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
  232 + CFG_CMD_ASKENV | \
  233 + CFG_CMD_DATE | \
  234 + CFG_CMD_DHCP | \
  235 + CFG_CMD_DIAG | \
  236 + CFG_CMD_ELF | \
  237 + CFG_CMD_I2C | \
  238 + CFG_CMD_IRQ | \
  239 + CFG_CMD_MII | \
  240 + CFG_CMD_NET | \
  241 + CFG_CMD_NFS | \
  242 + CFG_CMD_PCI | \
  243 + CFG_CMD_PING | \
  244 + CFG_CMD_REGINFO | \
  245 + CFG_CMD_SDRAM | \
  246 + CFG_CMD_USB | \
  247 + CFG_CMD_SNTP )
196 248  
197   -#ifdef CONFIG_440_EP
198   - /* Need to define POST */
199   -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
200   - CFG_CMD_DATE | \
201   - CFG_CMD_DHCP | \
202   - CFG_CMD_DIAG | \
203   - CFG_CMD_ECHO | \
204   - CFG_CMD_EEPROM | \
205   - CFG_CMD_ELF | \
206   - /* CFG_CMD_EXT2 |*/ \
207   - /* CFG_CMD_FAT |*/ \
208   - CFG_CMD_I2C | \
209   - /* CFG_CMD_IDE |*/ \
210   - CFG_CMD_IRQ | \
211   - /* CFG_CMD_KGDB |*/ \
212   - CFG_CMD_MII | \
213   - CFG_CMD_PCI | \
214   - CFG_CMD_PING | \
215   - CFG_CMD_REGINFO | \
216   - CFG_CMD_SDRAM | \
217   - CFG_CMD_FLASH | \
218   - /* CFG_CMD_SPI |*/ \
219   - CFG_CMD_USB | \
220   - 0 ) & ~CFG_CMD_IMLS)
221   -#else
222   -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
223   - CFG_CMD_DATE | \
224   - CFG_CMD_DHCP | \
225   - CFG_CMD_DIAG | \
226   - CFG_CMD_ECHO | \
227   - CFG_CMD_EEPROM | \
228   - CFG_CMD_ELF | \
229   - /* CFG_CMD_EXT2 |*/ \
230   - /* CFG_CMD_FAT |*/ \
231   - CFG_CMD_I2C | \
232   - /* CFG_CMD_IDE |*/ \
233   - CFG_CMD_IRQ | \
234   - /* CFG_CMD_KGDB |*/ \
235   - CFG_CMD_MII | \
236   - CFG_CMD_PCI | \
237   - CFG_CMD_PING | \
238   - CFG_CMD_REGINFO | \
239   - CFG_CMD_SDRAM | \
240   - CFG_CMD_FLASH | \
241   - /* CFG_CMD_SPI |*/ \
242   - 0 ) & ~CFG_CMD_IMLS)
243   -#endif
244   -
245 249 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
246 250 #include <cmd_confdefs.h>
247 251  
... ... @@ -263,8 +267,8 @@
263 267 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
264 268  
265 269 #define CFG_LOAD_ADDR 0x100000 /* default load address */
266   -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
267   -#define CONFIG_LYNXKDI 1 /* support kdi files */
  270 +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
  271 +#define CONFIG_LYNXKDI 1 /* support kdi files */
268 272  
269 273 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
270 274  
271 275  
272 276  
... ... @@ -273,18 +277,18 @@
273 277 *-----------------------------------------------------------------------
274 278 */
275 279 /* General PCI */
276   -#define CONFIG_PCI /* include pci support */
277   -#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
278   -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
279   -#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
  280 +#define CONFIG_PCI /* include pci support */
  281 +#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
  282 +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  283 +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
280 284  
281 285 /* Board-specific PCI */
282   -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
  286 +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
283 287 #define CFG_PCI_TARGET_INIT
284 288 #define CFG_PCI_MASTER_INIT
285 289  
286   -#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
287   -#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
  290 +#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
  291 +#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
288 292  
289 293 /*
290 294 * For booting Linux, the board info and command line data
291 295  
... ... @@ -292,10 +296,11 @@
292 296 * the maximum mapped by the Linux kernel during initialization.
293 297 */
294 298 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  299 +
295 300 /*-----------------------------------------------------------------------
296 301 * Cache Configuration
297 302 */
298   -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
  303 +#define CFG_DCACHE_SIZE 32768 /* For IBM 440 CPUs */
299 304 #define CFG_CACHELINE_SIZE 32 /* ... */
300 305 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
301 306 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
... ... @@ -331,6 +331,158 @@
331 331 #define plb1_bearl (PLB_ARBITER_BASE+ 0x0C)
332 332 #define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)
333 333  
  334 +/* Pin Function Control Register 1 */
  335 +#define SDR0_PFC1 0x4101
  336 +#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
  337 +#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
  338 +#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
  339 +#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
  340 +#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
  341 +#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
  342 +#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
  343 +#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
  344 +#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
  345 +#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
  346 +#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
  347 +#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
  348 +#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
  349 +#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
  350 +#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
  351 +#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
  352 +#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
  353 +#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
  354 +#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
  355 +#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
  356 +#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
  357 +#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
  358 +#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
  359 +#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
  360 +
  361 +#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
  362 +#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
  363 +#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
  364 +#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
  365 +
  366 +/* USB Control Register */
  367 +#define SDR0_USB0 0x0320
  368 +#define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */
  369 +#define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
  370 +#define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
  371 +#define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */
  372 +#define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
  373 +#define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
  374 +
  375 +/* CUST0 Customer Configuration Register0 */
  376 +#define SDR0_CUST0 0x4000
  377 +#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
  378 +#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
  379 +#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
  380 +#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
  381 +
  382 +#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
  383 +#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
  384 +#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
  385 +
  386 +#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
  387 +#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
  388 +#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
  389 +
  390 +#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
  391 +#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
  392 +#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
  393 +
  394 +#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
  395 +#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
  396 +#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
  397 +
  398 +#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
  399 +#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
  400 +#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
  401 +
  402 +#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
  403 +#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
  404 +#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
  405 +
  406 +#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
  407 +#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
  408 +#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
  409 +
  410 +#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
  411 +#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
  412 +#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */
  413 +#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
  414 +#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
  415 +#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
  416 +#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
  417 +
  418 +/* CUST1 Customer Configuration Register1 */
  419 +#define SDR0_CUST1 0x4002
  420 +#define SDR0_CUST1_NDRSC_MASK 0xFFFF0000 /* NDRSC Device Read Count */
  421 +#define SDR0_CUST1_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
  422 +#define SDR0_CUST1_NDRSC_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
  423 +
  424 +/* Pin Function Control Register 0 */
  425 +#define SDR0_PFC0 0x4100
  426 +#define SDR0_PFC0_CPU_TR_EN_MASK 0x00000100 /* CPU Trace Enable Mask */
  427 +#define SDR0_PFC0_CPU_TRACE_EN 0x00000100 /* CPU Trace Enable */
  428 +#define SDR0_PFC0_CPU_TRACE_DIS 0x00000100 /* CPU Trace Disable */
  429 +#define SDR0_PFC0_CTE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8)
  430 +#define SDR0_PFC0_CTE_DECODE(n) ((((unsigned long)(n))>>8)&0x01)
  431 +
  432 +/* Pin Function Control Register 1 */
  433 +#define SDR0_PFC1 0x4101
  434 +#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
  435 +#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
  436 +#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
  437 +#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
  438 +#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
  439 +#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
  440 +#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
  441 +#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
  442 +#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
  443 +#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
  444 +#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
  445 +#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
  446 +#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
  447 +#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
  448 +#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
  449 +#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
  450 +#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
  451 +#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
  452 +#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
  453 +#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
  454 +#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
  455 +#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
  456 +#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
  457 +#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
  458 +
  459 +#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
  460 +#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
  461 +#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
  462 +#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
  463 +
  464 +/* Miscealleneaous Function Reg. */
  465 +#define SDR0_MFR 0x4300
  466 +#define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */
  467 +#define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */
  468 +#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
  469 +#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
  470 +#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
  471 +#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
  472 +#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
  473 +#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
  474 +#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
  475 +#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
  476 +#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
  477 +
  478 +#define SDR0_MFR_ERRATA3_EN0 0x00800000
  479 +#define SDR0_MFR_ERRATA3_EN1 0x00400000
  480 +#define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */
  481 +#define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */
  482 +#define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */
  483 +#define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */
  484 +#define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */
  485 +
334 486 #else
335 487  
336 488 /*-----------------------------------------------------------------------------