Eric Lee / smarc-uboot

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Commit 17fa032671f7981628fe16b30399638842a4b1bb

Authored by Heiko Schocher
Committed by Tom Rini
1 parent 0675f992db
Exists in smarc_8mq_lf_v2020.04 and in 22 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

serial, ns16550: bugfix: ns16550 fifo not enabled 

commit: 65f83802b7a5b "serial: 16550: Add getfcr accessor"
breaks u-boot commandline working with long commands
sending to the board.

Since the above patch, you have to setup the fcr register.

For board/archs which enable OF_PLATDATA, the new field
fcr in struct ns16550_platdata is not filled with a
default value ...

This leads in not setting up the uarts fifo, which ends
in problems, when you send long commands to u-boots
commandline.

Detected this issue with automated tbot tests on am335x
based shc board.

The error does not popup, if you type commands. You need
to copy&paste a long command to u-boots commandshell
(or send a long command with tbot)

Possible boards/plattforms with problems:
./arch/arm/cpu/arm926ejs/lpc32xx/devices.c
./arch/arm/mach-tegra/board.c
./board/overo/overo.c
./board/quipos/cairo/cairo.c
./board/logicpd/omap3som/omap3logic.c
./board/logicpd/zoom1/zoom1.c
./board/timll/devkit8000/devkit8000.c
./board/lg/sniper/sniper.c
./board/ti/beagle/beagle.c
./drivers/serial/serial_rockchip.c

Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

Showing 14 changed files with 46 additions and 24 deletions Inline Diff

arch/arm/cpu/arm926ejs/lpc32xx/devices.c
Diff comments   View file @ 17fa032
1 /* 1 /*
2 * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> 2 * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <dm.h> 8 #include <dm.h>
9 #include <ns16550.h> 9 #include <ns16550.h>
10 #include <dm/platform_data/lpc32xx_hsuart.h> 10 #include <dm/platform_data/lpc32xx_hsuart.h>
11 11
12 #include <asm/arch/clk.h> 12 #include <asm/arch/clk.h>
13 #include <asm/arch/uart.h> 13 #include <asm/arch/uart.h>
14 #include <asm/arch/mux.h> 14 #include <asm/arch/mux.h>
15 #include <asm/io.h> 15 #include <asm/io.h>
16 16
17 static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; 17 static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
18 static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE; 18 static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
19 static struct mux_regs *mux = (struct mux_regs *)MUX_BASE; 19 static struct mux_regs *mux = (struct mux_regs *)MUX_BASE;
20 20
21 void lpc32xx_uart_init(unsigned int uart_id) 21 void lpc32xx_uart_init(unsigned int uart_id)
22 { 22 {
23 if (uart_id < 1 || uart_id > 7) 23 if (uart_id < 1 || uart_id > 7)
24 return; 24 return;
25 25
26 /* Disable loopback mode, if it is set by S1L bootloader */ 26 /* Disable loopback mode, if it is set by S1L bootloader */
27 clrbits_le32(&ctrl->loop, 27 clrbits_le32(&ctrl->loop,
28 UART_LOOPBACK(CONFIG_SYS_LPC32XX_UART)); 28 UART_LOOPBACK(CONFIG_SYS_LPC32XX_UART));
29 29
30 if (uart_id < 3 || uart_id > 6) 30 if (uart_id < 3 || uart_id > 6)
31 return; 31 return;
32 32
33 /* Enable UART system clock */ 33 /* Enable UART system clock */
34 setbits_le32(&clk->uartclk_ctrl, CLK_UART(uart_id)); 34 setbits_le32(&clk->uartclk_ctrl, CLK_UART(uart_id));
35 35
36 /* Set UART into autoclock mode */ 36 /* Set UART into autoclock mode */
37 clrsetbits_le32(&ctrl->clkmode, 37 clrsetbits_le32(&ctrl->clkmode,
38 UART_CLKMODE_MASK(uart_id), 38 UART_CLKMODE_MASK(uart_id),
39 UART_CLKMODE_AUTO(uart_id)); 39 UART_CLKMODE_AUTO(uart_id));
40 40
41 /* Bypass pre-divider of UART clock */ 41 /* Bypass pre-divider of UART clock */
42 writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1), 42 writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
43 &clk->u3clk + (uart_id - 3)); 43 &clk->u3clk + (uart_id - 3));
44 } 44 }
45 45
46 #if !CONFIG_IS_ENABLED(OF_CONTROL) 46 #if !CONFIG_IS_ENABLED(OF_CONTROL)
47 static const struct ns16550_platdata lpc32xx_uart[] = { 47 static const struct ns16550_platdata lpc32xx_uart[] = {
48 { .base = UART3_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, 48 { .base = UART3_BASE, .reg_shift = 2,
49 { .base = UART4_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, 49 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
50 { .base = UART5_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, 50 { .base = UART4_BASE, .reg_shift = 2,
51 { .base = UART6_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, 51 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
52 { .base = UART5_BASE, .reg_shift = 2,
53 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
54 { .base = UART6_BASE, .reg_shift = 2,
55 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
52 }; 56 };
53 57
54 #if defined(CONFIG_LPC32XX_HSUART) 58 #if defined(CONFIG_LPC32XX_HSUART)
55 static const struct lpc32xx_hsuart_platdata lpc32xx_hsuart[] = { 59 static const struct lpc32xx_hsuart_platdata lpc32xx_hsuart[] = {
56 { HS_UART1_BASE, }, 60 { HS_UART1_BASE, },
57 { HS_UART2_BASE, }, 61 { HS_UART2_BASE, },
58 { HS_UART7_BASE, }, 62 { HS_UART7_BASE, },
59 }; 63 };
60 #endif 64 #endif
61 65
62 U_BOOT_DEVICES(lpc32xx_uarts) = { 66 U_BOOT_DEVICES(lpc32xx_uarts) = {
63 #if defined(CONFIG_LPC32XX_HSUART) 67 #if defined(CONFIG_LPC32XX_HSUART)
64 { "lpc32xx_hsuart", &lpc32xx_hsuart[0], }, 68 { "lpc32xx_hsuart", &lpc32xx_hsuart[0], },
65 { "lpc32xx_hsuart", &lpc32xx_hsuart[1], }, 69 { "lpc32xx_hsuart", &lpc32xx_hsuart[1], },
66 #endif 70 #endif
67 { "ns16550_serial", &lpc32xx_uart[0], }, 71 { "ns16550_serial", &lpc32xx_uart[0], },
68 { "ns16550_serial", &lpc32xx_uart[1], }, 72 { "ns16550_serial", &lpc32xx_uart[1], },
69 { "ns16550_serial", &lpc32xx_uart[2], }, 73 { "ns16550_serial", &lpc32xx_uart[2], },
70 { "ns16550_serial", &lpc32xx_uart[3], }, 74 { "ns16550_serial", &lpc32xx_uart[3], },
71 #if defined(CONFIG_LPC32XX_HSUART) 75 #if defined(CONFIG_LPC32XX_HSUART)
72 { "lpc32xx_hsuart", &lpc32xx_hsuart[2], }, 76 { "lpc32xx_hsuart", &lpc32xx_hsuart[2], },
73 #endif 77 #endif
74 }; 78 };
75 #endif 79 #endif
76 80
77 void lpc32xx_dma_init(void) 81 void lpc32xx_dma_init(void)
78 { 82 {
79 /* Enable DMA interface */ 83 /* Enable DMA interface */
80 writel(CLK_DMA_ENABLE, &clk->dmaclk_ctrl); 84 writel(CLK_DMA_ENABLE, &clk->dmaclk_ctrl);
81 } 85 }
82 86
83 void lpc32xx_mac_init(void) 87 void lpc32xx_mac_init(void)
84 { 88 {
85 /* Enable MAC interface */ 89 /* Enable MAC interface */
86 writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER 90 writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
87 #if defined(CONFIG_RMII) 91 #if defined(CONFIG_RMII)
88 | CLK_MAC_RMII, 92 | CLK_MAC_RMII,
89 #else 93 #else
90 | CLK_MAC_MII, 94 | CLK_MAC_MII,
91 #endif 95 #endif
92 &clk->macclk_ctrl); 96 &clk->macclk_ctrl);
93 } 97 }
94 98
95 void lpc32xx_mlc_nand_init(void) 99 void lpc32xx_mlc_nand_init(void)
96 { 100 {
97 /* Enable NAND interface */ 101 /* Enable NAND interface */
98 writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl); 102 writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl);
99 } 103 }
100 104
101 void lpc32xx_slc_nand_init(void) 105 void lpc32xx_slc_nand_init(void)
102 { 106 {
103 /* Enable SLC NAND interface */ 107 /* Enable SLC NAND interface */
104 writel(CLK_NAND_SLC | CLK_NAND_SLC_SELECT, &clk->flashclk_ctrl); 108 writel(CLK_NAND_SLC | CLK_NAND_SLC_SELECT, &clk->flashclk_ctrl);
105 } 109 }
106 110
107 void lpc32xx_usb_init(void) 111 void lpc32xx_usb_init(void)
108 { 112 {
109 /* Do not route the UART 5 Tx/Rx pins to the USB D+ and USB D- pins. */ 113 /* Do not route the UART 5 Tx/Rx pins to the USB D+ and USB D- pins. */
110 clrbits_le32(&ctrl->ctrl, UART_CTRL_UART5_USB_MODE); 114 clrbits_le32(&ctrl->ctrl, UART_CTRL_UART5_USB_MODE);
111 } 115 }
112 116
113 void lpc32xx_i2c_init(unsigned int devnum) 117 void lpc32xx_i2c_init(unsigned int devnum)
114 { 118 {
115 /* Enable I2C interface */ 119 /* Enable I2C interface */
116 uint32_t ctrl = readl(&clk->i2cclk_ctrl); 120 uint32_t ctrl = readl(&clk->i2cclk_ctrl);
117 if (devnum == 1) 121 if (devnum == 1)
118 ctrl |= CLK_I2C1_ENABLE; 122 ctrl |= CLK_I2C1_ENABLE;
119 if (devnum == 2) 123 if (devnum == 2)
120 ctrl |= CLK_I2C2_ENABLE; 124 ctrl |= CLK_I2C2_ENABLE;
121 writel(ctrl, &clk->i2cclk_ctrl); 125 writel(ctrl, &clk->i2cclk_ctrl);
122 } 126 }
123 127
124 U_BOOT_DEVICE(lpc32xx_gpios) = { 128 U_BOOT_DEVICE(lpc32xx_gpios) = {
125 .name = "gpio_lpc32xx" 129 .name = "gpio_lpc32xx"
126 }; 130 };
127 131
128 /* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */ 132 /* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */
129 133
130 #define P_MUX_SET_SSP0 0x1600 134 #define P_MUX_SET_SSP0 0x1600
131 135
132 void lpc32xx_ssp_init(void) 136 void lpc32xx_ssp_init(void)
133 { 137 {
134 /* Enable SSP0 interface */ 138 /* Enable SSP0 interface */
135 writel(CLK_SSP0_ENABLE_CLOCK, &clk->ssp_ctrl); 139 writel(CLK_SSP0_ENABLE_CLOCK, &clk->ssp_ctrl);
136 /* Mux SSP0 pins */ 140 /* Mux SSP0 pins */
137 writel(P_MUX_SET_SSP0, &mux->p_mux_set); 141 writel(P_MUX_SET_SSP0, &mux->p_mux_set);
138 } 142 }
139 143
arch/arm/mach-omap2/am33xx/board.c
Diff comments   View file @ 17fa032
1 /* 1 /*
2 * board.c 2 * board.c
3 * 3 *
4 * Common board functions for AM33XX based boards 4 * Common board functions for AM33XX based boards
5 * 5 *
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7 * 7 *
8 * SPDX-License-Identifier: GPL-2.0+ 8 * SPDX-License-Identifier: GPL-2.0+
9 */ 9 */
10 10
11 #include <common.h> 11 #include <common.h>
12 #include <dm.h> 12 #include <dm.h>
13 #include <errno.h> 13 #include <errno.h>
14 #include <ns16550.h> 14 #include <ns16550.h>
15 #include <spl.h> 15 #include <spl.h>
16 #include <asm/arch/cpu.h> 16 #include <asm/arch/cpu.h>
17 #include <asm/arch/hardware.h> 17 #include <asm/arch/hardware.h>
18 #include <asm/arch/omap.h> 18 #include <asm/arch/omap.h>
19 #include <asm/arch/ddr_defs.h> 19 #include <asm/arch/ddr_defs.h>
20 #include <asm/arch/clock.h> 20 #include <asm/arch/clock.h>
21 #include <asm/arch/gpio.h> 21 #include <asm/arch/gpio.h>
22 #include <asm/arch/mem.h> 22 #include <asm/arch/mem.h>
23 #include <asm/arch/mmc_host_def.h> 23 #include <asm/arch/mmc_host_def.h>
24 #include <asm/arch/sys_proto.h> 24 #include <asm/arch/sys_proto.h>
25 #include <asm/io.h> 25 #include <asm/io.h>
26 #include <asm/emif.h> 26 #include <asm/emif.h>
27 #include <asm/gpio.h> 27 #include <asm/gpio.h>
28 #include <i2c.h> 28 #include <i2c.h>
29 #include <miiphy.h> 29 #include <miiphy.h>
30 #include <cpsw.h> 30 #include <cpsw.h>
31 #include <linux/errno.h> 31 #include <linux/errno.h>
32 #include <linux/compiler.h> 32 #include <linux/compiler.h>
33 #include <linux/usb/ch9.h> 33 #include <linux/usb/ch9.h>
34 #include <linux/usb/gadget.h> 34 #include <linux/usb/gadget.h>
35 #include <linux/usb/musb.h> 35 #include <linux/usb/musb.h>
36 #include <asm/omap_musb.h> 36 #include <asm/omap_musb.h>
37 #include <asm/davinci_rtc.h> 37 #include <asm/davinci_rtc.h>
38 38
39 DECLARE_GLOBAL_DATA_PTR; 39 DECLARE_GLOBAL_DATA_PTR;
40 40
41 #if !CONFIG_IS_ENABLED(OF_CONTROL) 41 #if !CONFIG_IS_ENABLED(OF_CONTROL)
42 static const struct ns16550_platdata am33xx_serial[] = { 42 static const struct ns16550_platdata am33xx_serial[] = {
43 { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, 43 { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
44 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
44 # ifdef CONFIG_SYS_NS16550_COM2 45 # ifdef CONFIG_SYS_NS16550_COM2
45 { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, 46 { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2,
47 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
46 # ifdef CONFIG_SYS_NS16550_COM3 48 # ifdef CONFIG_SYS_NS16550_COM3
47 { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, 49 { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2,
48 { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, 50 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
49 { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, 51 { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2,
50 { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, 52 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
53 { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2,
54 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
55 { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2,
56 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
51 # endif 57 # endif
52 # endif 58 # endif
53 }; 59 };
54 60
55 U_BOOT_DEVICES(am33xx_uarts) = { 61 U_BOOT_DEVICES(am33xx_uarts) = {
56 { "ns16550_serial", &am33xx_serial[0] }, 62 { "ns16550_serial", &am33xx_serial[0] },
57 # ifdef CONFIG_SYS_NS16550_COM2 63 # ifdef CONFIG_SYS_NS16550_COM2
58 { "ns16550_serial", &am33xx_serial[1] }, 64 { "ns16550_serial", &am33xx_serial[1] },
59 # ifdef CONFIG_SYS_NS16550_COM3 65 # ifdef CONFIG_SYS_NS16550_COM3
60 { "ns16550_serial", &am33xx_serial[2] }, 66 { "ns16550_serial", &am33xx_serial[2] },
61 { "ns16550_serial", &am33xx_serial[3] }, 67 { "ns16550_serial", &am33xx_serial[3] },
62 { "ns16550_serial", &am33xx_serial[4] }, 68 { "ns16550_serial", &am33xx_serial[4] },
63 { "ns16550_serial", &am33xx_serial[5] }, 69 { "ns16550_serial", &am33xx_serial[5] },
64 # endif 70 # endif
65 # endif 71 # endif
66 }; 72 };
67 73
68 #ifdef CONFIG_DM_GPIO 74 #ifdef CONFIG_DM_GPIO
69 static const struct omap_gpio_platdata am33xx_gpio[] = { 75 static const struct omap_gpio_platdata am33xx_gpio[] = {
70 { 0, AM33XX_GPIO0_BASE }, 76 { 0, AM33XX_GPIO0_BASE },
71 { 1, AM33XX_GPIO1_BASE }, 77 { 1, AM33XX_GPIO1_BASE },
72 { 2, AM33XX_GPIO2_BASE }, 78 { 2, AM33XX_GPIO2_BASE },
73 { 3, AM33XX_GPIO3_BASE }, 79 { 3, AM33XX_GPIO3_BASE },
74 #ifdef CONFIG_AM43XX 80 #ifdef CONFIG_AM43XX
75 { 4, AM33XX_GPIO4_BASE }, 81 { 4, AM33XX_GPIO4_BASE },
76 { 5, AM33XX_GPIO5_BASE }, 82 { 5, AM33XX_GPIO5_BASE },
77 #endif 83 #endif
78 }; 84 };
79 85
80 U_BOOT_DEVICES(am33xx_gpios) = { 86 U_BOOT_DEVICES(am33xx_gpios) = {
81 { "gpio_omap", &am33xx_gpio[0] }, 87 { "gpio_omap", &am33xx_gpio[0] },
82 { "gpio_omap", &am33xx_gpio[1] }, 88 { "gpio_omap", &am33xx_gpio[1] },
83 { "gpio_omap", &am33xx_gpio[2] }, 89 { "gpio_omap", &am33xx_gpio[2] },
84 { "gpio_omap", &am33xx_gpio[3] }, 90 { "gpio_omap", &am33xx_gpio[3] },
85 #ifdef CONFIG_AM43XX 91 #ifdef CONFIG_AM43XX
86 { "gpio_omap", &am33xx_gpio[4] }, 92 { "gpio_omap", &am33xx_gpio[4] },
87 { "gpio_omap", &am33xx_gpio[5] }, 93 { "gpio_omap", &am33xx_gpio[5] },
88 #endif 94 #endif
89 }; 95 };
90 #endif 96 #endif
91 #endif 97 #endif
92 98
93 #ifndef CONFIG_DM_GPIO 99 #ifndef CONFIG_DM_GPIO
94 static const struct gpio_bank gpio_bank_am33xx[] = { 100 static const struct gpio_bank gpio_bank_am33xx[] = {
95 { (void *)AM33XX_GPIO0_BASE }, 101 { (void *)AM33XX_GPIO0_BASE },
96 { (void *)AM33XX_GPIO1_BASE }, 102 { (void *)AM33XX_GPIO1_BASE },
97 { (void *)AM33XX_GPIO2_BASE }, 103 { (void *)AM33XX_GPIO2_BASE },
98 { (void *)AM33XX_GPIO3_BASE }, 104 { (void *)AM33XX_GPIO3_BASE },
99 #ifdef CONFIG_AM43XX 105 #ifdef CONFIG_AM43XX
100 { (void *)AM33XX_GPIO4_BASE }, 106 { (void *)AM33XX_GPIO4_BASE },
101 { (void *)AM33XX_GPIO5_BASE }, 107 { (void *)AM33XX_GPIO5_BASE },
102 #endif 108 #endif
103 }; 109 };
104 110
105 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; 111 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
106 #endif 112 #endif
107 113
108 #if defined(CONFIG_MMC_OMAP_HS) && !defined(CONFIG_SPL_BUILD) 114 #if defined(CONFIG_MMC_OMAP_HS) && !defined(CONFIG_SPL_BUILD)
109 int cpu_mmc_init(bd_t *bis) 115 int cpu_mmc_init(bd_t *bis)
110 { 116 {
111 int ret; 117 int ret;
112 118
113 ret = omap_mmc_init(0, 0, 0, -1, -1); 119 ret = omap_mmc_init(0, 0, 0, -1, -1);
114 if (ret) 120 if (ret)
115 return ret; 121 return ret;
116 122
117 return omap_mmc_init(1, 0, 0, -1, -1); 123 return omap_mmc_init(1, 0, 0, -1, -1);
118 } 124 }
119 #endif 125 #endif
120 126
121 /* AM33XX has two MUSB controllers which can be host or gadget */ 127 /* AM33XX has two MUSB controllers which can be host or gadget */
122 #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \ 128 #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
123 (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \ 129 (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
124 (!defined(CONFIG_DM_USB)) 130 (!defined(CONFIG_DM_USB))
125 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 131 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
126 132
127 /* USB 2.0 PHY Control */ 133 /* USB 2.0 PHY Control */
128 #define CM_PHY_PWRDN (1 << 0) 134 #define CM_PHY_PWRDN (1 << 0)
129 #define CM_PHY_OTG_PWRDN (1 << 1) 135 #define CM_PHY_OTG_PWRDN (1 << 1)
130 #define OTGVDET_EN (1 << 19) 136 #define OTGVDET_EN (1 << 19)
131 #define OTGSESSENDEN (1 << 20) 137 #define OTGSESSENDEN (1 << 20)
132 138
133 static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr) 139 static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
134 { 140 {
135 if (on) { 141 if (on) {
136 clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN, 142 clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
137 OTGVDET_EN | OTGSESSENDEN); 143 OTGVDET_EN | OTGSESSENDEN);
138 } else { 144 } else {
139 clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN); 145 clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
140 } 146 }
141 } 147 }
142 148
143 static struct musb_hdrc_config musb_config = { 149 static struct musb_hdrc_config musb_config = {
144 .multipoint = 1, 150 .multipoint = 1,
145 .dyn_fifo = 1, 151 .dyn_fifo = 1,
146 .num_eps = 16, 152 .num_eps = 16,
147 .ram_bits = 12, 153 .ram_bits = 12,
148 }; 154 };
149 155
150 #ifdef CONFIG_AM335X_USB0 156 #ifdef CONFIG_AM335X_USB0
151 static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on) 157 static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on)
152 { 158 {
153 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0); 159 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
154 } 160 }
155 161
156 struct omap_musb_board_data otg0_board_data = { 162 struct omap_musb_board_data otg0_board_data = {
157 .set_phy_power = am33xx_otg0_set_phy_power, 163 .set_phy_power = am33xx_otg0_set_phy_power,
158 }; 164 };
159 165
160 static struct musb_hdrc_platform_data otg0_plat = { 166 static struct musb_hdrc_platform_data otg0_plat = {
161 .mode = CONFIG_AM335X_USB0_MODE, 167 .mode = CONFIG_AM335X_USB0_MODE,
162 .config = &musb_config, 168 .config = &musb_config,
163 .power = 50, 169 .power = 50,
164 .platform_ops = &musb_dsps_ops, 170 .platform_ops = &musb_dsps_ops,
165 .board_data = &otg0_board_data, 171 .board_data = &otg0_board_data,
166 }; 172 };
167 #endif 173 #endif
168 174
169 #ifdef CONFIG_AM335X_USB1 175 #ifdef CONFIG_AM335X_USB1
170 static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on) 176 static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on)
171 { 177 {
172 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1); 178 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
173 } 179 }
174 180
175 struct omap_musb_board_data otg1_board_data = { 181 struct omap_musb_board_data otg1_board_data = {
176 .set_phy_power = am33xx_otg1_set_phy_power, 182 .set_phy_power = am33xx_otg1_set_phy_power,
177 }; 183 };
178 184
179 static struct musb_hdrc_platform_data otg1_plat = { 185 static struct musb_hdrc_platform_data otg1_plat = {
180 .mode = CONFIG_AM335X_USB1_MODE, 186 .mode = CONFIG_AM335X_USB1_MODE,
181 .config = &musb_config, 187 .config = &musb_config,
182 .power = 50, 188 .power = 50,
183 .platform_ops = &musb_dsps_ops, 189 .platform_ops = &musb_dsps_ops,
184 .board_data = &otg1_board_data, 190 .board_data = &otg1_board_data,
185 }; 191 };
186 #endif 192 #endif
187 #endif 193 #endif
188 194
189 int arch_misc_init(void) 195 int arch_misc_init(void)
190 { 196 {
191 #ifndef CONFIG_DM_USB 197 #ifndef CONFIG_DM_USB
192 #ifdef CONFIG_AM335X_USB0 198 #ifdef CONFIG_AM335X_USB0
193 musb_register(&otg0_plat, &otg0_board_data, 199 musb_register(&otg0_plat, &otg0_board_data,
194 (void *)USB0_OTG_BASE); 200 (void *)USB0_OTG_BASE);
195 #endif 201 #endif
196 #ifdef CONFIG_AM335X_USB1 202 #ifdef CONFIG_AM335X_USB1
197 musb_register(&otg1_plat, &otg1_board_data, 203 musb_register(&otg1_plat, &otg1_board_data,
198 (void *)USB1_OTG_BASE); 204 (void *)USB1_OTG_BASE);
199 #endif 205 #endif
200 #else 206 #else
201 struct udevice *dev; 207 struct udevice *dev;
202 int ret; 208 int ret;
203 209
204 ret = uclass_first_device(UCLASS_MISC, &dev); 210 ret = uclass_first_device(UCLASS_MISC, &dev);
205 if (ret || !dev) 211 if (ret || !dev)
206 return ret; 212 return ret;
207 213
208 #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER) 214 #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
209 ret = usb_ether_init(); 215 ret = usb_ether_init();
210 if (ret) { 216 if (ret) {
211 error("USB ether init failed\n"); 217 error("USB ether init failed\n");
212 return ret; 218 return ret;
213 } 219 }
214 #endif 220 #endif
215 #endif 221 #endif
216 return 0; 222 return 0;
217 } 223 }
218 224
219 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 225 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
220 /* 226 /*
221 * In the case of non-SPL based booting we'll want to call these 227 * In the case of non-SPL based booting we'll want to call these
222 * functions a tiny bit later as it will require gd to be set and cleared 228 * functions a tiny bit later as it will require gd to be set and cleared
223 * and that's not true in s_init in this case so we cannot do it there. 229 * and that's not true in s_init in this case so we cannot do it there.
224 */ 230 */
225 int board_early_init_f(void) 231 int board_early_init_f(void)
226 { 232 {
227 prcm_init(); 233 prcm_init();
228 set_mux_conf_regs(); 234 set_mux_conf_regs();
229 235
230 return 0; 236 return 0;
231 } 237 }
232 238
233 /* 239 /*
234 * This function is the place to do per-board things such as ramp up the 240 * This function is the place to do per-board things such as ramp up the
235 * MPU clock frequency. 241 * MPU clock frequency.
236 */ 242 */
237 __weak void am33xx_spl_board_init(void) 243 __weak void am33xx_spl_board_init(void)
238 { 244 {
239 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); 245 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
240 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); 246 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
241 } 247 }
242 248
243 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) 249 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
244 static void rtc32k_enable(void) 250 static void rtc32k_enable(void)
245 { 251 {
246 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; 252 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
247 253
248 /* 254 /*
249 * Unlock the RTC's registers. For more details please see the 255 * Unlock the RTC's registers. For more details please see the
250 * RTC_SS section of the TRM. In order to unlock we need to 256 * RTC_SS section of the TRM. In order to unlock we need to
251 * write these specific values (keys) in this order. 257 * write these specific values (keys) in this order.
252 */ 258 */
253 writel(RTC_KICK0R_WE, &rtc->kick0r); 259 writel(RTC_KICK0R_WE, &rtc->kick0r);
254 writel(RTC_KICK1R_WE, &rtc->kick1r); 260 writel(RTC_KICK1R_WE, &rtc->kick1r);
255 261
256 /* Enable the RTC 32K OSC by setting bits 3 and 6. */ 262 /* Enable the RTC 32K OSC by setting bits 3 and 6. */
257 writel((1 << 3) | (1 << 6), &rtc->osc); 263 writel((1 << 3) | (1 << 6), &rtc->osc);
258 } 264 }
259 #endif 265 #endif
260 266
261 static void uart_soft_reset(void) 267 static void uart_soft_reset(void)
262 { 268 {
263 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; 269 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
264 u32 regval; 270 u32 regval;
265 271
266 regval = readl(&uart_base->uartsyscfg); 272 regval = readl(&uart_base->uartsyscfg);
267 regval |= UART_RESET; 273 regval |= UART_RESET;
268 writel(regval, &uart_base->uartsyscfg); 274 writel(regval, &uart_base->uartsyscfg);
269 while ((readl(&uart_base->uartsyssts) & 275 while ((readl(&uart_base->uartsyssts) &
270 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) 276 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
271 ; 277 ;
272 278
273 /* Disable smart idle */ 279 /* Disable smart idle */
274 regval = readl(&uart_base->uartsyscfg); 280 regval = readl(&uart_base->uartsyscfg);
275 regval |= UART_SMART_IDLE_EN; 281 regval |= UART_SMART_IDLE_EN;
276 writel(regval, &uart_base->uartsyscfg); 282 writel(regval, &uart_base->uartsyscfg);
277 } 283 }
278 284
279 static void watchdog_disable(void) 285 static void watchdog_disable(void)
280 { 286 {
281 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; 287 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
282 288
283 writel(0xAAAA, &wdtimer->wdtwspr); 289 writel(0xAAAA, &wdtimer->wdtwspr);
284 while (readl(&wdtimer->wdtwwps) != 0x0) 290 while (readl(&wdtimer->wdtwwps) != 0x0)
285 ; 291 ;
286 writel(0x5555, &wdtimer->wdtwspr); 292 writel(0x5555, &wdtimer->wdtwspr);
287 while (readl(&wdtimer->wdtwwps) != 0x0) 293 while (readl(&wdtimer->wdtwwps) != 0x0)
288 ; 294 ;
289 } 295 }
290 296
291 void s_init(void) 297 void s_init(void)
292 { 298 {
293 } 299 }
294 300
295 void early_system_init(void) 301 void early_system_init(void)
296 { 302 {
297 /* 303 /*
298 * The ROM will only have set up sufficient pinmux to allow for the 304 * The ROM will only have set up sufficient pinmux to allow for the
299 * first 4KiB NOR to be read, we must finish doing what we know of 305 * first 4KiB NOR to be read, we must finish doing what we know of
300 * the NOR mux in this space in order to continue. 306 * the NOR mux in this space in order to continue.
301 */ 307 */
302 #ifdef CONFIG_NOR_BOOT 308 #ifdef CONFIG_NOR_BOOT
303 enable_norboot_pin_mux(); 309 enable_norboot_pin_mux();
304 #endif 310 #endif
305 watchdog_disable(); 311 watchdog_disable();
306 set_uart_mux_conf(); 312 set_uart_mux_conf();
307 setup_early_clocks(); 313 setup_early_clocks();
308 uart_soft_reset(); 314 uart_soft_reset();
309 #ifdef CONFIG_TI_I2C_BOARD_DETECT 315 #ifdef CONFIG_TI_I2C_BOARD_DETECT
310 do_board_detect(); 316 do_board_detect();
311 #endif 317 #endif
312 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) 318 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
313 /* Enable RTC32K clock */ 319 /* Enable RTC32K clock */
314 rtc32k_enable(); 320 rtc32k_enable();
315 #endif 321 #endif
316 } 322 }
317 323
318 #ifdef CONFIG_SPL_BUILD 324 #ifdef CONFIG_SPL_BUILD
319 void board_init_f(ulong dummy) 325 void board_init_f(ulong dummy)
320 { 326 {
321 early_system_init(); 327 early_system_init();
322 board_early_init_f(); 328 board_early_init_f();
323 sdram_init(); 329 sdram_init();
324 } 330 }
325 #endif 331 #endif
326 332
327 #endif 333 #endif
328 334
329 int arch_cpu_init_dm(void) 335 int arch_cpu_init_dm(void)
330 { 336 {
331 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 337 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
332 early_system_init(); 338 early_system_init();
333 #endif 339 #endif
334 return 0; 340 return 0;
335 } 341 }
336 342
arch/arm/mach-tegra/board.c
Diff comments   View file @ 17fa032
1 /* 1 /*
2 * (C) Copyright 2010-2015 2 * (C) Copyright 2010-2015
3 * NVIDIA Corporation <www.nvidia.com> 3 * NVIDIA Corporation <www.nvidia.com>
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #include <common.h> 8 #include <common.h>
9 #include <dm.h> 9 #include <dm.h>
10 #include <ns16550.h> 10 #include <ns16550.h>
11 #include <spl.h> 11 #include <spl.h>
12 #include <asm/io.h> 12 #include <asm/io.h>
13 #include <asm/arch/clock.h> 13 #include <asm/arch/clock.h>
14 #include <asm/arch/funcmux.h> 14 #include <asm/arch/funcmux.h>
15 #include <asm/arch/mc.h> 15 #include <asm/arch/mc.h>
16 #include <asm/arch/tegra.h> 16 #include <asm/arch/tegra.h>
17 #include <asm/arch-tegra/ap.h> 17 #include <asm/arch-tegra/ap.h>
18 #include <asm/arch-tegra/board.h> 18 #include <asm/arch-tegra/board.h>
19 #include <asm/arch-tegra/pmc.h> 19 #include <asm/arch-tegra/pmc.h>
20 #include <asm/arch-tegra/sys_proto.h> 20 #include <asm/arch-tegra/sys_proto.h>
21 #include <asm/arch-tegra/warmboot.h> 21 #include <asm/arch-tegra/warmboot.h>
22 22
23 void save_boot_params_ret(void); 23 void save_boot_params_ret(void);
24 24
25 DECLARE_GLOBAL_DATA_PTR; 25 DECLARE_GLOBAL_DATA_PTR;
26 26
27 enum { 27 enum {
28 /* UARTs which we can enable */ 28 /* UARTs which we can enable */
29 UARTA = 1 << 0, 29 UARTA = 1 << 0,
30 UARTB = 1 << 1, 30 UARTB = 1 << 1,
31 UARTC = 1 << 2, 31 UARTC = 1 << 2,
32 UARTD = 1 << 3, 32 UARTD = 1 << 3,
33 UARTE = 1 << 4, 33 UARTE = 1 << 4,
34 UART_COUNT = 5, 34 UART_COUNT = 5,
35 }; 35 };
36 36
37 static bool from_spl __attribute__ ((section(".data"))); 37 static bool from_spl __attribute__ ((section(".data")));
38 38
39 #ifndef CONFIG_SPL_BUILD 39 #ifndef CONFIG_SPL_BUILD
40 void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) 40 void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
41 { 41 {
42 from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL; 42 from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL;
43 save_boot_params_ret(); 43 save_boot_params_ret();
44 } 44 }
45 #endif 45 #endif
46 46
47 bool spl_was_boot_source(void) 47 bool spl_was_boot_source(void)
48 { 48 {
49 return from_spl; 49 return from_spl;
50 } 50 }
51 51
52 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) 52 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
53 #if !defined(CONFIG_TEGRA124) 53 #if !defined(CONFIG_TEGRA124)
54 #error tegra_cpu_is_non_secure has only been validated on Tegra124 54 #error tegra_cpu_is_non_secure has only been validated on Tegra124
55 #endif 55 #endif
56 bool tegra_cpu_is_non_secure(void) 56 bool tegra_cpu_is_non_secure(void)
57 { 57 {
58 /* 58 /*
59 * This register reads 0xffffffff in non-secure mode. This register 59 * This register reads 0xffffffff in non-secure mode. This register
60 * only implements bits 31:20, so the lower bits will always read 0 in 60 * only implements bits 31:20, so the lower bits will always read 0 in
61 * secure mode. Thus, the lower bits are an indicator for secure vs. 61 * secure mode. Thus, the lower bits are an indicator for secure vs.
62 * non-secure mode. 62 * non-secure mode.
63 */ 63 */
64 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE; 64 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
65 uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0); 65 uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0);
66 return (mc_s_cfg0 & 1) == 1; 66 return (mc_s_cfg0 & 1) == 1;
67 } 67 }
68 #endif 68 #endif
69 69
70 /* Read the RAM size directly from the memory controller */ 70 /* Read the RAM size directly from the memory controller */
71 static phys_size_t query_sdram_size(void) 71 static phys_size_t query_sdram_size(void)
72 { 72 {
73 struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE; 73 struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE;
74 u32 emem_cfg; 74 u32 emem_cfg;
75 phys_size_t size_bytes; 75 phys_size_t size_bytes;
76 76
77 emem_cfg = readl(&mc->mc_emem_cfg); 77 emem_cfg = readl(&mc->mc_emem_cfg);
78 #if defined(CONFIG_TEGRA20) 78 #if defined(CONFIG_TEGRA20)
79 debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg); 79 debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg);
80 size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024); 80 size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024);
81 #else 81 #else
82 debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg); 82 debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg);
83 #ifndef CONFIG_PHYS_64BIT 83 #ifndef CONFIG_PHYS_64BIT
84 /* 84 /*
85 * If >=4GB RAM is present, the byte RAM size won't fit into 32-bits 85 * If >=4GB RAM is present, the byte RAM size won't fit into 32-bits
86 * and will wrap. Clip the reported size to the maximum that a 32-bit 86 * and will wrap. Clip the reported size to the maximum that a 32-bit
87 * variable can represent (rounded to a page). 87 * variable can represent (rounded to a page).
88 */ 88 */
89 if (emem_cfg >= 4096) { 89 if (emem_cfg >= 4096) {
90 size_bytes = U32_MAX & ~(0x1000 - 1); 90 size_bytes = U32_MAX & ~(0x1000 - 1);
91 } else 91 } else
92 #endif 92 #endif
93 { 93 {
94 /* RAM size EMC is programmed to. */ 94 /* RAM size EMC is programmed to. */
95 size_bytes = (phys_size_t)emem_cfg * 1024 * 1024; 95 size_bytes = (phys_size_t)emem_cfg * 1024 * 1024;
96 #ifndef CONFIG_ARM64 96 #ifndef CONFIG_ARM64
97 /* 97 /*
98 * If all RAM fits within 32-bits, it can be accessed without 98 * If all RAM fits within 32-bits, it can be accessed without
99 * LPAE, so go test the RAM size. Otherwise, we can't access 99 * LPAE, so go test the RAM size. Otherwise, we can't access
100 * all the RAM, and get_ram_size() would get confused, so 100 * all the RAM, and get_ram_size() would get confused, so
101 * avoid using it. There's no reason we should need this 101 * avoid using it. There's no reason we should need this
102 * validation step anyway. 102 * validation step anyway.
103 */ 103 */
104 if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024)) 104 if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024))
105 size_bytes = get_ram_size((void *)PHYS_SDRAM_1, 105 size_bytes = get_ram_size((void *)PHYS_SDRAM_1,
106 size_bytes); 106 size_bytes);
107 #endif 107 #endif
108 } 108 }
109 #endif 109 #endif
110 110
111 #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) 111 #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
112 /* External memory limited to 2047 MB due to IROM/HI-VEC */ 112 /* External memory limited to 2047 MB due to IROM/HI-VEC */
113 if (size_bytes == SZ_2G) 113 if (size_bytes == SZ_2G)
114 size_bytes -= SZ_1M; 114 size_bytes -= SZ_1M;
115 #endif 115 #endif
116 116
117 return size_bytes; 117 return size_bytes;
118 } 118 }
119 119
120 int dram_init(void) 120 int dram_init(void)
121 { 121 {
122 /* We do not initialise DRAM here. We just query the size */ 122 /* We do not initialise DRAM here. We just query the size */
123 gd->ram_size = query_sdram_size(); 123 gd->ram_size = query_sdram_size();
124 return 0; 124 return 0;
125 } 125 }
126 126
127 static int uart_configs[] = { 127 static int uart_configs[] = {
128 #if defined(CONFIG_TEGRA20) 128 #if defined(CONFIG_TEGRA20)
129 #if defined(CONFIG_TEGRA_UARTA_UAA_UAB) 129 #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
130 FUNCMUX_UART1_UAA_UAB, 130 FUNCMUX_UART1_UAA_UAB,
131 #elif defined(CONFIG_TEGRA_UARTA_GPU) 131 #elif defined(CONFIG_TEGRA_UARTA_GPU)
132 FUNCMUX_UART1_GPU, 132 FUNCMUX_UART1_GPU,
133 #elif defined(CONFIG_TEGRA_UARTA_SDIO1) 133 #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
134 FUNCMUX_UART1_SDIO1, 134 FUNCMUX_UART1_SDIO1,
135 #else 135 #else
136 FUNCMUX_UART1_IRRX_IRTX, 136 FUNCMUX_UART1_IRRX_IRTX,
137 #endif 137 #endif
138 FUNCMUX_UART2_UAD, 138 FUNCMUX_UART2_UAD,
139 -1, 139 -1,
140 FUNCMUX_UART4_GMC, 140 FUNCMUX_UART4_GMC,
141 -1, 141 -1,
142 #elif defined(CONFIG_TEGRA30) 142 #elif defined(CONFIG_TEGRA30)
143 FUNCMUX_UART1_ULPI, /* UARTA */ 143 FUNCMUX_UART1_ULPI, /* UARTA */
144 -1, 144 -1,
145 -1, 145 -1,
146 -1, 146 -1,
147 -1, 147 -1,
148 #elif defined(CONFIG_TEGRA114) 148 #elif defined(CONFIG_TEGRA114)
149 -1, 149 -1,
150 -1, 150 -1,
151 -1, 151 -1,
152 FUNCMUX_UART4_GMI, /* UARTD */ 152 FUNCMUX_UART4_GMI, /* UARTD */
153 -1, 153 -1,
154 #elif defined(CONFIG_TEGRA124) 154 #elif defined(CONFIG_TEGRA124)
155 FUNCMUX_UART1_KBC, /* UARTA */ 155 FUNCMUX_UART1_KBC, /* UARTA */
156 -1, 156 -1,
157 -1, 157 -1,
158 FUNCMUX_UART4_GPIO, /* UARTD */ 158 FUNCMUX_UART4_GPIO, /* UARTD */
159 -1, 159 -1,
160 #else /* Tegra210 */ 160 #else /* Tegra210 */
161 FUNCMUX_UART1_UART1, /* UARTA */ 161 FUNCMUX_UART1_UART1, /* UARTA */
162 -1, 162 -1,
163 -1, 163 -1,
164 FUNCMUX_UART4_UART4, /* UARTD */ 164 FUNCMUX_UART4_UART4, /* UARTD */
165 -1, 165 -1,
166 #endif 166 #endif
167 }; 167 };
168 168
169 /** 169 /**
170 * Set up the specified uarts 170 * Set up the specified uarts
171 * 171 *
172 * @param uarts_ids Mask containing UARTs to init (UARTx) 172 * @param uarts_ids Mask containing UARTs to init (UARTx)
173 */ 173 */
174 static void setup_uarts(int uart_ids) 174 static void setup_uarts(int uart_ids)
175 { 175 {
176 static enum periph_id id_for_uart[] = { 176 static enum periph_id id_for_uart[] = {
177 PERIPH_ID_UART1, 177 PERIPH_ID_UART1,
178 PERIPH_ID_UART2, 178 PERIPH_ID_UART2,
179 PERIPH_ID_UART3, 179 PERIPH_ID_UART3,
180 PERIPH_ID_UART4, 180 PERIPH_ID_UART4,
181 PERIPH_ID_UART5, 181 PERIPH_ID_UART5,
182 }; 182 };
183 size_t i; 183 size_t i;
184 184
185 for (i = 0; i < UART_COUNT; i++) { 185 for (i = 0; i < UART_COUNT; i++) {
186 if (uart_ids & (1 << i)) { 186 if (uart_ids & (1 << i)) {
187 enum periph_id id = id_for_uart[i]; 187 enum periph_id id = id_for_uart[i];
188 188
189 funcmux_select(id, uart_configs[i]); 189 funcmux_select(id, uart_configs[i]);
190 clock_ll_start_uart(id); 190 clock_ll_start_uart(id);
191 } 191 }
192 } 192 }
193 } 193 }
194 194
195 void board_init_uart_f(void) 195 void board_init_uart_f(void)
196 { 196 {
197 int uart_ids = 0; /* bit mask of which UART ids to enable */ 197 int uart_ids = 0; /* bit mask of which UART ids to enable */
198 198
199 #ifdef CONFIG_TEGRA_ENABLE_UARTA 199 #ifdef CONFIG_TEGRA_ENABLE_UARTA
200 uart_ids |= UARTA; 200 uart_ids |= UARTA;
201 #endif 201 #endif
202 #ifdef CONFIG_TEGRA_ENABLE_UARTB 202 #ifdef CONFIG_TEGRA_ENABLE_UARTB
203 uart_ids |= UARTB; 203 uart_ids |= UARTB;
204 #endif 204 #endif
205 #ifdef CONFIG_TEGRA_ENABLE_UARTC 205 #ifdef CONFIG_TEGRA_ENABLE_UARTC
206 uart_ids |= UARTC; 206 uart_ids |= UARTC;
207 #endif 207 #endif
208 #ifdef CONFIG_TEGRA_ENABLE_UARTD 208 #ifdef CONFIG_TEGRA_ENABLE_UARTD
209 uart_ids |= UARTD; 209 uart_ids |= UARTD;
210 #endif 210 #endif
211 #ifdef CONFIG_TEGRA_ENABLE_UARTE 211 #ifdef CONFIG_TEGRA_ENABLE_UARTE
212 uart_ids |= UARTE; 212 uart_ids |= UARTE;
213 #endif 213 #endif
214 setup_uarts(uart_ids); 214 setup_uarts(uart_ids);
215 } 215 }
216 216
217 #if !CONFIG_IS_ENABLED(OF_CONTROL) 217 #if !CONFIG_IS_ENABLED(OF_CONTROL)
218 static struct ns16550_platdata ns16550_com1_pdata = { 218 static struct ns16550_platdata ns16550_com1_pdata = {
219 .base = CONFIG_SYS_NS16550_COM1, 219 .base = CONFIG_SYS_NS16550_COM1,
220 .reg_shift = 2, 220 .reg_shift = 2,
221 .clock = CONFIG_SYS_NS16550_CLK, 221 .clock = CONFIG_SYS_NS16550_CLK,
222 .fcr = UART_FCR_DEFVAL,
222 }; 223 };
223 224
224 U_BOOT_DEVICE(ns16550_com1) = { 225 U_BOOT_DEVICE(ns16550_com1) = {
225 "ns16550_serial", &ns16550_com1_pdata 226 "ns16550_serial", &ns16550_com1_pdata
226 }; 227 };
227 #endif 228 #endif
228 229
229 #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) 230 #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
230 void enable_caches(void) 231 void enable_caches(void)
231 { 232 {
232 /* Enable D-cache. I-cache is already enabled in start.S */ 233 /* Enable D-cache. I-cache is already enabled in start.S */
233 dcache_enable(); 234 dcache_enable();
234 } 235 }
235 #endif 236 #endif
236 237
board/isee/igep00x0/igep00x0.c
Diff comments   View file @ 17fa032
1 /* 1 /*
2 * (C) Copyright 2010 2 * (C) Copyright 2010
3 * ISEE 2007 SL, <www.iseebcn.com> 3 * ISEE 2007 SL, <www.iseebcn.com>
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 #include <common.h> 7 #include <common.h>
8 #include <status_led.h> 8 #include <status_led.h>
9 #include <dm.h> 9 #include <dm.h>
10 #include <ns16550.h> 10 #include <ns16550.h>
11 #include <twl4030.h> 11 #include <twl4030.h>
12 #include <netdev.h> 12 #include <netdev.h>
13 #include <spl.h> 13 #include <spl.h>
14 #include <asm/gpio.h> 14 #include <asm/gpio.h>
15 #include <asm/io.h> 15 #include <asm/io.h>
16 #include <asm/arch/mem.h> 16 #include <asm/arch/mem.h>
17 #include <asm/arch/mmc_host_def.h> 17 #include <asm/arch/mmc_host_def.h>
18 #include <asm/arch/mux.h> 18 #include <asm/arch/mux.h>
19 #include <asm/arch/sys_proto.h> 19 #include <asm/arch/sys_proto.h>
20 #include <asm/mach-types.h> 20 #include <asm/mach-types.h>
21 #include <linux/mtd/mtd.h> 21 #include <linux/mtd/mtd.h>
22 #include <linux/mtd/nand.h> 22 #include <linux/mtd/nand.h>
23 #include <linux/mtd/nand.h> 23 #include <linux/mtd/nand.h>
24 #include <linux/mtd/onenand.h> 24 #include <linux/mtd/onenand.h>
25 #include <jffs2/load_kernel.h> 25 #include <jffs2/load_kernel.h>
26 #include <mtd_node.h> 26 #include <mtd_node.h>
27 #include <fdt_support.h> 27 #include <fdt_support.h>
28 #include "igep00x0.h" 28 #include "igep00x0.h"
29 29
30 DECLARE_GLOBAL_DATA_PTR; 30 DECLARE_GLOBAL_DATA_PTR;
31 31
32 static const struct ns16550_platdata igep_serial = { 32 static const struct ns16550_platdata igep_serial = {
33 .base = OMAP34XX_UART3, 33 .base = OMAP34XX_UART3,
34 .reg_shift = 2, 34 .reg_shift = 2,
35 .clock = V_NS16550_CLK 35 .clock = V_NS16550_CLK,
36 .fcr = UART_FCR_DEFVAL,
36 }; 37 };
37 38
38 U_BOOT_DEVICE(igep_uart) = { 39 U_BOOT_DEVICE(igep_uart) = {
39 "ns16550_serial", 40 "ns16550_serial",
40 &igep_serial 41 &igep_serial
41 }; 42 };
42 43
43 /* 44 /*
44 * Routine: board_init 45 * Routine: board_init
45 * Description: Early hardware init. 46 * Description: Early hardware init.
46 */ 47 */
47 int board_init(void) 48 int board_init(void)
48 { 49 {
49 int loops = 100; 50 int loops = 100;
50 51
51 /* find out flash memory type, assume NAND first */ 52 /* find out flash memory type, assume NAND first */
52 gpmc_cs0_flash = MTD_DEV_TYPE_NAND; 53 gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
53 gpmc_init(); 54 gpmc_init();
54 55
55 /* Issue a RESET and then READID */ 56 /* Issue a RESET and then READID */
56 writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd); 57 writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
57 writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd); 58 writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
58 while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY) 59 while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
59 != NAND_STATUS_READY) { 60 != NAND_STATUS_READY) {
60 udelay(1); 61 udelay(1);
61 if (--loops == 0) { 62 if (--loops == 0) {
62 gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; 63 gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
63 gpmc_init(); /* reinitialize for OneNAND */ 64 gpmc_init(); /* reinitialize for OneNAND */
64 break; 65 break;
65 } 66 }
66 } 67 }
67 68
68 /* boot param addr */ 69 /* boot param addr */
69 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 70 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
70 71
71 #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) 72 #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
72 status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); 73 status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
73 #endif 74 #endif
74 75
75 return 0; 76 return 0;
76 } 77 }
77 78
78 #ifdef CONFIG_SPL_BUILD 79 #ifdef CONFIG_SPL_BUILD
79 /* 80 /*
80 * Routine: get_board_mem_timings 81 * Routine: get_board_mem_timings
81 * Description: If we use SPL then there is no x-loader nor config header 82 * Description: If we use SPL then there is no x-loader nor config header
82 * so we have to setup the DDR timings ourself on both banks. 83 * so we have to setup the DDR timings ourself on both banks.
83 */ 84 */
84 void get_board_mem_timings(struct board_sdrc_timings *timings) 85 void get_board_mem_timings(struct board_sdrc_timings *timings)
85 { 86 {
86 int mfr, id, err = identify_nand_chip(&mfr, &id); 87 int mfr, id, err = identify_nand_chip(&mfr, &id);
87 88
88 timings->mr = MICRON_V_MR_165; 89 timings->mr = MICRON_V_MR_165;
89 if (!err) { 90 if (!err) {
90 switch (mfr) { 91 switch (mfr) {
91 case NAND_MFR_HYNIX: 92 case NAND_MFR_HYNIX:
92 timings->mcfg = HYNIX_V_MCFG_200(256 << 20); 93 timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
93 timings->ctrla = HYNIX_V_ACTIMA_200; 94 timings->ctrla = HYNIX_V_ACTIMA_200;
94 timings->ctrlb = HYNIX_V_ACTIMB_200; 95 timings->ctrlb = HYNIX_V_ACTIMB_200;
95 break; 96 break;
96 case NAND_MFR_MICRON: 97 case NAND_MFR_MICRON:
97 timings->mcfg = MICRON_V_MCFG_200(256 << 20); 98 timings->mcfg = MICRON_V_MCFG_200(256 << 20);
98 timings->ctrla = MICRON_V_ACTIMA_200; 99 timings->ctrla = MICRON_V_ACTIMA_200;
99 timings->ctrlb = MICRON_V_ACTIMB_200; 100 timings->ctrlb = MICRON_V_ACTIMB_200;
100 break; 101 break;
101 default: 102 default:
102 /* Should not happen... */ 103 /* Should not happen... */
103 break; 104 break;
104 } 105 }
105 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 106 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
106 gpmc_cs0_flash = MTD_DEV_TYPE_NAND; 107 gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
107 } else { 108 } else {
108 if (get_cpu_family() == CPU_OMAP34XX) { 109 if (get_cpu_family() == CPU_OMAP34XX) {
109 timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); 110 timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
110 timings->ctrla = NUMONYX_V_ACTIMA_165; 111 timings->ctrla = NUMONYX_V_ACTIMA_165;
111 timings->ctrlb = NUMONYX_V_ACTIMB_165; 112 timings->ctrlb = NUMONYX_V_ACTIMB_165;
112 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 113 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
113 } else { 114 } else {
114 timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); 115 timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
115 timings->ctrla = NUMONYX_V_ACTIMA_200; 116 timings->ctrla = NUMONYX_V_ACTIMA_200;
116 timings->ctrlb = NUMONYX_V_ACTIMB_200; 117 timings->ctrlb = NUMONYX_V_ACTIMB_200;
117 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 118 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
118 } 119 }
119 gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; 120 gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
120 } 121 }
121 } 122 }
122 123
123 #ifdef CONFIG_SPL_OS_BOOT 124 #ifdef CONFIG_SPL_OS_BOOT
124 int spl_start_uboot(void) 125 int spl_start_uboot(void)
125 { 126 {
126 /* break into full u-boot on 'c' */ 127 /* break into full u-boot on 'c' */
127 if (serial_tstc() && serial_getc() == 'c') 128 if (serial_tstc() && serial_getc() == 'c')
128 return 1; 129 return 1;
129 130
130 return 0; 131 return 0;
131 } 132 }
132 #endif 133 #endif
133 #endif 134 #endif
134 135
135 int onenand_board_init(struct mtd_info *mtd) 136 int onenand_board_init(struct mtd_info *mtd)
136 { 137 {
137 if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) { 138 if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) {
138 struct onenand_chip *this = mtd->priv; 139 struct onenand_chip *this = mtd->priv;
139 this->base = (void *)CONFIG_SYS_ONENAND_BASE; 140 this->base = (void *)CONFIG_SYS_ONENAND_BASE;
140 return 0; 141 return 0;
141 } 142 }
142 return 1; 143 return 1;
143 } 144 }
144 145
145 #if defined(CONFIG_CMD_NET) 146 #if defined(CONFIG_CMD_NET)
146 static void reset_net_chip(int gpio) 147 static void reset_net_chip(int gpio)
147 { 148 {
148 if (!gpio_request(gpio, "eth nrst")) { 149 if (!gpio_request(gpio, "eth nrst")) {
149 gpio_direction_output(gpio, 1); 150 gpio_direction_output(gpio, 1);
150 udelay(1); 151 udelay(1);
151 gpio_set_value(gpio, 0); 152 gpio_set_value(gpio, 0);
152 udelay(40); 153 udelay(40);
153 gpio_set_value(gpio, 1); 154 gpio_set_value(gpio, 1);
154 mdelay(10); 155 mdelay(10);
155 } 156 }
156 } 157 }
157 158
158 /* 159 /*
159 * Routine: setup_net_chip 160 * Routine: setup_net_chip
160 * Description: Setting up the configuration GPMC registers specific to the 161 * Description: Setting up the configuration GPMC registers specific to the
161 * Ethernet hardware. 162 * Ethernet hardware.
162 */ 163 */
163 static void setup_net_chip(void) 164 static void setup_net_chip(void)
164 { 165 {
165 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; 166 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
166 static const u32 gpmc_lan_config[] = { 167 static const u32 gpmc_lan_config[] = {
167 NET_LAN9221_GPMC_CONFIG1, 168 NET_LAN9221_GPMC_CONFIG1,
168 NET_LAN9221_GPMC_CONFIG2, 169 NET_LAN9221_GPMC_CONFIG2,
169 NET_LAN9221_GPMC_CONFIG3, 170 NET_LAN9221_GPMC_CONFIG3,
170 NET_LAN9221_GPMC_CONFIG4, 171 NET_LAN9221_GPMC_CONFIG4,
171 NET_LAN9221_GPMC_CONFIG5, 172 NET_LAN9221_GPMC_CONFIG5,
172 NET_LAN9221_GPMC_CONFIG6, 173 NET_LAN9221_GPMC_CONFIG6,
173 }; 174 };
174 175
175 enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 176 enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
176 CONFIG_SMC911X_BASE, GPMC_SIZE_16M); 177 CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
177 178
178 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ 179 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
179 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); 180 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
180 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ 181 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
181 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); 182 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
182 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ 183 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
183 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, 184 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
184 &ctrl_base->gpmc_nadv_ale); 185 &ctrl_base->gpmc_nadv_ale);
185 186
186 reset_net_chip(64); 187 reset_net_chip(64);
187 } 188 }
188 189
189 int board_eth_init(bd_t *bis) 190 int board_eth_init(bd_t *bis)
190 { 191 {
191 #ifdef CONFIG_SMC911X 192 #ifdef CONFIG_SMC911X
192 return smc911x_initialize(0, CONFIG_SMC911X_BASE); 193 return smc911x_initialize(0, CONFIG_SMC911X_BASE);
193 #else 194 #else
194 return 0; 195 return 0;
195 #endif 196 #endif
196 } 197 }
197 #else 198 #else
198 static inline void setup_net_chip(void) {} 199 static inline void setup_net_chip(void) {}
199 #endif 200 #endif
200 201
201 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 202 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
202 int board_mmc_init(bd_t *bis) 203 int board_mmc_init(bd_t *bis)
203 { 204 {
204 return omap_mmc_init(0, 0, 0, -1, -1); 205 return omap_mmc_init(0, 0, 0, -1, -1);
205 } 206 }
206 #endif 207 #endif
207 208
208 #if defined(CONFIG_GENERIC_MMC) 209 #if defined(CONFIG_GENERIC_MMC)
209 void board_mmc_power_init(void) 210 void board_mmc_power_init(void)
210 { 211 {
211 twl4030_power_mmc_init(0); 212 twl4030_power_mmc_init(0);
212 } 213 }
213 #endif 214 #endif
214 215
215 #ifdef CONFIG_OF_BOARD_SETUP 216 #ifdef CONFIG_OF_BOARD_SETUP
216 int ft_board_setup(void *blob, bd_t *bd) 217 int ft_board_setup(void *blob, bd_t *bd)
217 { 218 {
218 #ifdef CONFIG_FDT_FIXUP_PARTITIONS 219 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
219 static struct node_info nodes[] = { 220 static struct node_info nodes[] = {
220 { "ti,omap2-nand", MTD_DEV_TYPE_NAND, }, 221 { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
221 { "ti,omap2-onenand", MTD_DEV_TYPE_ONENAND, }, 222 { "ti,omap2-onenand", MTD_DEV_TYPE_ONENAND, },
222 }; 223 };
223 224
224 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); 225 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
225 #endif 226 #endif
226 return 0; 227 return 0;
227 } 228 }
228 #endif 229 #endif
229 230
230 void set_fdt(void) 231 void set_fdt(void)
231 { 232 {
232 switch (gd->bd->bi_arch_number) { 233 switch (gd->bd->bi_arch_number) {
233 case MACH_TYPE_IGEP0020: 234 case MACH_TYPE_IGEP0020:
234 setenv("fdtfile", "omap3-igep0020.dtb"); 235 setenv("fdtfile", "omap3-igep0020.dtb");
235 break; 236 break;
236 case MACH_TYPE_IGEP0030: 237 case MACH_TYPE_IGEP0030:
237 setenv("fdtfile", "omap3-igep0030.dtb"); 238 setenv("fdtfile", "omap3-igep0030.dtb");
238 break; 239 break;
239 } 240 }
240 } 241 }
241 242
242 /* 243 /*
243 * Routine: misc_init_r 244 * Routine: misc_init_r
244 * Description: Configure board specific parts 245 * Description: Configure board specific parts
245 */ 246 */
246 int misc_init_r(void) 247 int misc_init_r(void)
247 { 248 {
248 twl4030_power_init(); 249 twl4030_power_init();
249 250
250 setup_net_chip(); 251 setup_net_chip();
251 252
252 omap_die_id_display(); 253 omap_die_id_display();
253 254
254 set_fdt(); 255 set_fdt();
255 256
256 return 0; 257 return 0;
257 } 258 }
258 259
259 void board_mtdparts_default(const char **mtdids, const char **mtdparts) 260 void board_mtdparts_default(const char **mtdids, const char **mtdparts)
260 { 261 {
261 struct mtd_info *mtd = get_mtd_device(NULL, 0); 262 struct mtd_info *mtd = get_mtd_device(NULL, 0);
262 if (mtd) { 263 if (mtd) {
263 static char ids[24]; 264 static char ids[24];
264 static char parts[48]; 265 static char parts[48];
265 const char *linux_name = "omap2-nand"; 266 const char *linux_name = "omap2-nand";
266 if (strncmp(mtd->name, "onenand0", 8) == 0) 267 if (strncmp(mtd->name, "onenand0", 8) == 0)
267 linux_name = "omap2-onenand"; 268 linux_name = "omap2-onenand";
268 snprintf(ids, sizeof(ids), "%s=%s", mtd->name, linux_name); 269 snprintf(ids, sizeof(ids), "%s=%s", mtd->name, linux_name);
269 snprintf(parts, sizeof(parts), "mtdparts=%s:%dk(SPL),-(UBI)", 270 snprintf(parts, sizeof(parts), "mtdparts=%s:%dk(SPL),-(UBI)",
270 linux_name, 4 * mtd->erasesize >> 10); 271 linux_name, 4 * mtd->erasesize >> 10);
271 *mtdids = ids; 272 *mtdids = ids;
272 *mtdparts = parts; 273 *mtdparts = parts;
273 } 274 }
274 } 275 }
275 276
276 /* 277 /*
277 * Routine: set_muxconf_regs 278 * Routine: set_muxconf_regs
278 * Description: Setting up the configuration Mux registers specific to the 279 * Description: Setting up the configuration Mux registers specific to the
279 * hardware. Many pins need to be moved from protect to primary 280 * hardware. Many pins need to be moved from protect to primary
280 * mode. 281 * mode.
281 */ 282 */
282 void set_muxconf_regs(void) 283 void set_muxconf_regs(void)
283 { 284 {
284 MUX_DEFAULT(); 285 MUX_DEFAULT();
285 286
286 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) 287 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
287 MUX_IGEP0020(); 288 MUX_IGEP0020();
288 #endif 289 #endif
289 290
290 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) 291 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
291 MUX_IGEP0030(); 292 MUX_IGEP0030();
292 #endif 293 #endif
293 } 294 }
294 295
board/lg/sniper/sniper.c
Diff comments   View file @ 17fa032
1 /* 1 /*
2 * LG Optimus Black codename sniper board 2 * LG Optimus Black codename sniper board
3 * 3 *
4 * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr> 4 * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 */ 7 */
8 8
9 #include <config.h> 9 #include <config.h>
10 #include <common.h> 10 #include <common.h>
11 #include <dm.h> 11 #include <dm.h>
12 #include <linux/ctype.h> 12 #include <linux/ctype.h>
13 #include <linux/usb/musb.h> 13 #include <linux/usb/musb.h>
14 #include <asm/omap_musb.h> 14 #include <asm/omap_musb.h>
15 #include <asm/arch/mmc_host_def.h> 15 #include <asm/arch/mmc_host_def.h>
16 #include <asm/arch/sys_proto.h> 16 #include <asm/arch/sys_proto.h>
17 #include <asm/arch/mem.h> 17 #include <asm/arch/mem.h>
18 #include <asm/io.h> 18 #include <asm/io.h>
19 #include <ns16550.h> 19 #include <ns16550.h>
20 #include <twl4030.h> 20 #include <twl4030.h>
21 #include "sniper.h" 21 #include "sniper.h"
22 22
23 DECLARE_GLOBAL_DATA_PTR; 23 DECLARE_GLOBAL_DATA_PTR;
24 24
25 const omap3_sysinfo sysinfo = { 25 const omap3_sysinfo sysinfo = {
26 .mtype = DDR_STACKED, 26 .mtype = DDR_STACKED,
27 .board_string = "sniper", 27 .board_string = "sniper",
28 .nand_string = "MMC" 28 .nand_string = "MMC"
29 }; 29 };
30 30
31 static const struct ns16550_platdata serial_omap_platdata = { 31 static const struct ns16550_platdata serial_omap_platdata = {
32 .base = OMAP34XX_UART3, 32 .base = OMAP34XX_UART3,
33 .reg_shift = 2, 33 .reg_shift = 2,
34 .clock = V_NS16550_CLK 34 .clock = V_NS16550_CLK,
35 .fcr = UART_FCR_DEFVAL,
35 }; 36 };
36 37
37 U_BOOT_DEVICE(sniper_serial) = { 38 U_BOOT_DEVICE(sniper_serial) = {
38 .name = "ns16550_serial", 39 .name = "ns16550_serial",
39 .platdata = &serial_omap_platdata 40 .platdata = &serial_omap_platdata
40 }; 41 };
41 42
42 static struct musb_hdrc_config musb_config = { 43 static struct musb_hdrc_config musb_config = {
43 .multipoint = 1, 44 .multipoint = 1,
44 .dyn_fifo = 1, 45 .dyn_fifo = 1,
45 .num_eps = 16, 46 .num_eps = 16,
46 .ram_bits = 12 47 .ram_bits = 12
47 }; 48 };
48 49
49 static struct omap_musb_board_data musb_board_data = { 50 static struct omap_musb_board_data musb_board_data = {
50 .interface_type = MUSB_INTERFACE_ULPI, 51 .interface_type = MUSB_INTERFACE_ULPI,
51 }; 52 };
52 53
53 static struct musb_hdrc_platform_data musb_platform_data = { 54 static struct musb_hdrc_platform_data musb_platform_data = {
54 .mode = MUSB_PERIPHERAL, 55 .mode = MUSB_PERIPHERAL,
55 .config = &musb_config, 56 .config = &musb_config,
56 .power = 100, 57 .power = 100,
57 .platform_ops = &omap2430_ops, 58 .platform_ops = &omap2430_ops,
58 .board_data = &musb_board_data, 59 .board_data = &musb_board_data,
59 }; 60 };
60 61
61 void set_muxconf_regs(void) 62 void set_muxconf_regs(void)
62 { 63 {
63 MUX_SNIPER(); 64 MUX_SNIPER();
64 } 65 }
65 66
66 #ifdef CONFIG_SPL_BUILD 67 #ifdef CONFIG_SPL_BUILD
67 void get_board_mem_timings(struct board_sdrc_timings *timings) 68 void get_board_mem_timings(struct board_sdrc_timings *timings)
68 { 69 {
69 timings->mcfg = HYNIX_V_MCFG_200(256 << 20); 70 timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
70 timings->ctrla = HYNIX_V_ACTIMA_200; 71 timings->ctrla = HYNIX_V_ACTIMA_200;
71 timings->ctrlb = HYNIX_V_ACTIMB_200; 72 timings->ctrlb = HYNIX_V_ACTIMB_200;
72 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 73 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
73 timings->mr = MICRON_V_MR_165; 74 timings->mr = MICRON_V_MR_165;
74 } 75 }
75 #endif 76 #endif
76 77
77 int board_init(void) 78 int board_init(void)
78 { 79 {
79 /* GPMC init */ 80 /* GPMC init */
80 gpmc_init(); 81 gpmc_init();
81 82
82 /* MACH number */ 83 /* MACH number */
83 gd->bd->bi_arch_number = 3000; 84 gd->bd->bi_arch_number = 3000;
84 85
85 /* ATAGs location */ 86 /* ATAGs location */
86 gd->bd->bi_boot_params = OMAP34XX_SDRC_CS0 + 0x100; 87 gd->bd->bi_boot_params = OMAP34XX_SDRC_CS0 + 0x100;
87 88
88 return 0; 89 return 0;
89 } 90 }
90 91
91 int misc_init_r(void) 92 int misc_init_r(void)
92 { 93 {
93 unsigned char keypad_matrix[64] = { 0 }; 94 unsigned char keypad_matrix[64] = { 0 };
94 char reboot_mode[2] = { 0 }; 95 char reboot_mode[2] = { 0 };
95 unsigned char keys[3]; 96 unsigned char keys[3];
96 unsigned char data = 0; 97 unsigned char data = 0;
97 int rc; 98 int rc;
98 99
99 /* Power button reset init */ 100 /* Power button reset init */
100 101
101 twl4030_power_reset_init(); 102 twl4030_power_reset_init();
102 103
103 /* Keypad */ 104 /* Keypad */
104 105
105 twl4030_keypad_scan((unsigned char *)&keypad_matrix); 106 twl4030_keypad_scan((unsigned char *)&keypad_matrix);
106 107
107 keys[0] = twl4030_keypad_key((unsigned char *)&keypad_matrix, 0, 0); 108 keys[0] = twl4030_keypad_key((unsigned char *)&keypad_matrix, 0, 0);
108 keys[1] = twl4030_keypad_key((unsigned char *)&keypad_matrix, 0, 1); 109 keys[1] = twl4030_keypad_key((unsigned char *)&keypad_matrix, 0, 1);
109 keys[2] = twl4030_keypad_key((unsigned char *)&keypad_matrix, 0, 2); 110 keys[2] = twl4030_keypad_key((unsigned char *)&keypad_matrix, 0, 2);
110 111
111 /* Reboot mode */ 112 /* Reboot mode */
112 113
113 rc = omap_reboot_mode(reboot_mode, sizeof(reboot_mode)); 114 rc = omap_reboot_mode(reboot_mode, sizeof(reboot_mode));
114 115
115 if (keys[0]) 116 if (keys[0])
116 reboot_mode[0] = 'r'; 117 reboot_mode[0] = 'r';
117 else if (keys[1]) 118 else if (keys[1])
118 reboot_mode[0] = 'b'; 119 reboot_mode[0] = 'b';
119 120
120 if (rc < 0 || reboot_mode[0] == 'o') { 121 if (rc < 0 || reboot_mode[0] == 'o') {
121 /* 122 /*
122 * When not rebooting, valid power on reasons are either the 123 * When not rebooting, valid power on reasons are either the
123 * power button, charger plug or USB plug. 124 * power button, charger plug or USB plug.
124 */ 125 */
125 126
126 data |= twl4030_input_power_button(); 127 data |= twl4030_input_power_button();
127 data |= twl4030_input_charger(); 128 data |= twl4030_input_charger();
128 data |= twl4030_input_usb(); 129 data |= twl4030_input_usb();
129 130
130 if (!data) 131 if (!data)
131 twl4030_power_off(); 132 twl4030_power_off();
132 } 133 }
133 134
134 if (reboot_mode[0] > 0 && isascii(reboot_mode[0])) { 135 if (reboot_mode[0] > 0 && isascii(reboot_mode[0])) {
135 if (!getenv("reboot-mode")) 136 if (!getenv("reboot-mode"))
136 setenv("reboot-mode", (char *)reboot_mode); 137 setenv("reboot-mode", (char *)reboot_mode);
137 } 138 }
138 139
139 omap_reboot_mode_clear(); 140 omap_reboot_mode_clear();
140 141
141 /* Serial number */ 142 /* Serial number */
142 143
143 omap_die_id_serial(); 144 omap_die_id_serial();
144 145
145 /* MUSB */ 146 /* MUSB */
146 147
147 musb_register(&musb_platform_data, &musb_board_data, (void *)MUSB_BASE); 148 musb_register(&musb_platform_data, &musb_board_data, (void *)MUSB_BASE);
148 149
149 return 0; 150 return 0;
150 } 151 }
151 152
152 u32 get_board_rev(void) 153 u32 get_board_rev(void)
153 { 154 {
154 /* Sold devices are expected to be at least revision F. */ 155 /* Sold devices are expected to be at least revision F. */
155 return 6; 156 return 6;
156 } 157 }
157 158
158 void get_board_serial(struct tag_serialnr *serialnr) 159 void get_board_serial(struct tag_serialnr *serialnr)
159 { 160 {
160 omap_die_id_get_board_serial(serialnr); 161 omap_die_id_get_board_serial(serialnr);
161 } 162 }
162 163
163 void reset_misc(void) 164 void reset_misc(void)
164 { 165 {
165 char reboot_mode[2] = { 0 }; 166 char reboot_mode[2] = { 0 };
166 167
167 /* 168 /*
168 * Valid resets must contain the reboot mode magic, but we must not 169 * Valid resets must contain the reboot mode magic, but we must not
169 * override it when set previously (e.g. reboot to bootloader). 170 * override it when set previously (e.g. reboot to bootloader).
170 */ 171 */
171 172
172 omap_reboot_mode(reboot_mode, sizeof(reboot_mode)); 173 omap_reboot_mode(reboot_mode, sizeof(reboot_mode));
173 omap_reboot_mode_store(reboot_mode); 174 omap_reboot_mode_store(reboot_mode);
174 } 175 }
175 176
176 int fb_set_reboot_flag(void) 177 int fb_set_reboot_flag(void)
177 { 178 {
178 return omap_reboot_mode_store("b"); 179 return omap_reboot_mode_store("b");
179 } 180 }
180 181
181 #ifndef CONFIG_SPL_BUILD 182 #ifndef CONFIG_SPL_BUILD
182 int board_mmc_init(bd_t *bis) 183 int board_mmc_init(bd_t *bis)
183 { 184 {
184 return omap_mmc_init(1, 0, 0, -1, -1); 185 return omap_mmc_init(1, 0, 0, -1, -1);
185 } 186 }
186 #endif 187 #endif
187 188
188 void board_mmc_power_init(void) 189 void board_mmc_power_init(void)
189 { 190 {
190 twl4030_power_mmc_init(1); 191 twl4030_power_mmc_init(1);
191 } 192 }
192 193
board/logicpd/omap3som/omap3logic.c
Diff comments   View file @ 17fa032
1 /* 1 /*
2 * (C) Copyright 2011 2 * (C) Copyright 2011
3 * Logic Product Development <www.logicpd.com> 3 * Logic Product Development <www.logicpd.com>
4 * 4 *
5 * Author : 5 * Author :
6 * Peter Barada <peter.barada@logicpd.com> 6 * Peter Barada <peter.barada@logicpd.com>
7 * 7 *
8 * Derived from Beagle Board and 3430 SDP code by 8 * Derived from Beagle Board and 3430 SDP code by
9 * Richard Woodruff <r-woodruff2@ti.com> 9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com> 10 * Syed Mohammed Khasim <khasim@ti.com>
11 * 11 *
12 * SPDX-License-Identifier: GPL-2.0+ 12 * SPDX-License-Identifier: GPL-2.0+
13 */ 13 */
14 #include <common.h> 14 #include <common.h>
15 #include <dm.h> 15 #include <dm.h>
16 #include <ns16550.h> 16 #include <ns16550.h>
17 #include <netdev.h> 17 #include <netdev.h>
18 #include <flash.h> 18 #include <flash.h>
19 #include <nand.h> 19 #include <nand.h>
20 #include <i2c.h> 20 #include <i2c.h>
21 #include <twl4030.h> 21 #include <twl4030.h>
22 #include <asm/io.h> 22 #include <asm/io.h>
23 #include <asm/arch/mmc_host_def.h> 23 #include <asm/arch/mmc_host_def.h>
24 #include <asm/arch/mux.h> 24 #include <asm/arch/mux.h>
25 #include <asm/arch/mem.h> 25 #include <asm/arch/mem.h>
26 #include <asm/arch/sys_proto.h> 26 #include <asm/arch/sys_proto.h>
27 #include <asm/gpio.h> 27 #include <asm/gpio.h>
28 #include <asm/mach-types.h> 28 #include <asm/mach-types.h>
29 #include <linux/mtd/nand.h> 29 #include <linux/mtd/nand.h>
30 #include <asm/omap_musb.h> 30 #include <asm/omap_musb.h>
31 #include <linux/errno.h> 31 #include <linux/errno.h>
32 #include <linux/usb/ch9.h> 32 #include <linux/usb/ch9.h>
33 #include <linux/usb/gadget.h> 33 #include <linux/usb/gadget.h>
34 #include <linux/usb/musb.h> 34 #include <linux/usb/musb.h>
35 #include "omap3logic.h" 35 #include "omap3logic.h"
36 36
37 DECLARE_GLOBAL_DATA_PTR; 37 DECLARE_GLOBAL_DATA_PTR;
38 38
39 #define CONTROL_WKUP_CTRL 0x48002a5c 39 #define CONTROL_WKUP_CTRL 0x48002a5c
40 #define GPIO_IO_PWRDNZ (1 << 6) 40 #define GPIO_IO_PWRDNZ (1 << 6)
41 #define PBIASLITEVMODE1 (1 << 8) 41 #define PBIASLITEVMODE1 (1 << 8)
42 42
43 /* 43 /*
44 * two dimensional array of strucures containining board name and Linux 44 * two dimensional array of strucures containining board name and Linux
45 * machine IDs; row it selected based on CPU column is slected based 45 * machine IDs; row it selected based on CPU column is slected based
46 * on hsusb0_data5 pin having a pulldown resistor 46 * on hsusb0_data5 pin having a pulldown resistor
47 */ 47 */
48 48
49 static const struct ns16550_platdata omap3logic_serial = { 49 static const struct ns16550_platdata omap3logic_serial = {
50 .base = OMAP34XX_UART1, 50 .base = OMAP34XX_UART1,
51 .reg_shift = 2, 51 .reg_shift = 2,
52 .clock = V_NS16550_CLK 52 .clock = V_NS16550_CLK,
53 .fcr = UART_FCR_DEFVAL,
53 }; 54 };
54 55
55 U_BOOT_DEVICE(omap3logic_uart) = { 56 U_BOOT_DEVICE(omap3logic_uart) = {
56 "ns16550_serial", 57 "ns16550_serial",
57 &omap3logic_serial 58 &omap3logic_serial
58 }; 59 };
59 60
60 static struct board_id { 61 static struct board_id {
61 char *name; 62 char *name;
62 int machine_id; 63 int machine_id;
63 char *fdtfile; 64 char *fdtfile;
64 } boards[2][2] = { 65 } boards[2][2] = {
65 { 66 {
66 { 67 {
67 .name = "OMAP35xx SOM LV", 68 .name = "OMAP35xx SOM LV",
68 .machine_id = MACH_TYPE_OMAP3530_LV_SOM, 69 .machine_id = MACH_TYPE_OMAP3530_LV_SOM,
69 .fdtfile = "logicpd-som-lv-35xx-devkit.dtb", 70 .fdtfile = "logicpd-som-lv-35xx-devkit.dtb",
70 }, 71 },
71 { 72 {
72 .name = "OMAP35xx Torpedo", 73 .name = "OMAP35xx Torpedo",
73 .machine_id = MACH_TYPE_OMAP3_TORPEDO, 74 .machine_id = MACH_TYPE_OMAP3_TORPEDO,
74 .fdtfile = "logicpd-torpedo-35xx-devkit.dtb", 75 .fdtfile = "logicpd-torpedo-35xx-devkit.dtb",
75 }, 76 },
76 }, 77 },
77 { 78 {
78 { 79 {
79 .name = "DM37xx SOM LV", 80 .name = "DM37xx SOM LV",
80 .fdtfile = "logicpd-som-lv-37xx-devkit.dtb", 81 .fdtfile = "logicpd-som-lv-37xx-devkit.dtb",
81 }, 82 },
82 { 83 {
83 .name = "DM37xx Torpedo", 84 .name = "DM37xx Torpedo",
84 .fdtfile = "logicpd-torpedo-37xx-devkit.dtb", 85 .fdtfile = "logicpd-torpedo-37xx-devkit.dtb",
85 }, 86 },
86 }, 87 },
87 }; 88 };
88 89
89 #ifdef CONFIG_SPL_OS_BOOT 90 #ifdef CONFIG_SPL_OS_BOOT
90 int spl_start_uboot(void) 91 int spl_start_uboot(void)
91 { 92 {
92 /* break into full u-boot on 'c' */ 93 /* break into full u-boot on 'c' */
93 return serial_tstc() && serial_getc() == 'c'; 94 return serial_tstc() && serial_getc() == 'c';
94 } 95 }
95 #endif 96 #endif
96 97
97 #if defined(CONFIG_SPL_BUILD) 98 #if defined(CONFIG_SPL_BUILD)
98 /* 99 /*
99 * Routine: get_board_mem_timings 100 * Routine: get_board_mem_timings
100 * Description: If we use SPL then there is no x-loader nor config header 101 * Description: If we use SPL then there is no x-loader nor config header
101 * so we have to setup the DDR timings ourself on the first bank. This 102 * so we have to setup the DDR timings ourself on the first bank. This
102 * provides the timing values back to the function that configures 103 * provides the timing values back to the function that configures
103 * the memory. 104 * the memory.
104 */ 105 */
105 void get_board_mem_timings(struct board_sdrc_timings *timings) 106 void get_board_mem_timings(struct board_sdrc_timings *timings)
106 { 107 {
107 timings->mr = MICRON_V_MR_165; 108 timings->mr = MICRON_V_MR_165;
108 /* 256MB DDR */ 109 /* 256MB DDR */
109 timings->mcfg = MICRON_V_MCFG_200(256 << 20); 110 timings->mcfg = MICRON_V_MCFG_200(256 << 20);
110 timings->ctrla = MICRON_V_ACTIMA_200; 111 timings->ctrla = MICRON_V_ACTIMA_200;
111 timings->ctrlb = MICRON_V_ACTIMB_200; 112 timings->ctrlb = MICRON_V_ACTIMB_200;
112 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 113 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
113 } 114 }
114 #endif 115 #endif
115 116
116 #ifdef CONFIG_USB_MUSB_OMAP2PLUS 117 #ifdef CONFIG_USB_MUSB_OMAP2PLUS
117 static struct musb_hdrc_config musb_config = { 118 static struct musb_hdrc_config musb_config = {
118 .multipoint = 1, 119 .multipoint = 1,
119 .dyn_fifo = 1, 120 .dyn_fifo = 1,
120 .num_eps = 16, 121 .num_eps = 16,
121 .ram_bits = 12, 122 .ram_bits = 12,
122 }; 123 };
123 124
124 static struct omap_musb_board_data musb_board_data = { 125 static struct omap_musb_board_data musb_board_data = {
125 .interface_type = MUSB_INTERFACE_ULPI, 126 .interface_type = MUSB_INTERFACE_ULPI,
126 }; 127 };
127 128
128 static struct musb_hdrc_platform_data musb_plat = { 129 static struct musb_hdrc_platform_data musb_plat = {
129 #if defined(CONFIG_USB_MUSB_HOST) 130 #if defined(CONFIG_USB_MUSB_HOST)
130 .mode = MUSB_HOST, 131 .mode = MUSB_HOST,
131 #elif defined(CONFIG_USB_MUSB_GADGET) 132 #elif defined(CONFIG_USB_MUSB_GADGET)
132 .mode = MUSB_PERIPHERAL, 133 .mode = MUSB_PERIPHERAL,
133 #else 134 #else
134 #error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET" 135 #error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET"
135 #endif 136 #endif
136 .config = &musb_config, 137 .config = &musb_config,
137 .power = 100, 138 .power = 100,
138 .platform_ops = &omap2430_ops, 139 .platform_ops = &omap2430_ops,
139 .board_data = &musb_board_data, 140 .board_data = &musb_board_data,
140 }; 141 };
141 #endif 142 #endif
142 143
143 144
144 /* 145 /*
145 * Routine: misc_init_r 146 * Routine: misc_init_r
146 * Description: Configure board specific parts 147 * Description: Configure board specific parts
147 */ 148 */
148 int misc_init_r(void) 149 int misc_init_r(void)
149 { 150 {
150 twl4030_power_init(); 151 twl4030_power_init();
151 omap_die_id_display(); 152 omap_die_id_display();
152 153
153 #ifdef CONFIG_USB_MUSB_OMAP2PLUS 154 #ifdef CONFIG_USB_MUSB_OMAP2PLUS
154 musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE); 155 musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE);
155 #endif 156 #endif
156 157
157 return 0; 158 return 0;
158 } 159 }
159 160
160 /* 161 /*
161 * BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM LV 162 * BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM LV
162 */ 163 */
163 #define BOARD_ID_GPIO 189 /* hsusb0_data5 pin */ 164 #define BOARD_ID_GPIO 189 /* hsusb0_data5 pin */
164 165
165 /* 166 /*
166 * Routine: board_init 167 * Routine: board_init
167 * Description: Early hardware init. 168 * Description: Early hardware init.
168 */ 169 */
169 int board_init(void) 170 int board_init(void)
170 { 171 {
171 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 172 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
172 173
173 /* boot param addr */ 174 /* boot param addr */
174 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 175 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
175 176
176 return 0; 177 return 0;
177 } 178 }
178 179
179 #ifdef CONFIG_BOARD_LATE_INIT 180 #ifdef CONFIG_BOARD_LATE_INIT
180 int board_late_init(void) 181 int board_late_init(void)
181 { 182 {
182 struct board_id *board; 183 struct board_id *board;
183 unsigned int val; 184 unsigned int val;
184 185
185 /* 186 /*
186 * To identify between a SOM LV and Torpedo module, 187 * To identify between a SOM LV and Torpedo module,
187 * a pulldown resistor is on hsusb0_data5 for the SOM LV module. 188 * a pulldown resistor is on hsusb0_data5 for the SOM LV module.
188 * Drive the pin (and let it soak), then read it back. 189 * Drive the pin (and let it soak), then read it back.
189 * If the pin is still high its a Torpedo. If low its a SOM LV 190 * If the pin is still high its a Torpedo. If low its a SOM LV
190 */ 191 */
191 192
192 /* Mux hsusb0_data5 as a GPIO */ 193 /* Mux hsusb0_data5 as a GPIO */
193 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M4)); 194 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M4));
194 195
195 if (gpio_request(BOARD_ID_GPIO, "husb0_data5.gpio_189") == 0) { 196 if (gpio_request(BOARD_ID_GPIO, "husb0_data5.gpio_189") == 0) {
196 197
197 /* 198 /*
198 * Drive BOARD_ID_GPIO - the pulldown resistor on the SOM LV 199 * Drive BOARD_ID_GPIO - the pulldown resistor on the SOM LV
199 * will drain the voltage. 200 * will drain the voltage.
200 */ 201 */
201 gpio_direction_output(BOARD_ID_GPIO, 0); 202 gpio_direction_output(BOARD_ID_GPIO, 0);
202 gpio_set_value(BOARD_ID_GPIO, 1); 203 gpio_set_value(BOARD_ID_GPIO, 1);
203 204
204 /* Let it soak for a bit */ 205 /* Let it soak for a bit */
205 sdelay(0x100); 206 sdelay(0x100);
206 207
207 /* 208 /*
208 * Read state of BOARD_ID_GPIO as an input and if its set. 209 * Read state of BOARD_ID_GPIO as an input and if its set.
209 * If so the board is a Torpedo 210 * If so the board is a Torpedo
210 */ 211 */
211 gpio_direction_input(BOARD_ID_GPIO); 212 gpio_direction_input(BOARD_ID_GPIO);
212 val = gpio_get_value(BOARD_ID_GPIO); 213 val = gpio_get_value(BOARD_ID_GPIO);
213 gpio_free(BOARD_ID_GPIO); 214 gpio_free(BOARD_ID_GPIO);
214 215
215 board = &boards[!!(get_cpu_family() == CPU_OMAP36XX)][!!val]; 216 board = &boards[!!(get_cpu_family() == CPU_OMAP36XX)][!!val];
216 printf("Board: %s\n", board->name); 217 printf("Board: %s\n", board->name);
217 218
218 /* Set the machine_id passed to Linux */ 219 /* Set the machine_id passed to Linux */
219 if (board->machine_id) 220 if (board->machine_id)
220 gd->bd->bi_arch_number = board->machine_id; 221 gd->bd->bi_arch_number = board->machine_id;
221 222
222 /* If the user has not set fdtimage, set the default */ 223 /* If the user has not set fdtimage, set the default */
223 if (!getenv("fdtimage")) 224 if (!getenv("fdtimage"))
224 setenv("fdtimage", board->fdtfile); 225 setenv("fdtimage", board->fdtfile);
225 } 226 }
226 227
227 /* restore hsusb0_data5 pin as hsusb0_data5 */ 228 /* restore hsusb0_data5 pin as hsusb0_data5 */
228 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); 229 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
229 return 0; 230 return 0;
230 } 231 }
231 #endif 232 #endif
232 233
233 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 234 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
234 int board_mmc_init(bd_t *bis) 235 int board_mmc_init(bd_t *bis)
235 { 236 {
236 return omap_mmc_init(0, 0, 0, -1, -1); 237 return omap_mmc_init(0, 0, 0, -1, -1);
237 } 238 }
238 #endif 239 #endif
239 240
240 #if defined(CONFIG_GENERIC_MMC) 241 #if defined(CONFIG_GENERIC_MMC)
241 void board_mmc_power_init(void) 242 void board_mmc_power_init(void)
242 { 243 {
243 twl4030_power_mmc_init(0); 244 twl4030_power_mmc_init(0);
244 } 245 }
245 #endif 246 #endif
246 247
247 #ifdef CONFIG_SMC911X 248 #ifdef CONFIG_SMC911X
248 /* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */ 249 /* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
249 static const u32 gpmc_lan92xx_config[] = { 250 static const u32 gpmc_lan92xx_config[] = {
250 NET_LAN92XX_GPMC_CONFIG1, 251 NET_LAN92XX_GPMC_CONFIG1,
251 NET_LAN92XX_GPMC_CONFIG2, 252 NET_LAN92XX_GPMC_CONFIG2,
252 NET_LAN92XX_GPMC_CONFIG3, 253 NET_LAN92XX_GPMC_CONFIG3,
253 NET_LAN92XX_GPMC_CONFIG4, 254 NET_LAN92XX_GPMC_CONFIG4,
254 NET_LAN92XX_GPMC_CONFIG5, 255 NET_LAN92XX_GPMC_CONFIG5,
255 NET_LAN92XX_GPMC_CONFIG6, 256 NET_LAN92XX_GPMC_CONFIG6,
256 }; 257 };
257 258
258 int board_eth_init(bd_t *bis) 259 int board_eth_init(bd_t *bis)
259 { 260 {
260 enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1], 261 enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
261 CONFIG_SMC911X_BASE, GPMC_SIZE_16M); 262 CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
262 263
263 return smc911x_initialize(0, CONFIG_SMC911X_BASE); 264 return smc911x_initialize(0, CONFIG_SMC911X_BASE);
264 } 265 }
265 #endif 266 #endif
266 267
267 /* 268 /*
268 * IEN - Input Enable 269 * IEN - Input Enable
269 * IDIS - Input Disable 270 * IDIS - Input Disable
270 * PTD - Pull type Down 271 * PTD - Pull type Down
271 * PTU - Pull type Up 272 * PTU - Pull type Up
272 * DIS - Pull type selection is inactive 273 * DIS - Pull type selection is inactive
273 * EN - Pull type selection is active 274 * EN - Pull type selection is active
274 * M0 - Mode 0 275 * M0 - Mode 0
275 * The commented string gives the final mux configuration for that pin 276 * The commented string gives the final mux configuration for that pin
276 */ 277 */
277 278
278 /* 279 /*
279 * Routine: set_muxconf_regs 280 * Routine: set_muxconf_regs
280 * Description: Setting up the configuration Mux registers specific to the 281 * Description: Setting up the configuration Mux registers specific to the
281 * hardware. Many pins need to be moved from protect to primary 282 * hardware. Many pins need to be moved from protect to primary
282 * mode. 283 * mode.
283 */ 284 */
284 void set_muxconf_regs(void) 285 void set_muxconf_regs(void)
285 { 286 {
286 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/ 287 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/
287 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/ 288 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/
288 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/ 289 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/
289 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/ 290 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/
290 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/ 291 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/
291 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/ 292 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/
292 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/ 293 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/
293 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/ 294 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/
294 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/ 295 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/
295 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/ 296 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/
296 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/ 297 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/
297 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/ 298 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/
298 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/ 299 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/
299 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/ 300 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/
300 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/ 301 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/
301 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/ 302 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/
302 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/ 303 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/
303 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/ 304 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/
304 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/ 305 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/
305 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/ 306 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/
306 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/ 307 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/
307 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/ 308 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/
308 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/ 309 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/
309 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/ 310 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/
310 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/ 311 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/
311 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/ 312 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/
312 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/ 313 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/
313 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/ 314 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/
314 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/ 315 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/
315 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/ 316 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/
316 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/ 317 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/
317 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/ 318 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/
318 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/ 319 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/
319 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/ 320 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/
320 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/ 321 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/
321 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/ 322 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/
322 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/ 323 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/
323 MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/ 324 MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/
324 MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/ 325 MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/
325 326
326 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/ 327 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/
327 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/ 328 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/
328 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/ 329 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/
329 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/ 330 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/
330 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/ 331 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/
331 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/ 332 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/
332 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/ 333 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/
333 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/ 334 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/
334 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/ 335 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/
335 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/ 336 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/
336 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/ 337 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/
337 MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/ 338 MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/
338 MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/ 339 MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/
339 MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/ 340 MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/
340 MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/ 341 MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/
341 MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/ 342 MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/
342 MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/ 343 MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/
343 MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/ 344 MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/
344 MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/ 345 MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/
345 MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/ 346 MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/
346 MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/ 347 MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/
347 MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/ 348 MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/
348 MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/ 349 MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/
349 MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/ 350 MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/
350 MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/ 351 MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/
351 MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/ 352 MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/
352 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/ 353 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/
353 MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)); /*GPMC_nCS1*/ 354 MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)); /*GPMC_nCS1*/
354 MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)); /*GPMC_nCS2*/ 355 MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)); /*GPMC_nCS2*/
355 MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)); /*GPMC_nCS3*/ 356 MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)); /*GPMC_nCS3*/
356 MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/ 357 MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/
357 MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)); /*GPMC_nCS5*/ 358 MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)); /*GPMC_nCS5*/
358 MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M0)); /*GPMC_nCS6*/ 359 MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M0)); /*GPMC_nCS6*/
359 MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)); /*GPMC_nCS7*/ 360 MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)); /*GPMC_nCS7*/
360 MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)); /*GPMC_CLK*/ 361 MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)); /*GPMC_CLK*/
361 MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*GPMC_nADV_ALE*/ 362 MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*GPMC_nADV_ALE*/
362 MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*GPMC_nOE*/ 363 MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*GPMC_nOE*/
363 MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*GPMC_nWE*/ 364 MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*GPMC_nWE*/
364 MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*GPMC_nBE0_CLE*/ 365 MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*GPMC_nBE0_CLE*/
365 MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)); /*GPMC_nBE1*/ 366 MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)); /*GPMC_nBE1*/
366 MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*GPMC_nWP*/ 367 MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*GPMC_nWP*/
367 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*GPMC_WAIT0*/ 368 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*GPMC_WAIT0*/
368 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); /*GPMC_WAIT1*/ 369 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); /*GPMC_WAIT1*/
369 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)); /*GPIO_64*/ 370 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)); /*GPIO_64*/
370 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)); /*GPMC_WAIT3*/ 371 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)); /*GPMC_WAIT3*/
371 372
372 MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)); /*CAM_HS */ 373 MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)); /*CAM_HS */
373 MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)); /*CAM_VS */ 374 MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)); /*CAM_VS */
374 MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)); /*CAM_XCLKA*/ 375 MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)); /*CAM_XCLKA*/
375 MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)); /*CAM_PCLK*/ 376 MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)); /*CAM_PCLK*/
376 MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)); /*GPIO_98*/ 377 MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)); /*GPIO_98*/
377 MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)); /*CAM_D0*/ 378 MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)); /*CAM_D0*/
378 MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)); /*CAM_D1*/ 379 MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)); /*CAM_D1*/
379 MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)); /*CAM_D2*/ 380 MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)); /*CAM_D2*/
380 MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)); /*CAM_D3*/ 381 MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)); /*CAM_D3*/
381 MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)); /*CAM_D4*/ 382 MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)); /*CAM_D4*/
382 MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)); /*CAM_D5*/ 383 MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)); /*CAM_D5*/
383 MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)); /*CAM_D6*/ 384 MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)); /*CAM_D6*/
384 MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)); /*CAM_D7*/ 385 MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)); /*CAM_D7*/
385 MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)); /*CAM_D8*/ 386 MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)); /*CAM_D8*/
386 MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)); /*CAM_D9*/ 387 MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)); /*CAM_D9*/
387 MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)); /*CAM_D10*/ 388 MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)); /*CAM_D10*/
388 MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)); /*CAM_D11*/ 389 MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)); /*CAM_D11*/
389 MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)); /*CAM_XCLKB*/ 390 MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)); /*CAM_XCLKB*/
390 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)); /*GPIO_167*/ 391 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)); /*GPIO_167*/
391 MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)); /*CAM_STROBE*/ 392 MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)); /*CAM_STROBE*/
392 393
393 MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)); /*CSI2_DX0*/ 394 MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)); /*CSI2_DX0*/
394 MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)); /*CSI2_DY0*/ 395 MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)); /*CSI2_DY0*/
395 MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)); /*CSI2_DX1*/ 396 MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)); /*CSI2_DX1*/
396 MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)); /*CSI2_DY1*/ 397 MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)); /*CSI2_DY1*/
397 398
398 MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)); /*McBSP2_FSX*/ 399 MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)); /*McBSP2_FSX*/
399 MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)); /*McBSP2_CLKX*/ 400 MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)); /*McBSP2_CLKX*/
400 MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)); /*McBSP2_DR*/ 401 MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)); /*McBSP2_DR*/
401 MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)); /*McBSP2_DX*/ 402 MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)); /*McBSP2_DX*/
402 403
403 MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/ 404 MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/
404 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/ 405 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/
405 MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/ 406 MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/
406 MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/ 407 MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/
407 MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/ 408 MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/
408 MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/ 409 MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/
409 MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /*MMC1_DAT4*/ 410 MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /*MMC1_DAT4*/
410 MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /*MMC1_DAT5*/ 411 MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /*MMC1_DAT5*/
411 MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /*MMC1_DAT6*/ 412 MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /*MMC1_DAT6*/
412 MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /*MMC1_DAT7*/ 413 MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /*MMC1_DAT7*/
413 414
414 MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)); /*MMC2_CLK*/ 415 MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)); /*MMC2_CLK*/
415 MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)); /*MMC2_CMD*/ 416 MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)); /*MMC2_CMD*/
416 MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)); /*MMC2_DAT0*/ 417 MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)); /*MMC2_DAT0*/
417 MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)); /*MMC2_DAT1*/ 418 MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)); /*MMC2_DAT1*/
418 MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)); /*MMC2_DAT2*/ 419 MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)); /*MMC2_DAT2*/
419 MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)); /*MMC2_DAT3*/ 420 MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)); /*MMC2_DAT3*/
420 MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M0)); /*MMC2_DAT4*/ 421 MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M0)); /*MMC2_DAT4*/
421 MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M0)); /*MMC2_DAT5*/ 422 MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M0)); /*MMC2_DAT5*/
422 MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M0)); /*MMC2_DAT6 */ 423 MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M0)); /*MMC2_DAT6 */
423 MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M0)); /*MMC2_DAT7*/ 424 MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M0)); /*MMC2_DAT7*/
424 425
425 MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)); /*McBSP3_DX*/ 426 MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)); /*McBSP3_DX*/
426 MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)); /*McBSP3_DR*/ 427 MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)); /*McBSP3_DR*/
427 MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)); /*McBSP3_CLKX*/ 428 MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)); /*McBSP3_CLKX*/
428 MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)); /*McBSP3_FSX*/ 429 MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)); /*McBSP3_FSX*/
429 430
430 MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)); /*UART2_CTS*/ 431 MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)); /*UART2_CTS*/
431 MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)); /*UART2_RTS*/ 432 MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)); /*UART2_RTS*/
432 MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)); /*UART2_TX*/ 433 MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)); /*UART2_TX*/
433 MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)); /*UART2_RX*/ 434 MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)); /*UART2_RX*/
434 435
435 MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); /*UART1_TX*/ 436 MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); /*UART1_TX*/
436 MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); /*UART1_RTS*/ 437 MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); /*UART1_RTS*/
437 MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); /*UART1_CTS*/ 438 MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); /*UART1_CTS*/
438 MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); /*UART1_RX*/ 439 MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); /*UART1_RX*/
439 440
440 MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)); /*GPIO_152*/ 441 MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)); /*GPIO_152*/
441 MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)); /*GPIO_153*/ 442 MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)); /*GPIO_153*/
442 443
443 MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)); /*MCBSP1_CLKR*/ 444 MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)); /*MCBSP1_CLKR*/
444 MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)); /*MCBSP1_FSR*/ 445 MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)); /*MCBSP1_FSR*/
445 MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)); /*MCBSP1_DX*/ 446 MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)); /*MCBSP1_DX*/
446 MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)); /*MCBSP1_DR*/ 447 MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)); /*MCBSP1_DR*/
447 MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)); /*MCBSP_CLKS*/ 448 MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)); /*MCBSP_CLKS*/
448 MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)); /*MCBSP1_FSX*/ 449 MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)); /*MCBSP1_FSX*/
449 MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)); /*MCBSP1_CLKX*/ 450 MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)); /*MCBSP1_CLKX*/
450 451
451 MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)); /*UART3_CTS_*/ 452 MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)); /*UART3_CTS_*/
452 MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)); /*UART3_RTS_SD */ 453 MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)); /*UART3_RTS_SD */
453 MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX_IRRX*/ 454 MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX_IRRX*/
454 MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX_IRTX*/ 455 MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX_IRTX*/
455 456
456 MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/ 457 MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/
457 MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/ 458 MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/
458 MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/ 459 MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/
459 MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/ 460 MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/
460 MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/ 461 MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/
461 MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/ 462 MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/
462 MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/ 463 MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/
463 MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/ 464 MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/
464 MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/ 465 MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/
465 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/ 466 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/
466 MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/ 467 MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/
467 MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/ 468 MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/
468 469
469 MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/ 470 MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/
470 MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/ 471 MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/
471 472
472 MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/ 473 MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/
473 MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/ 474 MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/
474 475
475 MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/ 476 MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/
476 MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/ 477 MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/
477 478
478 MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)); /*I2C4_SCL*/ 479 MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)); /*I2C4_SCL*/
479 MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)); /*I2C4_SDA*/ 480 MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)); /*I2C4_SDA*/
480 481
481 MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)); /*HDQ_SIO*/ 482 MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)); /*HDQ_SIO*/
482 483
483 MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)); /*McSPI1_CLK*/ 484 MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)); /*McSPI1_CLK*/
484 MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)); /*McSPI1_SIMO */ 485 MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)); /*McSPI1_SIMO */
485 MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)); /*McSPI1_SOMI */ 486 MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)); /*McSPI1_SOMI */
486 MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)); /*McSPI1_CS0*/ 487 MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)); /*McSPI1_CS0*/
487 MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)); /*GPIO_175*/ 488 MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)); /*GPIO_175*/
488 MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)); /*GPIO_176*/ 489 MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)); /*GPIO_176*/
489 MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)); /*McSPI1_CS3*/ 490 MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)); /*McSPI1_CS3*/
490 491
491 MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)); /*McSPI2_CLK*/ 492 MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)); /*McSPI2_CLK*/
492 MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)); /*McSPI2_SIMO*/ 493 MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)); /*McSPI2_SIMO*/
493 MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)); /*McSPI2_SOMI*/ 494 MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)); /*McSPI2_SOMI*/
494 MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)); /*McSPI2_CS0*/ 495 MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)); /*McSPI2_CS0*/
495 MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)); /*McSPI2_CS1*/ 496 MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)); /*McSPI2_CS1*/
496 497
497 MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/ 498 MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/
498 MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/ 499 MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/
499 MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/ 500 MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/
500 MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)); /*GPIO_2*/ 501 MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)); /*GPIO_2*/
501 MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)); /*GPIO_3 */ 502 MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)); /*GPIO_3 */
502 MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)); /*GPIO_4*/ 503 MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)); /*GPIO_4*/
503 MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)); /*GPIO_5*/ 504 MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)); /*GPIO_5*/
504 MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)); /*GPIO_6*/ 505 MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)); /*GPIO_6*/
505 MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)); /*GPIO_7*/ 506 MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)); /*GPIO_7*/
506 507
507 MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*SYS_OFF_MODE*/ 508 MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*SYS_OFF_MODE*/
508 MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*SYS_CLKOUT1*/ 509 MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*SYS_CLKOUT1*/
509 MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)); /*SYS_CLKOUT2*/ 510 MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)); /*SYS_CLKOUT2*/
510 511
511 MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/ 512 MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/
512 MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/ 513 MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/
513 MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/ 514 MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/
514 MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)); /*JTAG_EMU0*/ 515 MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)); /*JTAG_EMU0*/
515 MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)); /*JTAG_EMU1*/ 516 MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)); /*JTAG_EMU1*/
516 517
517 MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)); /*ETK_CLK*/ 518 MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)); /*ETK_CLK*/
518 MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)); /*ETK_CTL*/ 519 MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)); /*ETK_CTL*/
519 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)); /*ETK_D0*/ 520 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)); /*ETK_D0*/
520 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)); /*ETK_D1*/ 521 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)); /*ETK_D1*/
521 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)); /*ETK_D2*/ 522 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)); /*ETK_D2*/
522 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)); /*ETK_D3*/ 523 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)); /*ETK_D3*/
523 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)); /*ETK_D4*/ 524 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)); /*ETK_D4*/
524 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)); /*ETK_D5*/ 525 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)); /*ETK_D5*/
525 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)); /*ETK_D6*/ 526 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)); /*ETK_D6*/
526 MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)); /*ETK_D7*/ 527 MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)); /*ETK_D7*/
527 MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)); /*ETK_D8*/ 528 MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)); /*ETK_D8*/
528 MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)); /*ETK_D9*/ 529 MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)); /*ETK_D9*/
529 MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)); /*ETK_D10*/ 530 MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)); /*ETK_D10*/
530 MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)); /*ETK_D11*/ 531 MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)); /*ETK_D11*/
531 MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)); /*ETK_D12*/ 532 MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)); /*ETK_D12*/
532 MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)); /*ETK_D13*/ 533 MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)); /*ETK_D13*/
533 MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)); /*ETK_D14*/ 534 MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)); /*ETK_D14*/
534 MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)); /*ETK_D15*/ 535 MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)); /*ETK_D15*/
535 536
536 MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)); /*d2d_mcad1*/ 537 MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)); /*d2d_mcad1*/
537 MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)); /*d2d_mcad2*/ 538 MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)); /*d2d_mcad2*/
538 MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)); /*d2d_mcad3*/ 539 MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)); /*d2d_mcad3*/
539 MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)); /*d2d_mcad4*/ 540 MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)); /*d2d_mcad4*/
540 MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)); /*d2d_mcad5*/ 541 MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)); /*d2d_mcad5*/
541 MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)); /*d2d_mcad6*/ 542 MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)); /*d2d_mcad6*/
542 MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)); /*d2d_mcad7*/ 543 MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)); /*d2d_mcad7*/
543 MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)); /*d2d_mcad8*/ 544 MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)); /*d2d_mcad8*/
544 MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)); /*d2d_mcad9*/ 545 MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)); /*d2d_mcad9*/
545 MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)); /*d2d_mcad10*/ 546 MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)); /*d2d_mcad10*/
546 MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)); /*d2d_mcad11*/ 547 MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)); /*d2d_mcad11*/
547 MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)); /*d2d_mcad12*/ 548 MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)); /*d2d_mcad12*/
548 MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)); /*d2d_mcad13*/ 549 MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)); /*d2d_mcad13*/
549 MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)); /*d2d_mcad14*/ 550 MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)); /*d2d_mcad14*/
550 MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)); /*d2d_mcad15*/ 551 MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)); /*d2d_mcad15*/
551 MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)); /*d2d_mcad16*/ 552 MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)); /*d2d_mcad16*/
552 MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)); /*d2d_mcad17*/ 553 MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)); /*d2d_mcad17*/
553 MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)); /*d2d_mcad18*/ 554 MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)); /*d2d_mcad18*/
554 MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)); /*d2d_mcad19*/ 555 MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)); /*d2d_mcad19*/
555 MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)); /*d2d_mcad20*/ 556 MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)); /*d2d_mcad20*/
556 MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)); /*d2d_mcad21*/ 557 MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)); /*d2d_mcad21*/
557 MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)); /*d2d_mcad22*/ 558 MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)); /*d2d_mcad22*/
558 MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)); /*d2d_mcad23*/ 559 MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)); /*d2d_mcad23*/
559 MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)); /*d2d_mcad24*/ 560 MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)); /*d2d_mcad24*/
560 MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)); /*d2d_mcad25*/ 561 MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)); /*d2d_mcad25*/
561 MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)); /*d2d_mcad26*/ 562 MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)); /*d2d_mcad26*/
562 MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)); /*d2d_mcad27*/ 563 MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)); /*d2d_mcad27*/
563 MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)); /*d2d_mcad28*/ 564 MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)); /*d2d_mcad28*/
564 MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)); /*d2d_mcad29*/ 565 MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)); /*d2d_mcad29*/
565 MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)); /*d2d_mcad30*/ 566 MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)); /*d2d_mcad30*/
566 MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)); /*d2d_mcad31*/ 567 MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)); /*d2d_mcad31*/
567 MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)); /*d2d_mcad32*/ 568 MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)); /*d2d_mcad32*/
568 MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)); /*d2d_mcad33*/ 569 MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)); /*d2d_mcad33*/
569 MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)); /*d2d_mcad34*/ 570 MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)); /*d2d_mcad34*/
570 MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)); /*d2d_mcad35*/ 571 MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)); /*d2d_mcad35*/
571 MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)); /*d2d_mcad36*/ 572 MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)); /*d2d_mcad36*/
572 MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)); /*d2d_clk26mi*/ 573 MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)); /*d2d_clk26mi*/
573 MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)); /*d2d_nrespwron*/ 574 MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)); /*d2d_nrespwron*/
574 MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)); /*d2d_nreswarm */ 575 MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)); /*d2d_nreswarm */
575 MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)); /*d2d_arm9nirq */ 576 MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)); /*d2d_arm9nirq */
576 MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)); /*d2d_uma2p6fiq*/ 577 MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)); /*d2d_uma2p6fiq*/
577 MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)); /*d2d_spint*/ 578 MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)); /*d2d_spint*/
578 MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)); /*d2d_frint*/ 579 MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)); /*d2d_frint*/
579 MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)); /*d2d_dmareq0*/ 580 MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)); /*d2d_dmareq0*/
580 MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)); /*d2d_dmareq1*/ 581 MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)); /*d2d_dmareq1*/
581 MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)); /*d2d_dmareq2*/ 582 MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)); /*d2d_dmareq2*/
582 MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)); /*d2d_dmareq3*/ 583 MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)); /*d2d_dmareq3*/
583 MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)); /*d2d_n3gtrst*/ 584 MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)); /*d2d_n3gtrst*/
584 MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)); /*d2d_n3gtdi*/ 585 MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)); /*d2d_n3gtdi*/
585 MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)); /*d2d_n3gtdo*/ 586 MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)); /*d2d_n3gtdo*/
586 MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)); /*d2d_n3gtms*/ 587 MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)); /*d2d_n3gtms*/
587 MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)); /*d2d_n3gtck*/ 588 MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)); /*d2d_n3gtck*/
588 MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)); /*d2d_n3grtck*/ 589 MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)); /*d2d_n3grtck*/
589 MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)); /*d2d_mstdby*/ 590 MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)); /*d2d_mstdby*/
590 MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)); /*d2d_swakeup*/ 591 MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)); /*d2d_swakeup*/
591 MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)); /*d2d_idlereq*/ 592 MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)); /*d2d_idlereq*/
592 MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)); /*d2d_idleack*/ 593 MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)); /*d2d_idleack*/
593 MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)); /*d2d_mwrite*/ 594 MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)); /*d2d_mwrite*/
594 MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)); /*d2d_swrite*/ 595 MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)); /*d2d_swrite*/
595 MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)); /*d2d_mread*/ 596 MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)); /*d2d_mread*/
596 MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)); /*d2d_sread*/ 597 MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)); /*d2d_sread*/
597 MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_mbusflag*/ 598 MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_mbusflag*/
598 MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_sbusflag*/ 599 MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_sbusflag*/
599 } 600 }
600 601
board/logicpd/zoom1/zoom1.c
Diff comments   View file @ 17fa032
1 /* 1 /*
2 * (C) Copyright 2004-2008 2 * (C) Copyright 2004-2008
3 * Texas Instruments, <www.ti.com> 3 * Texas Instruments, <www.ti.com>
4 * 4 *
5 * Author : 5 * Author :
6 * Nishanth Menon <nm@ti.com> 6 * Nishanth Menon <nm@ti.com>
7 * 7 *
8 * Derived from Beagle Board and 3430 SDP code by 8 * Derived from Beagle Board and 3430 SDP code by
9 * Sunil Kumar <sunilsaini05@gmail.com> 9 * Sunil Kumar <sunilsaini05@gmail.com>
10 * Shashi Ranjan <shashiranjanmca05@gmail.com> 10 * Shashi Ranjan <shashiranjanmca05@gmail.com>
11 * Richard Woodruff <r-woodruff2@ti.com> 11 * Richard Woodruff <r-woodruff2@ti.com>
12 * Syed Mohammed Khasim <khasim@ti.com> 12 * Syed Mohammed Khasim <khasim@ti.com>
13 * 13 *
14 * 14 *
15 * SPDX-License-Identifier: GPL-2.0+ 15 * SPDX-License-Identifier: GPL-2.0+
16 */ 16 */
17 #include <common.h> 17 #include <common.h>
18 #include <dm.h> 18 #include <dm.h>
19 #include <ns16550.h> 19 #include <ns16550.h>
20 #include <netdev.h> 20 #include <netdev.h>
21 #include <twl4030.h> 21 #include <twl4030.h>
22 #include <linux/mtd/omap_gpmc.h> 22 #include <linux/mtd/omap_gpmc.h>
23 #include <asm/io.h> 23 #include <asm/io.h>
24 #include <asm/arch/mem.h> 24 #include <asm/arch/mem.h>
25 #include <asm/arch/mmc_host_def.h> 25 #include <asm/arch/mmc_host_def.h>
26 #include <asm/arch/mux.h> 26 #include <asm/arch/mux.h>
27 #include <asm/arch/sys_proto.h> 27 #include <asm/arch/sys_proto.h>
28 #include <asm/mach-types.h> 28 #include <asm/mach-types.h>
29 #include "zoom1.h" 29 #include "zoom1.h"
30 30
31 DECLARE_GLOBAL_DATA_PTR; 31 DECLARE_GLOBAL_DATA_PTR;
32 32
33 /* 33 /*
34 * gpmc_cfg is initialized by gpmc_init and we use it here. 34 * gpmc_cfg is initialized by gpmc_init and we use it here.
35 * GPMC definitions for Ethenet Controller LAN9211 35 * GPMC definitions for Ethenet Controller LAN9211
36 */ 36 */
37 static const u32 gpmc_lab_enet[] = { 37 static const u32 gpmc_lab_enet[] = {
38 ZOOM1_ENET_GPMC_CONF1, 38 ZOOM1_ENET_GPMC_CONF1,
39 ZOOM1_ENET_GPMC_CONF2, 39 ZOOM1_ENET_GPMC_CONF2,
40 ZOOM1_ENET_GPMC_CONF3, 40 ZOOM1_ENET_GPMC_CONF3,
41 ZOOM1_ENET_GPMC_CONF4, 41 ZOOM1_ENET_GPMC_CONF4,
42 ZOOM1_ENET_GPMC_CONF5, 42 ZOOM1_ENET_GPMC_CONF5,
43 ZOOM1_ENET_GPMC_CONF6, 43 ZOOM1_ENET_GPMC_CONF6,
44 /*CONF7- computed as params */ 44 /*CONF7- computed as params */
45 }; 45 };
46 46
47 static const struct ns16550_platdata zoom1_serial = { 47 static const struct ns16550_platdata zoom1_serial = {
48 .base = OMAP34XX_UART3, 48 .base = OMAP34XX_UART3,
49 .reg_shift = 2, 49 .reg_shift = 2,
50 .clock = V_NS16550_CLK 50 .clock = V_NS16550_CLK,
51 .fcr = UART_FCR_DEFVAL,
51 }; 52 };
52 53
53 U_BOOT_DEVICE(zoom1_uart) = { 54 U_BOOT_DEVICE(zoom1_uart) = {
54 "ns16550_serial", 55 "ns16550_serial",
55 &zoom1_serial 56 &zoom1_serial
56 }; 57 };
57 58
58 /* 59 /*
59 * Routine: board_init 60 * Routine: board_init
60 * Description: Early hardware init. 61 * Description: Early hardware init.
61 */ 62 */
62 int board_init(void) 63 int board_init(void)
63 { 64 {
64 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 65 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
65 /* CS1 is Ethernet LAN9211 */ 66 /* CS1 is Ethernet LAN9211 */
66 enable_gpmc_cs_config(gpmc_lab_enet, &gpmc_cfg->cs[1], 67 enable_gpmc_cs_config(gpmc_lab_enet, &gpmc_cfg->cs[1],
67 DEBUG_BASE, GPMC_SIZE_16M); 68 DEBUG_BASE, GPMC_SIZE_16M);
68 /* board id for Linux */ 69 /* board id for Linux */
69 gd->bd->bi_arch_number = MACH_TYPE_OMAP_LDP; 70 gd->bd->bi_arch_number = MACH_TYPE_OMAP_LDP;
70 /* boot param addr */ 71 /* boot param addr */
71 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 72 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
72 73
73 return 0; 74 return 0;
74 } 75 }
75 76
76 /* 77 /*
77 * Routine: misc_init_r 78 * Routine: misc_init_r
78 * Description: Configure zoom board specific configurations 79 * Description: Configure zoom board specific configurations
79 */ 80 */
80 int misc_init_r(void) 81 int misc_init_r(void)
81 { 82 {
82 twl4030_power_init(); 83 twl4030_power_init();
83 twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); 84 twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
84 omap_die_id_display(); 85 omap_die_id_display();
85 86
86 /* 87 /*
87 * Board Reset 88 * Board Reset
88 * The board is reset by holding the red button on the 89 * The board is reset by holding the red button on the
89 * top right front face for eight seconds. 90 * top right front face for eight seconds.
90 */ 91 */
91 twl4030_power_reset_init(); 92 twl4030_power_reset_init();
92 93
93 return 0; 94 return 0;
94 } 95 }
95 96
96 /* 97 /*
97 * Routine: set_muxconf_regs 98 * Routine: set_muxconf_regs
98 * Description: Setting up the configuration Mux registers specific to the 99 * Description: Setting up the configuration Mux registers specific to the
99 * hardware. Many pins need to be moved from protect to primary 100 * hardware. Many pins need to be moved from protect to primary
100 * mode. 101 * mode.
101 */ 102 */
102 void set_muxconf_regs(void) 103 void set_muxconf_regs(void)
103 { 104 {
104 /* platform specific muxes */ 105 /* platform specific muxes */
105 MUX_ZOOM1_MDK(); 106 MUX_ZOOM1_MDK();
106 } 107 }
107 108
108 #ifdef CONFIG_GENERIC_MMC 109 #ifdef CONFIG_GENERIC_MMC
109 int board_mmc_init(bd_t *bis) 110 int board_mmc_init(bd_t *bis)
110 { 111 {
111 return omap_mmc_init(0, 0, 0, -1, -1); 112 return omap_mmc_init(0, 0, 0, -1, -1);
112 } 113 }
113 114
114 void board_mmc_power_init(void) 115 void board_mmc_power_init(void)
115 { 116 {
116 twl4030_power_mmc_init(0); 117 twl4030_power_mmc_init(0);
117 } 118 }
118 #endif 119 #endif
119 120
120 #ifdef CONFIG_CMD_NET 121 #ifdef CONFIG_CMD_NET
121 int board_eth_init(bd_t *bis) 122 int board_eth_init(bd_t *bis)
122 { 123 {
123 int rc = 0; 124 int rc = 0;
124 125
125 #ifdef CONFIG_SMC911X 126 #ifdef CONFIG_SMC911X
126 #define STR_ENV_ETHADDR "ethaddr" 127 #define STR_ENV_ETHADDR "ethaddr"
127 128
128 struct eth_device *dev; 129 struct eth_device *dev;
129 uchar eth_addr[6]; 130 uchar eth_addr[6];
130 131
131 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); 132 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
132 if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) { 133 if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
133 dev = eth_get_dev_by_index(0); 134 dev = eth_get_dev_by_index(0);
134 if (dev) { 135 if (dev) {
135 eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr); 136 eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
136 } else { 137 } else {
137 printf("zoom1: Couldn't get eth device\n"); 138 printf("zoom1: Couldn't get eth device\n");
138 rc = -1; 139 rc = -1;
139 } 140 }
140 } 141 }
141 #endif 142 #endif
142 143
143 return rc; 144 return rc;
144 } 145 }
145 #endif 146 #endif
146 147
1 /* 1 /*
2 * Maintainer : Steve Sakoman <steve@sakoman.com> 2 * Maintainer : Steve Sakoman <steve@sakoman.com>
3 * 3 *
4 * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by 4 * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
5 * Richard Woodruff <r-woodruff2@ti.com> 5 * Richard Woodruff <r-woodruff2@ti.com>
6 * Syed Mohammed Khasim <khasim@ti.com> 6 * Syed Mohammed Khasim <khasim@ti.com>
7 * Sunil Kumar <sunilsaini05@gmail.com> 7 * Sunil Kumar <sunilsaini05@gmail.com>
8 * Shashi Ranjan <shashiranjanmca05@gmail.com> 8 * Shashi Ranjan <shashiranjanmca05@gmail.com>
9 * 9 *
10 * (C) Copyright 2004-2008 10 * (C) Copyright 2004-2008
11 * Texas Instruments, <www.ti.com> 11 * Texas Instruments, <www.ti.com>
12 * 12 *
13 * SPDX-License-Identifier: GPL-2.0+ 13 * SPDX-License-Identifier: GPL-2.0+
14 */ 14 */
15 #include <common.h> 15 #include <common.h>
16 #include <dm.h> 16 #include <dm.h>
17 #include <ns16550.h> 17 #include <ns16550.h>
18 #include <netdev.h> 18 #include <netdev.h>
19 #include <twl4030.h> 19 #include <twl4030.h>
20 #include <linux/mtd/nand.h> 20 #include <linux/mtd/nand.h>
21 #include <asm/io.h> 21 #include <asm/io.h>
22 #include <asm/arch/mmc_host_def.h> 22 #include <asm/arch/mmc_host_def.h>
23 #include <asm/arch/mux.h> 23 #include <asm/arch/mux.h>
24 #include <asm/arch/mem.h> 24 #include <asm/arch/mem.h>
25 #include <asm/arch/sys_proto.h> 25 #include <asm/arch/sys_proto.h>
26 #include <asm/gpio.h> 26 #include <asm/gpio.h>
27 #include <asm/mach-types.h> 27 #include <asm/mach-types.h>
28 #include "overo.h" 28 #include "overo.h"
29 29
30 #ifdef CONFIG_USB_EHCI 30 #ifdef CONFIG_USB_EHCI
31 #include <usb.h> 31 #include <usb.h>
32 #include <asm/ehci-omap.h> 32 #include <asm/ehci-omap.h>
33 #endif 33 #endif
34 34
35 DECLARE_GLOBAL_DATA_PTR; 35 DECLARE_GLOBAL_DATA_PTR;
36 36
37 #define TWL4030_I2C_BUS 0 37 #define TWL4030_I2C_BUS 0
38 #define EXPANSION_EEPROM_I2C_BUS 2 38 #define EXPANSION_EEPROM_I2C_BUS 2
39 #define EXPANSION_EEPROM_I2C_ADDRESS 0x51 39 #define EXPANSION_EEPROM_I2C_ADDRESS 0x51
40 40
41 #define GUMSTIX_EMPTY_EEPROM 0x0 41 #define GUMSTIX_EMPTY_EEPROM 0x0
42 42
43 #define GUMSTIX_SUMMIT 0x01000200 43 #define GUMSTIX_SUMMIT 0x01000200
44 #define GUMSTIX_TOBI 0x02000200 44 #define GUMSTIX_TOBI 0x02000200
45 #define GUMSTIX_TOBI_DUO 0x03000200 45 #define GUMSTIX_TOBI_DUO 0x03000200
46 #define GUMSTIX_PALO35 0x04000200 46 #define GUMSTIX_PALO35 0x04000200
47 #define GUMSTIX_PALO43 0x05000200 47 #define GUMSTIX_PALO43 0x05000200
48 #define GUMSTIX_CHESTNUT43 0x06000200 48 #define GUMSTIX_CHESTNUT43 0x06000200
49 #define GUMSTIX_PINTO 0x07000200 49 #define GUMSTIX_PINTO 0x07000200
50 #define GUMSTIX_GALLOP43 0x08000200 50 #define GUMSTIX_GALLOP43 0x08000200
51 #define GUMSTIX_ALTO35 0x09000200 51 #define GUMSTIX_ALTO35 0x09000200
52 #define GUMSTIX_STAGECOACH 0x0A000200 52 #define GUMSTIX_STAGECOACH 0x0A000200
53 #define GUMSTIX_THUMBO 0x0B000200 53 #define GUMSTIX_THUMBO 0x0B000200
54 #define GUMSTIX_TURTLECORE 0x0C000200 54 #define GUMSTIX_TURTLECORE 0x0C000200
55 #define GUMSTIX_ARBOR43C 0x0D000200 55 #define GUMSTIX_ARBOR43C 0x0D000200
56 56
57 #define ETTUS_USRP_E 0x01000300 57 #define ETTUS_USRP_E 0x01000300
58 58
59 #define GUMSTIX_NO_EEPROM 0xffffffff 59 #define GUMSTIX_NO_EEPROM 0xffffffff
60 60
61 static struct { 61 static struct {
62 unsigned int device_vendor; 62 unsigned int device_vendor;
63 unsigned char revision; 63 unsigned char revision;
64 unsigned char content; 64 unsigned char content;
65 char fab_revision[8]; 65 char fab_revision[8];
66 char env_var[16]; 66 char env_var[16];
67 char env_setting[64]; 67 char env_setting[64];
68 } expansion_config = {0x0}; 68 } expansion_config = {0x0};
69 69
70 static const struct ns16550_platdata overo_serial = { 70 static const struct ns16550_platdata overo_serial = {
71 .base = OMAP34XX_UART3, 71 .base = OMAP34XX_UART3,
72 .reg_shift = 2, 72 .reg_shift = 2,
73 .clock = V_NS16550_CLK 73 .clock = V_NS16550_CLK,
74 .fcr = UART_FCR_DEFVAL,
74 }; 75 };
75 76
76 U_BOOT_DEVICE(overo_uart) = { 77 U_BOOT_DEVICE(overo_uart) = {
77 "ns16550_serial", 78 "ns16550_serial",
78 &overo_serial 79 &overo_serial
79 }; 80 };
80 81
81 /* 82 /*
82 * Routine: get_sdio2_config 83 * Routine: get_sdio2_config
83 * Description: Return information about the wifi module connection 84 * Description: Return information about the wifi module connection
84 * Returns 0 if the module connects though a level translator 85 * Returns 0 if the module connects though a level translator
85 * Returns 1 if the module connects directly 86 * Returns 1 if the module connects directly
86 */ 87 */
87 int get_sdio2_config(void) 88 int get_sdio2_config(void)
88 { 89 {
89 int sdio_direct; 90 int sdio_direct;
90 91
91 if (!gpio_request(130, "") && !gpio_request(139, "")) { 92 if (!gpio_request(130, "") && !gpio_request(139, "")) {
92 93
93 gpio_direction_output(130, 0); 94 gpio_direction_output(130, 0);
94 gpio_direction_input(139); 95 gpio_direction_input(139);
95 96
96 sdio_direct = 1; 97 sdio_direct = 1;
97 gpio_set_value(130, 0); 98 gpio_set_value(130, 0);
98 if (gpio_get_value(139) == 0) { 99 if (gpio_get_value(139) == 0) {
99 gpio_set_value(130, 1); 100 gpio_set_value(130, 1);
100 if (gpio_get_value(139) == 1) 101 if (gpio_get_value(139) == 1)
101 sdio_direct = 0; 102 sdio_direct = 0;
102 } 103 }
103 104
104 gpio_direction_input(130); 105 gpio_direction_input(130);
105 } else { 106 } else {
106 puts("Error: unable to acquire sdio2 clk GPIOs\n"); 107 puts("Error: unable to acquire sdio2 clk GPIOs\n");
107 sdio_direct = -1; 108 sdio_direct = -1;
108 } 109 }
109 110
110 return sdio_direct; 111 return sdio_direct;
111 } 112 }
112 113
113 /* 114 /*
114 * Routine: get_expansion_id 115 * Routine: get_expansion_id
115 * Description: This function checks for expansion board by checking I2C 116 * Description: This function checks for expansion board by checking I2C
116 * bus 2 for the availability of an AT24C01B serial EEPROM. 117 * bus 2 for the availability of an AT24C01B serial EEPROM.
117 * returns the device_vendor field from the EEPROM 118 * returns the device_vendor field from the EEPROM
118 */ 119 */
119 unsigned int get_expansion_id(void) 120 unsigned int get_expansion_id(void)
120 { 121 {
121 if (expansion_config.device_vendor != 0x0) 122 if (expansion_config.device_vendor != 0x0)
122 return expansion_config.device_vendor; 123 return expansion_config.device_vendor;
123 124
124 i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS); 125 i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS);
125 126
126 /* return GUMSTIX_NO_EEPROM if eeprom doesn't respond */ 127 /* return GUMSTIX_NO_EEPROM if eeprom doesn't respond */
127 if (i2c_probe(EXPANSION_EEPROM_I2C_ADDRESS) == 1) { 128 if (i2c_probe(EXPANSION_EEPROM_I2C_ADDRESS) == 1) {
128 i2c_set_bus_num(TWL4030_I2C_BUS); 129 i2c_set_bus_num(TWL4030_I2C_BUS);
129 return GUMSTIX_NO_EEPROM; 130 return GUMSTIX_NO_EEPROM;
130 } 131 }
131 132
132 /* read configuration data */ 133 /* read configuration data */
133 i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config, 134 i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config,
134 sizeof(expansion_config)); 135 sizeof(expansion_config));
135 136
136 i2c_set_bus_num(TWL4030_I2C_BUS); 137 i2c_set_bus_num(TWL4030_I2C_BUS);
137 138
138 return expansion_config.device_vendor; 139 return expansion_config.device_vendor;
139 } 140 }
140 141
141 /* 142 /*
142 * Routine: misc_init_r 143 * Routine: misc_init_r
143 * Description: Configure board specific parts 144 * Description: Configure board specific parts
144 */ 145 */
145 int misc_init_r(void) 146 int misc_init_r(void)
146 { 147 {
147 unsigned int expansion_id; 148 unsigned int expansion_id;
148 149
149 twl4030_power_init(); 150 twl4030_power_init();
150 twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); 151 twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
151 152
152 printf("Board revision: %d\n", get_board_revision()); 153 printf("Board revision: %d\n", get_board_revision());
153 154
154 switch (get_sdio2_config()) { 155 switch (get_sdio2_config()) {
155 case 0: 156 case 0:
156 puts("Tranceiver detected on mmc2\n"); 157 puts("Tranceiver detected on mmc2\n");
157 MUX_OVERO_SDIO2_TRANSCEIVER(); 158 MUX_OVERO_SDIO2_TRANSCEIVER();
158 break; 159 break;
159 case 1: 160 case 1:
160 puts("Direct connection on mmc2\n"); 161 puts("Direct connection on mmc2\n");
161 MUX_OVERO_SDIO2_DIRECT(); 162 MUX_OVERO_SDIO2_DIRECT();
162 break; 163 break;
163 default: 164 default:
164 puts("Unable to detect mmc2 connection type\n"); 165 puts("Unable to detect mmc2 connection type\n");
165 } 166 }
166 167
167 expansion_id = get_expansion_id(); 168 expansion_id = get_expansion_id();
168 switch (expansion_id) { 169 switch (expansion_id) {
169 case GUMSTIX_SUMMIT: 170 case GUMSTIX_SUMMIT:
170 printf("Recognized Summit expansion board (rev %d %s)\n", 171 printf("Recognized Summit expansion board (rev %d %s)\n",
171 expansion_config.revision, 172 expansion_config.revision,
172 expansion_config.fab_revision); 173 expansion_config.fab_revision);
173 MUX_GUMSTIX(); 174 MUX_GUMSTIX();
174 setenv("defaultdisplay", "dvi"); 175 setenv("defaultdisplay", "dvi");
175 setenv("expansionname", "summit"); 176 setenv("expansionname", "summit");
176 break; 177 break;
177 case GUMSTIX_TOBI: 178 case GUMSTIX_TOBI:
178 printf("Recognized Tobi expansion board (rev %d %s)\n", 179 printf("Recognized Tobi expansion board (rev %d %s)\n",
179 expansion_config.revision, 180 expansion_config.revision,
180 expansion_config.fab_revision); 181 expansion_config.fab_revision);
181 MUX_GUMSTIX(); 182 MUX_GUMSTIX();
182 setenv("defaultdisplay", "dvi"); 183 setenv("defaultdisplay", "dvi");
183 setenv("expansionname", "tobi"); 184 setenv("expansionname", "tobi");
184 break; 185 break;
185 case GUMSTIX_TOBI_DUO: 186 case GUMSTIX_TOBI_DUO:
186 printf("Recognized Tobi Duo expansion board (rev %d %s)\n", 187 printf("Recognized Tobi Duo expansion board (rev %d %s)\n",
187 expansion_config.revision, 188 expansion_config.revision,
188 expansion_config.fab_revision); 189 expansion_config.fab_revision);
189 MUX_GUMSTIX(); 190 MUX_GUMSTIX();
190 setenv("expansionname", "tobiduo"); 191 setenv("expansionname", "tobiduo");
191 break; 192 break;
192 case GUMSTIX_PALO35: 193 case GUMSTIX_PALO35:
193 printf("Recognized Palo35 expansion board (rev %d %s)\n", 194 printf("Recognized Palo35 expansion board (rev %d %s)\n",
194 expansion_config.revision, 195 expansion_config.revision,
195 expansion_config.fab_revision); 196 expansion_config.fab_revision);
196 MUX_GUMSTIX(); 197 MUX_GUMSTIX();
197 setenv("defaultdisplay", "lcd35"); 198 setenv("defaultdisplay", "lcd35");
198 setenv("expansionname", "palo35"); 199 setenv("expansionname", "palo35");
199 break; 200 break;
200 case GUMSTIX_PALO43: 201 case GUMSTIX_PALO43:
201 printf("Recognized Palo43 expansion board (rev %d %s)\n", 202 printf("Recognized Palo43 expansion board (rev %d %s)\n",
202 expansion_config.revision, 203 expansion_config.revision,
203 expansion_config.fab_revision); 204 expansion_config.fab_revision);
204 MUX_GUMSTIX(); 205 MUX_GUMSTIX();
205 setenv("defaultdisplay", "lcd43"); 206 setenv("defaultdisplay", "lcd43");
206 setenv("expansionname", "palo43"); 207 setenv("expansionname", "palo43");
207 break; 208 break;
208 case GUMSTIX_CHESTNUT43: 209 case GUMSTIX_CHESTNUT43:
209 printf("Recognized Chestnut43 expansion board (rev %d %s)\n", 210 printf("Recognized Chestnut43 expansion board (rev %d %s)\n",
210 expansion_config.revision, 211 expansion_config.revision,
211 expansion_config.fab_revision); 212 expansion_config.fab_revision);
212 MUX_GUMSTIX(); 213 MUX_GUMSTIX();
213 setenv("defaultdisplay", "lcd43"); 214 setenv("defaultdisplay", "lcd43");
214 setenv("expansionname", "chestnut43"); 215 setenv("expansionname", "chestnut43");
215 break; 216 break;
216 case GUMSTIX_PINTO: 217 case GUMSTIX_PINTO:
217 printf("Recognized Pinto expansion board (rev %d %s)\n", 218 printf("Recognized Pinto expansion board (rev %d %s)\n",
218 expansion_config.revision, 219 expansion_config.revision,
219 expansion_config.fab_revision); 220 expansion_config.fab_revision);
220 MUX_GUMSTIX(); 221 MUX_GUMSTIX();
221 break; 222 break;
222 case GUMSTIX_GALLOP43: 223 case GUMSTIX_GALLOP43:
223 printf("Recognized Gallop43 expansion board (rev %d %s)\n", 224 printf("Recognized Gallop43 expansion board (rev %d %s)\n",
224 expansion_config.revision, 225 expansion_config.revision,
225 expansion_config.fab_revision); 226 expansion_config.fab_revision);
226 MUX_GUMSTIX(); 227 MUX_GUMSTIX();
227 setenv("defaultdisplay", "lcd43"); 228 setenv("defaultdisplay", "lcd43");
228 setenv("expansionname", "gallop43"); 229 setenv("expansionname", "gallop43");
229 break; 230 break;
230 case GUMSTIX_ALTO35: 231 case GUMSTIX_ALTO35:
231 printf("Recognized Alto35 expansion board (rev %d %s)\n", 232 printf("Recognized Alto35 expansion board (rev %d %s)\n",
232 expansion_config.revision, 233 expansion_config.revision,
233 expansion_config.fab_revision); 234 expansion_config.fab_revision);
234 MUX_GUMSTIX(); 235 MUX_GUMSTIX();
235 MUX_ALTO35(); 236 MUX_ALTO35();
236 setenv("defaultdisplay", "lcd35"); 237 setenv("defaultdisplay", "lcd35");
237 setenv("expansionname", "alto35"); 238 setenv("expansionname", "alto35");
238 break; 239 break;
239 case GUMSTIX_STAGECOACH: 240 case GUMSTIX_STAGECOACH:
240 printf("Recognized Stagecoach expansion board (rev %d %s)\n", 241 printf("Recognized Stagecoach expansion board (rev %d %s)\n",
241 expansion_config.revision, 242 expansion_config.revision,
242 expansion_config.fab_revision); 243 expansion_config.fab_revision);
243 MUX_GUMSTIX(); 244 MUX_GUMSTIX();
244 break; 245 break;
245 case GUMSTIX_THUMBO: 246 case GUMSTIX_THUMBO:
246 printf("Recognized Thumbo expansion board (rev %d %s)\n", 247 printf("Recognized Thumbo expansion board (rev %d %s)\n",
247 expansion_config.revision, 248 expansion_config.revision,
248 expansion_config.fab_revision); 249 expansion_config.fab_revision);
249 MUX_GUMSTIX(); 250 MUX_GUMSTIX();
250 break; 251 break;
251 case GUMSTIX_TURTLECORE: 252 case GUMSTIX_TURTLECORE:
252 printf("Recognized Turtlecore expansion board (rev %d %s)\n", 253 printf("Recognized Turtlecore expansion board (rev %d %s)\n",
253 expansion_config.revision, 254 expansion_config.revision,
254 expansion_config.fab_revision); 255 expansion_config.fab_revision);
255 MUX_GUMSTIX(); 256 MUX_GUMSTIX();
256 break; 257 break;
257 case GUMSTIX_ARBOR43C: 258 case GUMSTIX_ARBOR43C:
258 printf("Recognized Arbor43C expansion board (rev %d %s)\n", 259 printf("Recognized Arbor43C expansion board (rev %d %s)\n",
259 expansion_config.revision, 260 expansion_config.revision,
260 expansion_config.fab_revision); 261 expansion_config.fab_revision);
261 MUX_GUMSTIX(); 262 MUX_GUMSTIX();
262 MUX_ARBOR43C(); 263 MUX_ARBOR43C();
263 setenv("defaultdisplay", "lcd43"); 264 setenv("defaultdisplay", "lcd43");
264 setenv("expansionname", "arbor43c"); 265 setenv("expansionname", "arbor43c");
265 break; 266 break;
266 case ETTUS_USRP_E: 267 case ETTUS_USRP_E:
267 printf("Recognized Ettus Research USRP-E (rev %d %s)\n", 268 printf("Recognized Ettus Research USRP-E (rev %d %s)\n",
268 expansion_config.revision, 269 expansion_config.revision,
269 expansion_config.fab_revision); 270 expansion_config.fab_revision);
270 MUX_GUMSTIX(); 271 MUX_GUMSTIX();
271 MUX_USRP_E(); 272 MUX_USRP_E();
272 setenv("defaultdisplay", "dvi"); 273 setenv("defaultdisplay", "dvi");
273 break; 274 break;
274 case GUMSTIX_NO_EEPROM: 275 case GUMSTIX_NO_EEPROM:
275 case GUMSTIX_EMPTY_EEPROM: 276 case GUMSTIX_EMPTY_EEPROM:
276 puts("No or empty EEPROM on expansion board\n"); 277 puts("No or empty EEPROM on expansion board\n");
277 MUX_GUMSTIX(); 278 MUX_GUMSTIX();
278 setenv("expansionname", "tobi"); 279 setenv("expansionname", "tobi");
279 break; 280 break;
280 default: 281 default:
281 printf("Unrecognized expansion board 0x%08x\n", expansion_id); 282 printf("Unrecognized expansion board 0x%08x\n", expansion_id);
282 break; 283 break;
283 } 284 }
284 285
285 if (expansion_config.content == 1) 286 if (expansion_config.content == 1)
286 setenv(expansion_config.env_var, expansion_config.env_setting); 287 setenv(expansion_config.env_var, expansion_config.env_setting);
287 288
288 omap_die_id_display(); 289 omap_die_id_display();
289 290
290 if (get_cpu_family() == CPU_OMAP34XX) 291 if (get_cpu_family() == CPU_OMAP34XX)
291 setenv("boardname", "overo"); 292 setenv("boardname", "overo");
292 else 293 else
293 setenv("boardname", "overo-storm"); 294 setenv("boardname", "overo-storm");
294 295
295 return 0; 296 return 0;
296 } 297 }
297 298
298 #if defined(CONFIG_CMD_NET) 299 #if defined(CONFIG_CMD_NET)
299 /* GPMC definitions for LAN9221 chips on Tobi expansion boards */ 300 /* GPMC definitions for LAN9221 chips on Tobi expansion boards */
300 static const u32 gpmc_lan_config[] = { 301 static const u32 gpmc_lan_config[] = {
301 NET_LAN9221_GPMC_CONFIG1, 302 NET_LAN9221_GPMC_CONFIG1,
302 NET_LAN9221_GPMC_CONFIG2, 303 NET_LAN9221_GPMC_CONFIG2,
303 NET_LAN9221_GPMC_CONFIG3, 304 NET_LAN9221_GPMC_CONFIG3,
304 NET_LAN9221_GPMC_CONFIG4, 305 NET_LAN9221_GPMC_CONFIG4,
305 NET_LAN9221_GPMC_CONFIG5, 306 NET_LAN9221_GPMC_CONFIG5,
306 NET_LAN9221_GPMC_CONFIG6, 307 NET_LAN9221_GPMC_CONFIG6,
307 /*CONFIG7- computed as params */ 308 /*CONFIG7- computed as params */
308 }; 309 };
309 310
310 /* 311 /*
311 * Routine: setup_net_chip 312 * Routine: setup_net_chip
312 * Description: Setting up the configuration GPMC registers specific to the 313 * Description: Setting up the configuration GPMC registers specific to the
313 * Ethernet hardware. 314 * Ethernet hardware.
314 */ 315 */
315 static void setup_net_chip(void) 316 static void setup_net_chip(void)
316 { 317 {
317 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; 318 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
318 319
319 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ 320 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
320 writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); 321 writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
321 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ 322 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
322 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); 323 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
323 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ 324 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
324 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, 325 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
325 &ctrl_base->gpmc_nadv_ale); 326 &ctrl_base->gpmc_nadv_ale);
326 } 327 }
327 328
328 /* 329 /*
329 * Routine: reset_net_chip 330 * Routine: reset_net_chip
330 * Description: Reset the Ethernet hardware. 331 * Description: Reset the Ethernet hardware.
331 */ 332 */
332 static void reset_net_chip(void) 333 static void reset_net_chip(void)
333 { 334 {
334 /* Make GPIO 64 as output pin and send a magic pulse through it */ 335 /* Make GPIO 64 as output pin and send a magic pulse through it */
335 if (!gpio_request(64, "")) { 336 if (!gpio_request(64, "")) {
336 gpio_direction_output(64, 0); 337 gpio_direction_output(64, 0);
337 gpio_set_value(64, 1); 338 gpio_set_value(64, 1);
338 udelay(1); 339 udelay(1);
339 gpio_set_value(64, 0); 340 gpio_set_value(64, 0);
340 udelay(1); 341 udelay(1);
341 gpio_set_value(64, 1); 342 gpio_set_value(64, 1);
342 } 343 }
343 } 344 }
344 345
345 int board_eth_init(bd_t *bis) 346 int board_eth_init(bd_t *bis)
346 { 347 {
347 unsigned int expansion_id; 348 unsigned int expansion_id;
348 int rc = 0; 349 int rc = 0;
349 350
350 #ifdef CONFIG_SMC911X 351 #ifdef CONFIG_SMC911X
351 expansion_id = get_expansion_id(); 352 expansion_id = get_expansion_id();
352 switch (expansion_id) { 353 switch (expansion_id) {
353 case GUMSTIX_TOBI_DUO: 354 case GUMSTIX_TOBI_DUO:
354 /* second lan chip */ 355 /* second lan chip */
355 enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4], 356 enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4],
356 0x2B000000, GPMC_SIZE_16M); 357 0x2B000000, GPMC_SIZE_16M);
357 /* no break */ 358 /* no break */
358 case GUMSTIX_TOBI: 359 case GUMSTIX_TOBI:
359 case GUMSTIX_CHESTNUT43: 360 case GUMSTIX_CHESTNUT43:
360 case GUMSTIX_STAGECOACH: 361 case GUMSTIX_STAGECOACH:
361 case GUMSTIX_NO_EEPROM: 362 case GUMSTIX_NO_EEPROM:
362 case GUMSTIX_EMPTY_EEPROM: 363 case GUMSTIX_EMPTY_EEPROM:
363 /* first lan chip */ 364 /* first lan chip */
364 enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 365 enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
365 0x2C000000, GPMC_SIZE_16M); 366 0x2C000000, GPMC_SIZE_16M);
366 367
367 setup_net_chip(); 368 setup_net_chip();
368 reset_net_chip(); 369 reset_net_chip();
369 370
370 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); 371 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
371 break; 372 break;
372 default: 373 default:
373 break; 374 break;
374 } 375 }
375 #endif 376 #endif
376 377
377 return rc; 378 return rc;
378 } 379 }
379 #endif 380 #endif
380 381
381 #if defined(CONFIG_GENERIC_MMC) 382 #if defined(CONFIG_GENERIC_MMC)
382 int board_mmc_init(bd_t *bis) 383 int board_mmc_init(bd_t *bis)
383 { 384 {
384 return omap_mmc_init(0, 0, 0, -1, -1); 385 return omap_mmc_init(0, 0, 0, -1, -1);
385 } 386 }
386 #endif 387 #endif
387 388
388 #if defined(CONFIG_GENERIC_MMC) 389 #if defined(CONFIG_GENERIC_MMC)
389 void board_mmc_power_init(void) 390 void board_mmc_power_init(void)
390 { 391 {
391 twl4030_power_mmc_init(0); 392 twl4030_power_mmc_init(0);
392 } 393 }
393 #endif 394 #endif
394 395
395 #if defined(CONFIG_USB_EHCI) 396 #if defined(CONFIG_USB_EHCI)
396 static struct omap_usbhs_board_data usbhs_bdata = { 397 static struct omap_usbhs_board_data usbhs_bdata = {
397 .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, 398 .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
398 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, 399 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
399 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED 400 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
400 }; 401 };
401 402
402 #define GUMSTIX_GPIO_USBH_CPEN 168 403 #define GUMSTIX_GPIO_USBH_CPEN 168
403 int ehci_hcd_init(int index, enum usb_init_type init, 404 int ehci_hcd_init(int index, enum usb_init_type init,
404 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 405 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
405 { 406 {
406 /* Enable USB power */ 407 /* Enable USB power */
407 if (!gpio_request(GUMSTIX_GPIO_USBH_CPEN, "usbh_cpen")) 408 if (!gpio_request(GUMSTIX_GPIO_USBH_CPEN, "usbh_cpen"))
408 gpio_direction_output(GUMSTIX_GPIO_USBH_CPEN, 1); 409 gpio_direction_output(GUMSTIX_GPIO_USBH_CPEN, 1);
409 410
410 return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); 411 return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
411 } 412 }
412 413
413 int ehci_hcd_stop(void) 414 int ehci_hcd_stop(void)
414 { 415 {
415 /* Disable USB power */ 416 /* Disable USB power */
416 gpio_set_value(GUMSTIX_GPIO_USBH_CPEN, 0); 417 gpio_set_value(GUMSTIX_GPIO_USBH_CPEN, 0);
417 gpio_free(GUMSTIX_GPIO_USBH_CPEN); 418 gpio_free(GUMSTIX_GPIO_USBH_CPEN);
418 419
419 return omap_ehci_hcd_stop(); 420 return omap_ehci_hcd_stop();
420 } 421 }
421 422
422 #endif /* CONFIG_USB_EHCI */ 423 #endif /* CONFIG_USB_EHCI */
423 424
board/quipos/cairo/cairo.c
Diff comments   View file @ 17fa032
1 /* 1 /*
2 * Copyright (c) 2014 DENX 2 * Copyright (c) 2014 DENX
3 * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> 3 * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
4 * 4 *
5 * Derived from code written by Robert Aigner (ra@spiid.net) 5 * Derived from code written by Robert Aigner (ra@spiid.net)
6 * 6 *
7 * Itself derived from Beagle Board and 3430 SDP code by 7 * Itself derived from Beagle Board and 3430 SDP code by
8 * Richard Woodruff <r-woodruff2@ti.com> 8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Syed Mohammed Khasim <khasim@ti.com> 9 * Syed Mohammed Khasim <khasim@ti.com>
10 * 10 *
11 * SPDX-License-Identifier: GPL-2.0+ 11 * SPDX-License-Identifier: GPL-2.0+
12 */ 12 */
13 #include <common.h> 13 #include <common.h>
14 #include <dm.h> 14 #include <dm.h>
15 #include <netdev.h> 15 #include <netdev.h>
16 #include <ns16550.h> 16 #include <ns16550.h>
17 #include <asm/io.h> 17 #include <asm/io.h>
18 #include <asm/arch/mem.h> 18 #include <asm/arch/mem.h>
19 #include <asm/arch/mux.h> 19 #include <asm/arch/mux.h>
20 #include <asm/arch/sys_proto.h> 20 #include <asm/arch/sys_proto.h>
21 #include <i2c.h> 21 #include <i2c.h>
22 #include <asm/mach-types.h> 22 #include <asm/mach-types.h>
23 #include <asm/omap_mmc.h> 23 #include <asm/omap_mmc.h>
24 #include "cairo.h" 24 #include "cairo.h"
25 25
26 DECLARE_GLOBAL_DATA_PTR; 26 DECLARE_GLOBAL_DATA_PTR;
27 27
28 /* 28 /*
29 * MUSB port on OMAP3EVM Rev >= E requires extvbus programming. 29 * MUSB port on OMAP3EVM Rev >= E requires extvbus programming.
30 */ 30 */
31 u8 omap3_evm_need_extvbus(void) 31 u8 omap3_evm_need_extvbus(void)
32 { 32 {
33 u8 retval = 0; 33 u8 retval = 0;
34 34
35 /* TODO: verify if cairo handheld platform needs extvbus programming */ 35 /* TODO: verify if cairo handheld platform needs extvbus programming */
36 36
37 return retval; 37 return retval;
38 } 38 }
39 39
40 /* 40 /*
41 * Routine: board_init 41 * Routine: board_init
42 * Description: Early hardware init. 42 * Description: Early hardware init.
43 */ 43 */
44 int board_init(void) 44 int board_init(void)
45 { 45 {
46 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 46 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
47 /* board id for Linux */ 47 /* board id for Linux */
48 gd->bd->bi_arch_number = MACH_TYPE_OMAP3_CAIRO; 48 gd->bd->bi_arch_number = MACH_TYPE_OMAP3_CAIRO;
49 /* boot param addr */ 49 /* boot param addr */
50 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 50 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
51 return 0; 51 return 0;
52 } 52 }
53 53
54 /* 54 /*
55 * Routine: set_muxconf_regs 55 * Routine: set_muxconf_regs
56 * Description: Setting up the configuration Mux registers specific to the 56 * Description: Setting up the configuration Mux registers specific to the
57 * hardware. Many pins need to be moved from protect to primary 57 * hardware. Many pins need to be moved from protect to primary
58 * mode. 58 * mode.
59 */ 59 */
60 void set_muxconf_regs(void) 60 void set_muxconf_regs(void)
61 { 61 {
62 MUX_CAIRO(); 62 MUX_CAIRO();
63 } 63 }
64 64
65 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 65 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
66 int board_mmc_init(bd_t *bis) 66 int board_mmc_init(bd_t *bis)
67 { 67 {
68 return omap_mmc_init(0, 0, 0, -1, -1); 68 return omap_mmc_init(0, 0, 0, -1, -1);
69 } 69 }
70 #endif 70 #endif
71 71
72 #ifdef CONFIG_SPL_BUILD 72 #ifdef CONFIG_SPL_BUILD
73 /* 73 /*
74 * Routine: get_board_mem_timings 74 * Routine: get_board_mem_timings
75 * Description: If we use SPL then there is no x-loader nor config header 75 * Description: If we use SPL then there is no x-loader nor config header
76 * so we have to setup the DDR timings ourself on the first bank. This 76 * so we have to setup the DDR timings ourself on the first bank. This
77 * provides the timing values back to the function that configures 77 * provides the timing values back to the function that configures
78 * the memory. 78 * the memory.
79 * 79 *
80 * The Cairo board uses SAMSUNG DDR - K4X51163PG-FGC6 80 * The Cairo board uses SAMSUNG DDR - K4X51163PG-FGC6
81 */ 81 */
82 void get_board_mem_timings(struct board_sdrc_timings *timings) 82 void get_board_mem_timings(struct board_sdrc_timings *timings)
83 { 83 {
84 timings->sharing = SAMSUNG_SHARING; 84 timings->sharing = SAMSUNG_SHARING;
85 timings->mcfg = SAMSUNG_V_MCFG_165(128 << 20); 85 timings->mcfg = SAMSUNG_V_MCFG_165(128 << 20);
86 timings->ctrla = SAMSUNG_V_ACTIMA_165; 86 timings->ctrla = SAMSUNG_V_ACTIMA_165;
87 timings->ctrlb = SAMSUNG_V_ACTIMB_165; 87 timings->ctrlb = SAMSUNG_V_ACTIMB_165;
88 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 88 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
89 timings->mr = SAMSUNG_V_MR_165; 89 timings->mr = SAMSUNG_V_MR_165;
90 } 90 }
91 #endif 91 #endif
92 92
93 static const struct ns16550_platdata cairo_serial = { 93 static const struct ns16550_platdata cairo_serial = {
94 .base = OMAP34XX_UART2, 94 .base = OMAP34XX_UART2,
95 .reg_shift = 2, 95 .reg_shift = 2,
96 .clock = V_NS16550_CLK 96 .clock = V_NS16550_CLK,
97 .fcr = UART_FCR_DEFVAL,
97 }; 98 };
98 99
99 U_BOOT_DEVICE(cairo_uart) = { 100 U_BOOT_DEVICE(cairo_uart) = {
100 "ns16550_serial", 101 "ns16550_serial",
101 &cairo_serial 102 &cairo_serial
102 }; 103 };
103 104
104 /* force SPL booting into U-Boot, not Linux */ 105 /* force SPL booting into U-Boot, not Linux */
105 #ifdef CONFIG_SPL_OS_BOOT 106 #ifdef CONFIG_SPL_OS_BOOT
106 int spl_start_uboot(void) 107 int spl_start_uboot(void)
107 { 108 {
108 return 1; 109 return 1;
109 } 110 }
110 #endif 111 #endif
111 112
board/ti/beagle/beagle.c
Diff comments   View file @ 17fa032
1 /* 1 /*
2 * (C) Copyright 2004-2011 2 * (C) Copyright 2004-2011
3 * Texas Instruments, <www.ti.com> 3 * Texas Instruments, <www.ti.com>
4 * 4 *
5 * Author : 5 * Author :
6 * Sunil Kumar <sunilsaini05@gmail.com> 6 * Sunil Kumar <sunilsaini05@gmail.com>
7 * Shashi Ranjan <shashiranjanmca05@gmail.com> 7 * Shashi Ranjan <shashiranjanmca05@gmail.com>
8 * 8 *
9 * Derived from Beagle Board and 3430 SDP code by 9 * Derived from Beagle Board and 3430 SDP code by
10 * Richard Woodruff <r-woodruff2@ti.com> 10 * Richard Woodruff <r-woodruff2@ti.com>
11 * Syed Mohammed Khasim <khasim@ti.com> 11 * Syed Mohammed Khasim <khasim@ti.com>
12 * 12 *
13 * 13 *
14 * SPDX-License-Identifier: GPL-2.0+ 14 * SPDX-License-Identifier: GPL-2.0+
15 */ 15 */
16 #include <common.h> 16 #include <common.h>
17 #include <dm.h> 17 #include <dm.h>
18 #include <ns16550.h> 18 #include <ns16550.h>
19 #ifdef CONFIG_STATUS_LED 19 #ifdef CONFIG_STATUS_LED
20 #include <status_led.h> 20 #include <status_led.h>
21 #endif 21 #endif
22 #include <twl4030.h> 22 #include <twl4030.h>
23 #include <linux/mtd/nand.h> 23 #include <linux/mtd/nand.h>
24 #include <asm/io.h> 24 #include <asm/io.h>
25 #include <asm/arch/mmc_host_def.h> 25 #include <asm/arch/mmc_host_def.h>
26 #include <asm/arch/mux.h> 26 #include <asm/arch/mux.h>
27 #include <asm/arch/mem.h> 27 #include <asm/arch/mem.h>
28 #include <asm/arch/sys_proto.h> 28 #include <asm/arch/sys_proto.h>
29 #include <asm/gpio.h> 29 #include <asm/gpio.h>
30 #include <asm/mach-types.h> 30 #include <asm/mach-types.h>
31 #include <asm/omap_musb.h> 31 #include <asm/omap_musb.h>
32 #include <linux/errno.h> 32 #include <linux/errno.h>
33 #include <linux/usb/ch9.h> 33 #include <linux/usb/ch9.h>
34 #include <linux/usb/gadget.h> 34 #include <linux/usb/gadget.h>
35 #include <linux/usb/musb.h> 35 #include <linux/usb/musb.h>
36 #include "beagle.h" 36 #include "beagle.h"
37 #include <command.h> 37 #include <command.h>
38 38
39 #ifdef CONFIG_USB_EHCI 39 #ifdef CONFIG_USB_EHCI
40 #include <usb.h> 40 #include <usb.h>
41 #include <asm/ehci-omap.h> 41 #include <asm/ehci-omap.h>
42 #endif 42 #endif
43 43
44 #define TWL4030_I2C_BUS 0 44 #define TWL4030_I2C_BUS 0
45 #define EXPANSION_EEPROM_I2C_BUS 1 45 #define EXPANSION_EEPROM_I2C_BUS 1
46 #define EXPANSION_EEPROM_I2C_ADDRESS 0x50 46 #define EXPANSION_EEPROM_I2C_ADDRESS 0x50
47 47
48 #define TINCANTOOLS_ZIPPY 0x01000100 48 #define TINCANTOOLS_ZIPPY 0x01000100
49 #define TINCANTOOLS_ZIPPY2 0x02000100 49 #define TINCANTOOLS_ZIPPY2 0x02000100
50 #define TINCANTOOLS_TRAINER 0x04000100 50 #define TINCANTOOLS_TRAINER 0x04000100
51 #define TINCANTOOLS_SHOWDOG 0x03000100 51 #define TINCANTOOLS_SHOWDOG 0x03000100
52 #define KBADC_BEAGLEFPGA 0x01000600 52 #define KBADC_BEAGLEFPGA 0x01000600
53 #define LW_BEAGLETOUCH 0x01000700 53 #define LW_BEAGLETOUCH 0x01000700
54 #define BRAINMUX_LCDOG 0x01000800 54 #define BRAINMUX_LCDOG 0x01000800
55 #define BRAINMUX_LCDOGTOUCH 0x02000800 55 #define BRAINMUX_LCDOGTOUCH 0x02000800
56 #define BBTOYS_WIFI 0x01000B00 56 #define BBTOYS_WIFI 0x01000B00
57 #define BBTOYS_VGA 0x02000B00 57 #define BBTOYS_VGA 0x02000B00
58 #define BBTOYS_LCD 0x03000B00 58 #define BBTOYS_LCD 0x03000B00
59 #define BCT_BRETTL3 0x01000F00 59 #define BCT_BRETTL3 0x01000F00
60 #define BCT_BRETTL4 0x02000F00 60 #define BCT_BRETTL4 0x02000F00
61 #define LSR_COM6L_ADPT 0x01001300 61 #define LSR_COM6L_ADPT 0x01001300
62 #define BEAGLE_NO_EEPROM 0xffffffff 62 #define BEAGLE_NO_EEPROM 0xffffffff
63 63
64 DECLARE_GLOBAL_DATA_PTR; 64 DECLARE_GLOBAL_DATA_PTR;
65 65
66 static struct { 66 static struct {
67 unsigned int device_vendor; 67 unsigned int device_vendor;
68 unsigned char revision; 68 unsigned char revision;
69 unsigned char content; 69 unsigned char content;
70 char fab_revision[8]; 70 char fab_revision[8];
71 char env_var[16]; 71 char env_var[16];
72 char env_setting[64]; 72 char env_setting[64];
73 } expansion_config; 73 } expansion_config;
74 74
75 static const struct ns16550_platdata beagle_serial = { 75 static const struct ns16550_platdata beagle_serial = {
76 .base = OMAP34XX_UART3, 76 .base = OMAP34XX_UART3,
77 .reg_shift = 2, 77 .reg_shift = 2,
78 .clock = V_NS16550_CLK 78 .clock = V_NS16550_CLK,
79 .fcr = UART_FCR_DEFVAL,
79 }; 80 };
80 81
81 U_BOOT_DEVICE(beagle_uart) = { 82 U_BOOT_DEVICE(beagle_uart) = {
82 "ns16550_serial", 83 "ns16550_serial",
83 &beagle_serial 84 &beagle_serial
84 }; 85 };
85 86
86 /* 87 /*
87 * Routine: board_init 88 * Routine: board_init
88 * Description: Early hardware init. 89 * Description: Early hardware init.
89 */ 90 */
90 int board_init(void) 91 int board_init(void)
91 { 92 {
92 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 93 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
93 /* board id for Linux */ 94 /* board id for Linux */
94 gd->bd->bi_arch_number = MACH_TYPE_OMAP3_BEAGLE; 95 gd->bd->bi_arch_number = MACH_TYPE_OMAP3_BEAGLE;
95 /* boot param addr */ 96 /* boot param addr */
96 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 97 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
97 98
98 #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) 99 #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
99 status_led_set (STATUS_LED_BOOT, STATUS_LED_ON); 100 status_led_set (STATUS_LED_BOOT, STATUS_LED_ON);
100 #endif 101 #endif
101 102
102 return 0; 103 return 0;
103 } 104 }
104 105
105 /* 106 /*
106 * Routine: get_board_revision 107 * Routine: get_board_revision
107 * Description: Detect if we are running on a Beagle revision Ax/Bx, 108 * Description: Detect if we are running on a Beagle revision Ax/Bx,
108 * C1/2/3, C4, xM Ax/Bx or xM Cx. This can be done by reading 109 * C1/2/3, C4, xM Ax/Bx or xM Cx. This can be done by reading
109 * the level of GPIO173, GPIO172 and GPIO171. This should 110 * the level of GPIO173, GPIO172 and GPIO171. This should
110 * result in 111 * result in
111 * GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx 112 * GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx
112 * GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3 113 * GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3
113 * GPIO173, GPIO172, GPIO171: 1 0 1 => C4 114 * GPIO173, GPIO172, GPIO171: 1 0 1 => C4
114 * GPIO173, GPIO172, GPIO171: 0 1 0 => xM Cx 115 * GPIO173, GPIO172, GPIO171: 0 1 0 => xM Cx
115 * GPIO173, GPIO172, GPIO171: 0 0 0 => xM Ax/Bx 116 * GPIO173, GPIO172, GPIO171: 0 0 0 => xM Ax/Bx
116 */ 117 */
117 static int get_board_revision(void) 118 static int get_board_revision(void)
118 { 119 {
119 static int revision = -1; 120 static int revision = -1;
120 121
121 if (revision == -1) { 122 if (revision == -1) {
122 if (!gpio_request(171, "rev0") && 123 if (!gpio_request(171, "rev0") &&
123 !gpio_request(172, "rev1") && 124 !gpio_request(172, "rev1") &&
124 !gpio_request(173, "rev2")) { 125 !gpio_request(173, "rev2")) {
125 gpio_direction_input(171); 126 gpio_direction_input(171);
126 gpio_direction_input(172); 127 gpio_direction_input(172);
127 gpio_direction_input(173); 128 gpio_direction_input(173);
128 129
129 revision = gpio_get_value(173) << 2 | 130 revision = gpio_get_value(173) << 2 |
130 gpio_get_value(172) << 1 | 131 gpio_get_value(172) << 1 |
131 gpio_get_value(171); 132 gpio_get_value(171);
132 } else { 133 } else {
133 printf("Error: unable to acquire board revision GPIOs\n"); 134 printf("Error: unable to acquire board revision GPIOs\n");
134 } 135 }
135 } 136 }
136 137
137 return revision; 138 return revision;
138 } 139 }
139 140
140 #ifdef CONFIG_SPL_BUILD 141 #ifdef CONFIG_SPL_BUILD
141 /* 142 /*
142 * Routine: get_board_mem_timings 143 * Routine: get_board_mem_timings
143 * Description: If we use SPL then there is no x-loader nor config header 144 * Description: If we use SPL then there is no x-loader nor config header
144 * so we have to setup the DDR timings ourself on both banks. 145 * so we have to setup the DDR timings ourself on both banks.
145 */ 146 */
146 void get_board_mem_timings(struct board_sdrc_timings *timings) 147 void get_board_mem_timings(struct board_sdrc_timings *timings)
147 { 148 {
148 int pop_mfr, pop_id; 149 int pop_mfr, pop_id;
149 150
150 /* 151 /*
151 * We need to identify what PoP memory is on the board so that 152 * We need to identify what PoP memory is on the board so that
152 * we know what timings to use. If we can't identify it then 153 * we know what timings to use. If we can't identify it then
153 * we know it's an xM. To map the ID values please see nand_ids.c 154 * we know it's an xM. To map the ID values please see nand_ids.c
154 */ 155 */
155 identify_nand_chip(&pop_mfr, &pop_id); 156 identify_nand_chip(&pop_mfr, &pop_id);
156 157
157 timings->mr = MICRON_V_MR_165; 158 timings->mr = MICRON_V_MR_165;
158 switch (get_board_revision()) { 159 switch (get_board_revision()) {
159 case REVISION_C4: 160 case REVISION_C4:
160 if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) { 161 if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) {
161 /* 512MB DDR */ 162 /* 512MB DDR */
162 timings->mcfg = NUMONYX_V_MCFG_165(512 << 20); 163 timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
163 timings->ctrla = NUMONYX_V_ACTIMA_165; 164 timings->ctrla = NUMONYX_V_ACTIMA_165;
164 timings->ctrlb = NUMONYX_V_ACTIMB_165; 165 timings->ctrlb = NUMONYX_V_ACTIMB_165;
165 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 166 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
166 break; 167 break;
167 } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xba) { 168 } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xba) {
168 /* Beagleboard Rev C4, 512MB Nand/256MB DDR*/ 169 /* Beagleboard Rev C4, 512MB Nand/256MB DDR*/
169 timings->mcfg = MICRON_V_MCFG_165(128 << 20); 170 timings->mcfg = MICRON_V_MCFG_165(128 << 20);
170 timings->ctrla = MICRON_V_ACTIMA_165; 171 timings->ctrla = MICRON_V_ACTIMA_165;
171 timings->ctrlb = MICRON_V_ACTIMB_165; 172 timings->ctrlb = MICRON_V_ACTIMB_165;
172 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 173 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
173 break; 174 break;
174 } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) { 175 } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) {
175 /* Beagleboard Rev C5, 256MB DDR */ 176 /* Beagleboard Rev C5, 256MB DDR */
176 timings->mcfg = MICRON_V_MCFG_200(256 << 20); 177 timings->mcfg = MICRON_V_MCFG_200(256 << 20);
177 timings->ctrla = MICRON_V_ACTIMA_200; 178 timings->ctrla = MICRON_V_ACTIMA_200;
178 timings->ctrlb = MICRON_V_ACTIMB_200; 179 timings->ctrlb = MICRON_V_ACTIMB_200;
179 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 180 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
180 break; 181 break;
181 } 182 }
182 case REVISION_XM_AB: 183 case REVISION_XM_AB:
183 case REVISION_XM_C: 184 case REVISION_XM_C:
184 if (pop_mfr == 0) { 185 if (pop_mfr == 0) {
185 /* 256MB DDR */ 186 /* 256MB DDR */
186 timings->mcfg = MICRON_V_MCFG_200(256 << 20); 187 timings->mcfg = MICRON_V_MCFG_200(256 << 20);
187 timings->ctrla = MICRON_V_ACTIMA_200; 188 timings->ctrla = MICRON_V_ACTIMA_200;
188 timings->ctrlb = MICRON_V_ACTIMB_200; 189 timings->ctrlb = MICRON_V_ACTIMB_200;
189 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 190 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
190 } else { 191 } else {
191 /* 512MB DDR */ 192 /* 512MB DDR */
192 timings->mcfg = NUMONYX_V_MCFG_165(512 << 20); 193 timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
193 timings->ctrla = NUMONYX_V_ACTIMA_165; 194 timings->ctrla = NUMONYX_V_ACTIMA_165;
194 timings->ctrlb = NUMONYX_V_ACTIMB_165; 195 timings->ctrlb = NUMONYX_V_ACTIMB_165;
195 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 196 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
196 } 197 }
197 break; 198 break;
198 default: 199 default:
199 /* Assume 128MB and Micron/165MHz timings to be safe */ 200 /* Assume 128MB and Micron/165MHz timings to be safe */
200 timings->mcfg = MICRON_V_MCFG_165(128 << 20); 201 timings->mcfg = MICRON_V_MCFG_165(128 << 20);
201 timings->ctrla = MICRON_V_ACTIMA_165; 202 timings->ctrla = MICRON_V_ACTIMA_165;
202 timings->ctrlb = MICRON_V_ACTIMB_165; 203 timings->ctrlb = MICRON_V_ACTIMB_165;
203 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 204 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
204 } 205 }
205 } 206 }
206 #endif 207 #endif
207 208
208 /* 209 /*
209 * Routine: get_expansion_id 210 * Routine: get_expansion_id
210 * Description: This function checks for expansion board by checking I2C 211 * Description: This function checks for expansion board by checking I2C
211 * bus 1 for the availability of an AT24C01B serial EEPROM. 212 * bus 1 for the availability of an AT24C01B serial EEPROM.
212 * returns the device_vendor field from the EEPROM 213 * returns the device_vendor field from the EEPROM
213 */ 214 */
214 static unsigned int get_expansion_id(void) 215 static unsigned int get_expansion_id(void)
215 { 216 {
216 i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS); 217 i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS);
217 218
218 /* return BEAGLE_NO_EEPROM if eeprom doesn't respond */ 219 /* return BEAGLE_NO_EEPROM if eeprom doesn't respond */
219 if (i2c_probe(EXPANSION_EEPROM_I2C_ADDRESS) == 1) { 220 if (i2c_probe(EXPANSION_EEPROM_I2C_ADDRESS) == 1) {
220 i2c_set_bus_num(TWL4030_I2C_BUS); 221 i2c_set_bus_num(TWL4030_I2C_BUS);
221 return BEAGLE_NO_EEPROM; 222 return BEAGLE_NO_EEPROM;
222 } 223 }
223 224
224 /* read configuration data */ 225 /* read configuration data */
225 i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config, 226 i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config,
226 sizeof(expansion_config)); 227 sizeof(expansion_config));
227 228
228 /* retry reading configuration data with 16bit addressing */ 229 /* retry reading configuration data with 16bit addressing */
229 if ((expansion_config.device_vendor == 0xFFFFFF00) || 230 if ((expansion_config.device_vendor == 0xFFFFFF00) ||
230 (expansion_config.device_vendor == 0xFFFFFFFF)) { 231 (expansion_config.device_vendor == 0xFFFFFFFF)) {
231 printf("EEPROM is blank or 8bit addressing failed: retrying with 16bit:\n"); 232 printf("EEPROM is blank or 8bit addressing failed: retrying with 16bit:\n");
232 i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 2, (u8 *)&expansion_config, 233 i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 2, (u8 *)&expansion_config,
233 sizeof(expansion_config)); 234 sizeof(expansion_config));
234 } 235 }
235 236
236 i2c_set_bus_num(TWL4030_I2C_BUS); 237 i2c_set_bus_num(TWL4030_I2C_BUS);
237 238
238 return expansion_config.device_vendor; 239 return expansion_config.device_vendor;
239 } 240 }
240 241
241 #ifdef CONFIG_VIDEO_OMAP3 242 #ifdef CONFIG_VIDEO_OMAP3
242 /* 243 /*
243 * Configure DSS to display background color on DVID 244 * Configure DSS to display background color on DVID
244 * Configure VENC to display color bar on S-Video 245 * Configure VENC to display color bar on S-Video
245 */ 246 */
246 static void beagle_display_init(void) 247 static void beagle_display_init(void)
247 { 248 {
248 omap3_dss_venc_config(&venc_config_std_tv, VENC_HEIGHT, VENC_WIDTH); 249 omap3_dss_venc_config(&venc_config_std_tv, VENC_HEIGHT, VENC_WIDTH);
249 switch (get_board_revision()) { 250 switch (get_board_revision()) {
250 case REVISION_AXBX: 251 case REVISION_AXBX:
251 case REVISION_CX: 252 case REVISION_CX:
252 case REVISION_C4: 253 case REVISION_C4:
253 omap3_dss_panel_config(&dvid_cfg); 254 omap3_dss_panel_config(&dvid_cfg);
254 break; 255 break;
255 case REVISION_XM_AB: 256 case REVISION_XM_AB:
256 case REVISION_XM_C: 257 case REVISION_XM_C:
257 default: 258 default:
258 omap3_dss_panel_config(&dvid_cfg_xm); 259 omap3_dss_panel_config(&dvid_cfg_xm);
259 break; 260 break;
260 } 261 }
261 } 262 }
262 263
263 /* 264 /*
264 * Enable DVI power 265 * Enable DVI power
265 */ 266 */
266 static void beagle_dvi_pup(void) 267 static void beagle_dvi_pup(void)
267 { 268 {
268 uchar val; 269 uchar val;
269 270
270 switch (get_board_revision()) { 271 switch (get_board_revision()) {
271 case REVISION_AXBX: 272 case REVISION_AXBX:
272 case REVISION_CX: 273 case REVISION_CX:
273 case REVISION_C4: 274 case REVISION_C4:
274 gpio_request(170, "dvi"); 275 gpio_request(170, "dvi");
275 gpio_direction_output(170, 0); 276 gpio_direction_output(170, 0);
276 gpio_set_value(170, 1); 277 gpio_set_value(170, 1);
277 break; 278 break;
278 case REVISION_XM_AB: 279 case REVISION_XM_AB:
279 case REVISION_XM_C: 280 case REVISION_XM_C:
280 default: 281 default:
281 #define GPIODATADIR1 (TWL4030_BASEADD_GPIO+3) 282 #define GPIODATADIR1 (TWL4030_BASEADD_GPIO+3)
282 #define GPIODATAOUT1 (TWL4030_BASEADD_GPIO+6) 283 #define GPIODATAOUT1 (TWL4030_BASEADD_GPIO+6)
283 284
284 i2c_read(TWL4030_CHIP_GPIO, GPIODATADIR1, 1, &val, 1); 285 i2c_read(TWL4030_CHIP_GPIO, GPIODATADIR1, 1, &val, 1);
285 val |= 4; 286 val |= 4;
286 i2c_write(TWL4030_CHIP_GPIO, GPIODATADIR1, 1, &val, 1); 287 i2c_write(TWL4030_CHIP_GPIO, GPIODATADIR1, 1, &val, 1);
287 288
288 i2c_read(TWL4030_CHIP_GPIO, GPIODATAOUT1, 1, &val, 1); 289 i2c_read(TWL4030_CHIP_GPIO, GPIODATAOUT1, 1, &val, 1);
289 val |= 4; 290 val |= 4;
290 i2c_write(TWL4030_CHIP_GPIO, GPIODATAOUT1, 1, &val, 1); 291 i2c_write(TWL4030_CHIP_GPIO, GPIODATAOUT1, 1, &val, 1);
291 break; 292 break;
292 } 293 }
293 } 294 }
294 #endif 295 #endif
295 296
296 #ifdef CONFIG_USB_MUSB_OMAP2PLUS 297 #ifdef CONFIG_USB_MUSB_OMAP2PLUS
297 static struct musb_hdrc_config musb_config = { 298 static struct musb_hdrc_config musb_config = {
298 .multipoint = 1, 299 .multipoint = 1,
299 .dyn_fifo = 1, 300 .dyn_fifo = 1,
300 .num_eps = 16, 301 .num_eps = 16,
301 .ram_bits = 12, 302 .ram_bits = 12,
302 }; 303 };
303 304
304 static struct omap_musb_board_data musb_board_data = { 305 static struct omap_musb_board_data musb_board_data = {
305 .interface_type = MUSB_INTERFACE_ULPI, 306 .interface_type = MUSB_INTERFACE_ULPI,
306 }; 307 };
307 308
308 static struct musb_hdrc_platform_data musb_plat = { 309 static struct musb_hdrc_platform_data musb_plat = {
309 #if defined(CONFIG_USB_MUSB_HOST) 310 #if defined(CONFIG_USB_MUSB_HOST)
310 .mode = MUSB_HOST, 311 .mode = MUSB_HOST,
311 #elif defined(CONFIG_USB_MUSB_GADGET) 312 #elif defined(CONFIG_USB_MUSB_GADGET)
312 .mode = MUSB_PERIPHERAL, 313 .mode = MUSB_PERIPHERAL,
313 #else 314 #else
314 #error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET" 315 #error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET"
315 #endif 316 #endif
316 .config = &musb_config, 317 .config = &musb_config,
317 .power = 100, 318 .power = 100,
318 .platform_ops = &omap2430_ops, 319 .platform_ops = &omap2430_ops,
319 .board_data = &musb_board_data, 320 .board_data = &musb_board_data,
320 }; 321 };
321 #endif 322 #endif
322 323
323 /* 324 /*
324 * Routine: misc_init_r 325 * Routine: misc_init_r
325 * Description: Configure board specific parts 326 * Description: Configure board specific parts
326 */ 327 */
327 int misc_init_r(void) 328 int misc_init_r(void)
328 { 329 {
329 struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE; 330 struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
330 struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE; 331 struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
331 struct control_prog_io *prog_io_base = (struct control_prog_io *)OMAP34XX_CTRL_BASE; 332 struct control_prog_io *prog_io_base = (struct control_prog_io *)OMAP34XX_CTRL_BASE;
332 bool generate_fake_mac = false; 333 bool generate_fake_mac = false;
333 u32 value; 334 u32 value;
334 335
335 /* Enable i2c2 pullup resisters */ 336 /* Enable i2c2 pullup resisters */
336 value = readl(&prog_io_base->io1); 337 value = readl(&prog_io_base->io1);
337 value &= ~(PRG_I2C2_PULLUPRESX); 338 value &= ~(PRG_I2C2_PULLUPRESX);
338 writel(value, &prog_io_base->io1); 339 writel(value, &prog_io_base->io1);
339 340
340 switch (get_board_revision()) { 341 switch (get_board_revision()) {
341 case REVISION_AXBX: 342 case REVISION_AXBX:
342 printf("Beagle Rev Ax/Bx\n"); 343 printf("Beagle Rev Ax/Bx\n");
343 setenv("beaglerev", "AxBx"); 344 setenv("beaglerev", "AxBx");
344 break; 345 break;
345 case REVISION_CX: 346 case REVISION_CX:
346 printf("Beagle Rev C1/C2/C3\n"); 347 printf("Beagle Rev C1/C2/C3\n");
347 setenv("beaglerev", "Cx"); 348 setenv("beaglerev", "Cx");
348 MUX_BEAGLE_C(); 349 MUX_BEAGLE_C();
349 break; 350 break;
350 case REVISION_C4: 351 case REVISION_C4:
351 printf("Beagle Rev C4\n"); 352 printf("Beagle Rev C4\n");
352 setenv("beaglerev", "C4"); 353 setenv("beaglerev", "C4");
353 MUX_BEAGLE_C(); 354 MUX_BEAGLE_C();
354 /* Set VAUX2 to 1.8V for EHCI PHY */ 355 /* Set VAUX2 to 1.8V for EHCI PHY */
355 twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED, 356 twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
356 TWL4030_PM_RECEIVER_VAUX2_VSEL_18, 357 TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
357 TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, 358 TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
358 TWL4030_PM_RECEIVER_DEV_GRP_P1); 359 TWL4030_PM_RECEIVER_DEV_GRP_P1);
359 break; 360 break;
360 case REVISION_XM_AB: 361 case REVISION_XM_AB:
361 printf("Beagle xM Rev A/B\n"); 362 printf("Beagle xM Rev A/B\n");
362 setenv("beaglerev", "xMAB"); 363 setenv("beaglerev", "xMAB");
363 MUX_BEAGLE_XM(); 364 MUX_BEAGLE_XM();
364 /* Set VAUX2 to 1.8V for EHCI PHY */ 365 /* Set VAUX2 to 1.8V for EHCI PHY */
365 twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED, 366 twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
366 TWL4030_PM_RECEIVER_VAUX2_VSEL_18, 367 TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
367 TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, 368 TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
368 TWL4030_PM_RECEIVER_DEV_GRP_P1); 369 TWL4030_PM_RECEIVER_DEV_GRP_P1);
369 generate_fake_mac = true; 370 generate_fake_mac = true;
370 break; 371 break;
371 case REVISION_XM_C: 372 case REVISION_XM_C:
372 printf("Beagle xM Rev C\n"); 373 printf("Beagle xM Rev C\n");
373 setenv("beaglerev", "xMC"); 374 setenv("beaglerev", "xMC");
374 MUX_BEAGLE_XM(); 375 MUX_BEAGLE_XM();
375 /* Set VAUX2 to 1.8V for EHCI PHY */ 376 /* Set VAUX2 to 1.8V for EHCI PHY */
376 twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED, 377 twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
377 TWL4030_PM_RECEIVER_VAUX2_VSEL_18, 378 TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
378 TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, 379 TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
379 TWL4030_PM_RECEIVER_DEV_GRP_P1); 380 TWL4030_PM_RECEIVER_DEV_GRP_P1);
380 generate_fake_mac = true; 381 generate_fake_mac = true;
381 break; 382 break;
382 default: 383 default:
383 printf("Beagle unknown 0x%02x\n", get_board_revision()); 384 printf("Beagle unknown 0x%02x\n", get_board_revision());
384 MUX_BEAGLE_XM(); 385 MUX_BEAGLE_XM();
385 /* Set VAUX2 to 1.8V for EHCI PHY */ 386 /* Set VAUX2 to 1.8V for EHCI PHY */
386 twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED, 387 twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
387 TWL4030_PM_RECEIVER_VAUX2_VSEL_18, 388 TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
388 TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, 389 TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
389 TWL4030_PM_RECEIVER_DEV_GRP_P1); 390 TWL4030_PM_RECEIVER_DEV_GRP_P1);
390 generate_fake_mac = true; 391 generate_fake_mac = true;
391 } 392 }
392 393
393 switch (get_expansion_id()) { 394 switch (get_expansion_id()) {
394 case TINCANTOOLS_ZIPPY: 395 case TINCANTOOLS_ZIPPY:
395 printf("Recognized Tincantools Zippy board (rev %d %s)\n", 396 printf("Recognized Tincantools Zippy board (rev %d %s)\n",
396 expansion_config.revision, 397 expansion_config.revision,
397 expansion_config.fab_revision); 398 expansion_config.fab_revision);
398 MUX_TINCANTOOLS_ZIPPY(); 399 MUX_TINCANTOOLS_ZIPPY();
399 setenv("buddy", "zippy"); 400 setenv("buddy", "zippy");
400 break; 401 break;
401 case TINCANTOOLS_ZIPPY2: 402 case TINCANTOOLS_ZIPPY2:
402 printf("Recognized Tincantools Zippy2 board (rev %d %s)\n", 403 printf("Recognized Tincantools Zippy2 board (rev %d %s)\n",
403 expansion_config.revision, 404 expansion_config.revision,
404 expansion_config.fab_revision); 405 expansion_config.fab_revision);
405 MUX_TINCANTOOLS_ZIPPY(); 406 MUX_TINCANTOOLS_ZIPPY();
406 setenv("buddy", "zippy2"); 407 setenv("buddy", "zippy2");
407 break; 408 break;
408 case TINCANTOOLS_TRAINER: 409 case TINCANTOOLS_TRAINER:
409 printf("Recognized Tincantools Trainer board (rev %d %s)\n", 410 printf("Recognized Tincantools Trainer board (rev %d %s)\n",
410 expansion_config.revision, 411 expansion_config.revision,
411 expansion_config.fab_revision); 412 expansion_config.fab_revision);
412 MUX_TINCANTOOLS_ZIPPY(); 413 MUX_TINCANTOOLS_ZIPPY();
413 MUX_TINCANTOOLS_TRAINER(); 414 MUX_TINCANTOOLS_TRAINER();
414 setenv("buddy", "trainer"); 415 setenv("buddy", "trainer");
415 break; 416 break;
416 case TINCANTOOLS_SHOWDOG: 417 case TINCANTOOLS_SHOWDOG:
417 printf("Recognized Tincantools Showdow board (rev %d %s)\n", 418 printf("Recognized Tincantools Showdow board (rev %d %s)\n",
418 expansion_config.revision, 419 expansion_config.revision,
419 expansion_config.fab_revision); 420 expansion_config.fab_revision);
420 /* Place holder for DSS2 definition for showdog lcd */ 421 /* Place holder for DSS2 definition for showdog lcd */
421 setenv("defaultdisplay", "showdoglcd"); 422 setenv("defaultdisplay", "showdoglcd");
422 setenv("buddy", "showdog"); 423 setenv("buddy", "showdog");
423 break; 424 break;
424 case KBADC_BEAGLEFPGA: 425 case KBADC_BEAGLEFPGA:
425 printf("Recognized KBADC Beagle FPGA board\n"); 426 printf("Recognized KBADC Beagle FPGA board\n");
426 MUX_KBADC_BEAGLEFPGA(); 427 MUX_KBADC_BEAGLEFPGA();
427 setenv("buddy", "beaglefpga"); 428 setenv("buddy", "beaglefpga");
428 break; 429 break;
429 case LW_BEAGLETOUCH: 430 case LW_BEAGLETOUCH:
430 printf("Recognized Liquidware BeagleTouch board\n"); 431 printf("Recognized Liquidware BeagleTouch board\n");
431 setenv("buddy", "beagletouch"); 432 setenv("buddy", "beagletouch");
432 break; 433 break;
433 case BRAINMUX_LCDOG: 434 case BRAINMUX_LCDOG:
434 printf("Recognized Brainmux LCDog board\n"); 435 printf("Recognized Brainmux LCDog board\n");
435 setenv("buddy", "lcdog"); 436 setenv("buddy", "lcdog");
436 break; 437 break;
437 case BRAINMUX_LCDOGTOUCH: 438 case BRAINMUX_LCDOGTOUCH:
438 printf("Recognized Brainmux LCDog Touch board\n"); 439 printf("Recognized Brainmux LCDog Touch board\n");
439 setenv("buddy", "lcdogtouch"); 440 setenv("buddy", "lcdogtouch");
440 break; 441 break;
441 case BBTOYS_WIFI: 442 case BBTOYS_WIFI:
442 printf("Recognized BeagleBoardToys WiFi board\n"); 443 printf("Recognized BeagleBoardToys WiFi board\n");
443 MUX_BBTOYS_WIFI() 444 MUX_BBTOYS_WIFI()
444 setenv("buddy", "bbtoys-wifi"); 445 setenv("buddy", "bbtoys-wifi");
445 break;; 446 break;;
446 case BBTOYS_VGA: 447 case BBTOYS_VGA:
447 printf("Recognized BeagleBoardToys VGA board\n"); 448 printf("Recognized BeagleBoardToys VGA board\n");
448 break;; 449 break;;
449 case BBTOYS_LCD: 450 case BBTOYS_LCD:
450 printf("Recognized BeagleBoardToys LCD board\n"); 451 printf("Recognized BeagleBoardToys LCD board\n");
451 break;; 452 break;;
452 case BCT_BRETTL3: 453 case BCT_BRETTL3:
453 printf("Recognized bct electronic GmbH brettl3 board\n"); 454 printf("Recognized bct electronic GmbH brettl3 board\n");
454 break; 455 break;
455 case BCT_BRETTL4: 456 case BCT_BRETTL4:
456 printf("Recognized bct electronic GmbH brettl4 board\n"); 457 printf("Recognized bct electronic GmbH brettl4 board\n");
457 break; 458 break;
458 case LSR_COM6L_ADPT: 459 case LSR_COM6L_ADPT:
459 printf("Recognized LSR COM6L Adapter Board\n"); 460 printf("Recognized LSR COM6L Adapter Board\n");
460 MUX_BBTOYS_WIFI() 461 MUX_BBTOYS_WIFI()
461 setenv("buddy", "lsr-com6l-adpt"); 462 setenv("buddy", "lsr-com6l-adpt");
462 break; 463 break;
463 case BEAGLE_NO_EEPROM: 464 case BEAGLE_NO_EEPROM:
464 printf("No EEPROM on expansion board\n"); 465 printf("No EEPROM on expansion board\n");
465 setenv("buddy", "none"); 466 setenv("buddy", "none");
466 break; 467 break;
467 default: 468 default:
468 printf("Unrecognized expansion board: %x\n", 469 printf("Unrecognized expansion board: %x\n",
469 expansion_config.device_vendor); 470 expansion_config.device_vendor);
470 setenv("buddy", "unknown"); 471 setenv("buddy", "unknown");
471 } 472 }
472 473
473 if (expansion_config.content == 1) 474 if (expansion_config.content == 1)
474 setenv(expansion_config.env_var, expansion_config.env_setting); 475 setenv(expansion_config.env_var, expansion_config.env_setting);
475 476
476 twl4030_power_init(); 477 twl4030_power_init();
477 switch (get_board_revision()) { 478 switch (get_board_revision()) {
478 case REVISION_XM_AB: 479 case REVISION_XM_AB:
479 twl4030_led_init(TWL4030_LED_LEDEN_LEDBON); 480 twl4030_led_init(TWL4030_LED_LEDEN_LEDBON);
480 break; 481 break;
481 default: 482 default:
482 twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); 483 twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
483 break; 484 break;
484 } 485 }
485 486
486 /* Set GPIO states before they are made outputs */ 487 /* Set GPIO states before they are made outputs */
487 writel(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1, 488 writel(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1,
488 &gpio6_base->setdataout); 489 &gpio6_base->setdataout);
489 writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | 490 writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
490 GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout); 491 GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
491 492
492 /* Configure GPIOs to output */ 493 /* Configure GPIOs to output */
493 writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe); 494 writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
494 writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | 495 writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
495 GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe); 496 GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);
496 497
497 omap_die_id_display(); 498 omap_die_id_display();
498 499
499 #ifdef CONFIG_VIDEO_OMAP3 500 #ifdef CONFIG_VIDEO_OMAP3
500 beagle_dvi_pup(); 501 beagle_dvi_pup();
501 beagle_display_init(); 502 beagle_display_init();
502 omap3_dss_enable(); 503 omap3_dss_enable();
503 #endif 504 #endif
504 505
505 #ifdef CONFIG_USB_MUSB_OMAP2PLUS 506 #ifdef CONFIG_USB_MUSB_OMAP2PLUS
506 musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE); 507 musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE);
507 #endif 508 #endif
508 509
509 if (generate_fake_mac) 510 if (generate_fake_mac)
510 omap_die_id_usbethaddr(); 511 omap_die_id_usbethaddr();
511 512
512 return 0; 513 return 0;
513 } 514 }
514 515
515 /* 516 /*
516 * Routine: set_muxconf_regs 517 * Routine: set_muxconf_regs
517 * Description: Setting up the configuration Mux registers specific to the 518 * Description: Setting up the configuration Mux registers specific to the
518 * hardware. Many pins need to be moved from protect to primary 519 * hardware. Many pins need to be moved from protect to primary
519 * mode. 520 * mode.
520 */ 521 */
521 void set_muxconf_regs(void) 522 void set_muxconf_regs(void)
522 { 523 {
523 MUX_BEAGLE(); 524 MUX_BEAGLE();
524 } 525 }
525 526
526 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 527 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
527 int board_mmc_init(bd_t *bis) 528 int board_mmc_init(bd_t *bis)
528 { 529 {
529 return omap_mmc_init(0, 0, 0, -1, -1); 530 return omap_mmc_init(0, 0, 0, -1, -1);
530 } 531 }
531 #endif 532 #endif
532 533
533 #if defined(CONFIG_GENERIC_MMC) 534 #if defined(CONFIG_GENERIC_MMC)
534 void board_mmc_power_init(void) 535 void board_mmc_power_init(void)
535 { 536 {
536 twl4030_power_mmc_init(0); 537 twl4030_power_mmc_init(0);
537 } 538 }
538 #endif 539 #endif
539 540
540 #if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD) 541 #if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
541 /* Call usb_stop() before starting the kernel */ 542 /* Call usb_stop() before starting the kernel */
542 void show_boot_progress(int val) 543 void show_boot_progress(int val)
543 { 544 {
544 if (val == BOOTSTAGE_ID_RUN_OS) 545 if (val == BOOTSTAGE_ID_RUN_OS)
545 usb_stop(); 546 usb_stop();
546 } 547 }
547 548
548 static struct omap_usbhs_board_data usbhs_bdata = { 549 static struct omap_usbhs_board_data usbhs_bdata = {
549 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, 550 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
550 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, 551 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
551 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED 552 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
552 }; 553 };
553 554
554 int ehci_hcd_init(int index, enum usb_init_type init, 555 int ehci_hcd_init(int index, enum usb_init_type init,
555 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 556 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
556 { 557 {
557 return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); 558 return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
558 } 559 }
559 560
560 int ehci_hcd_stop(int index) 561 int ehci_hcd_stop(int index)
561 { 562 {
562 return omap_ehci_hcd_stop(); 563 return omap_ehci_hcd_stop();
563 } 564 }
564 565
565 #endif /* CONFIG_USB_EHCI */ 566 #endif /* CONFIG_USB_EHCI */
566 567
567 #if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET) 568 #if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)
568 int board_eth_init(bd_t *bis) 569 int board_eth_init(bd_t *bis)
569 { 570 {
570 return usb_eth_initialize(bis); 571 return usb_eth_initialize(bis);
571 } 572 }
572 #endif 573 #endif
573 574
board/timll/devkit8000/devkit8000.c
Diff comments   View file @ 17fa032
1 /* 1 /*
2 * (C) Copyright 2004-2008 2 * (C) Copyright 2004-2008
3 * Texas Instruments, <www.ti.com> 3 * Texas Instruments, <www.ti.com>
4 * 4 *
5 * Author : 5 * Author :
6 * Sunil Kumar <sunilsaini05@gmail.com> 6 * Sunil Kumar <sunilsaini05@gmail.com>
7 * Shashi Ranjan <shashiranjanmca05@gmail.com> 7 * Shashi Ranjan <shashiranjanmca05@gmail.com>
8 * 8 *
9 * (C) Copyright 2009 9 * (C) Copyright 2009
10 * Frederik Kriewitz <frederik@kriewitz.eu> 10 * Frederik Kriewitz <frederik@kriewitz.eu>
11 * 11 *
12 * Derived from Beagle Board and 3430 SDP code by 12 * Derived from Beagle Board and 3430 SDP code by
13 * Richard Woodruff <r-woodruff2@ti.com> 13 * Richard Woodruff <r-woodruff2@ti.com>
14 * Syed Mohammed Khasim <khasim@ti.com> 14 * Syed Mohammed Khasim <khasim@ti.com>
15 * 15 *
16 * 16 *
17 * SPDX-License-Identifier: GPL-2.0+ 17 * SPDX-License-Identifier: GPL-2.0+
18 */ 18 */
19 #include <common.h> 19 #include <common.h>
20 #include <dm.h> 20 #include <dm.h>
21 #include <ns16550.h> 21 #include <ns16550.h>
22 #include <twl4030.h> 22 #include <twl4030.h>
23 #include <asm/io.h> 23 #include <asm/io.h>
24 #include <asm/arch/mmc_host_def.h> 24 #include <asm/arch/mmc_host_def.h>
25 #include <asm/arch/mux.h> 25 #include <asm/arch/mux.h>
26 #include <asm/arch/sys_proto.h> 26 #include <asm/arch/sys_proto.h>
27 #include <asm/arch/mem.h> 27 #include <asm/arch/mem.h>
28 #include <asm/mach-types.h> 28 #include <asm/mach-types.h>
29 #include "devkit8000.h" 29 #include "devkit8000.h"
30 #include <asm/gpio.h> 30 #include <asm/gpio.h>
31 #ifdef CONFIG_DRIVER_DM9000 31 #ifdef CONFIG_DRIVER_DM9000
32 #include <net.h> 32 #include <net.h>
33 #include <netdev.h> 33 #include <netdev.h>
34 #endif 34 #endif
35 35
36 DECLARE_GLOBAL_DATA_PTR; 36 DECLARE_GLOBAL_DATA_PTR;
37 37
38 static u32 gpmc_net_config[GPMC_MAX_REG] = { 38 static u32 gpmc_net_config[GPMC_MAX_REG] = {
39 NET_GPMC_CONFIG1, 39 NET_GPMC_CONFIG1,
40 NET_GPMC_CONFIG2, 40 NET_GPMC_CONFIG2,
41 NET_GPMC_CONFIG3, 41 NET_GPMC_CONFIG3,
42 NET_GPMC_CONFIG4, 42 NET_GPMC_CONFIG4,
43 NET_GPMC_CONFIG5, 43 NET_GPMC_CONFIG5,
44 NET_GPMC_CONFIG6, 44 NET_GPMC_CONFIG6,
45 0 45 0
46 }; 46 };
47 47
48 static const struct ns16550_platdata devkit8000_serial = { 48 static const struct ns16550_platdata devkit8000_serial = {
49 .base = OMAP34XX_UART3, 49 .base = OMAP34XX_UART3,
50 .reg_shift = 2, 50 .reg_shift = 2,
51 .clock = V_NS16550_CLK 51 .clock = V_NS16550_CLK,
52 .fcr = UART_FCR_DEFVAL,
52 }; 53 };
53 54
54 U_BOOT_DEVICE(devkit8000_uart) = { 55 U_BOOT_DEVICE(devkit8000_uart) = {
55 "ns16550_serial", 56 "ns16550_serial",
56 &devkit8000_serial 57 &devkit8000_serial
57 }; 58 };
58 59
59 /* 60 /*
60 * Routine: board_init 61 * Routine: board_init
61 * Description: Early hardware init. 62 * Description: Early hardware init.
62 */ 63 */
63 int board_init(void) 64 int board_init(void)
64 { 65 {
65 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 66 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
66 /* board id for Linux */ 67 /* board id for Linux */
67 gd->bd->bi_arch_number = MACH_TYPE_DEVKIT8000; 68 gd->bd->bi_arch_number = MACH_TYPE_DEVKIT8000;
68 /* boot param addr */ 69 /* boot param addr */
69 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 70 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
70 71
71 return 0; 72 return 0;
72 } 73 }
73 74
74 /* Configure GPMC registers for DM9000 */ 75 /* Configure GPMC registers for DM9000 */
75 static void gpmc_dm9000_config(void) 76 static void gpmc_dm9000_config(void)
76 { 77 {
77 enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6], 78 enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
78 CONFIG_DM9000_BASE, GPMC_SIZE_16M); 79 CONFIG_DM9000_BASE, GPMC_SIZE_16M);
79 } 80 }
80 81
81 /* 82 /*
82 * Routine: misc_init_r 83 * Routine: misc_init_r
83 * Description: Configure board specific parts 84 * Description: Configure board specific parts
84 */ 85 */
85 int misc_init_r(void) 86 int misc_init_r(void)
86 { 87 {
87 struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE; 88 struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
88 #ifdef CONFIG_DRIVER_DM9000 89 #ifdef CONFIG_DRIVER_DM9000
89 uchar enetaddr[6]; 90 uchar enetaddr[6];
90 u32 die_id_0; 91 u32 die_id_0;
91 #endif 92 #endif
92 93
93 twl4030_power_init(); 94 twl4030_power_init();
94 #ifdef CONFIG_TWL4030_LED 95 #ifdef CONFIG_TWL4030_LED
95 twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); 96 twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
96 #endif 97 #endif
97 98
98 #ifdef CONFIG_DRIVER_DM9000 99 #ifdef CONFIG_DRIVER_DM9000
99 /* Configure GPMC registers for DM9000 */ 100 /* Configure GPMC registers for DM9000 */
100 enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6], 101 enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
101 CONFIG_DM9000_BASE, GPMC_SIZE_16M); 102 CONFIG_DM9000_BASE, GPMC_SIZE_16M);
102 103
103 /* Use OMAP DIE_ID as MAC address */ 104 /* Use OMAP DIE_ID as MAC address */
104 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { 105 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
105 printf("ethaddr not set, using Die ID\n"); 106 printf("ethaddr not set, using Die ID\n");
106 die_id_0 = readl(&id_base->die_id_0); 107 die_id_0 = readl(&id_base->die_id_0);
107 enetaddr[0] = 0x02; /* locally administered */ 108 enetaddr[0] = 0x02; /* locally administered */
108 enetaddr[1] = readl(&id_base->die_id_1) & 0xff; 109 enetaddr[1] = readl(&id_base->die_id_1) & 0xff;
109 enetaddr[2] = (die_id_0 & 0xff000000) >> 24; 110 enetaddr[2] = (die_id_0 & 0xff000000) >> 24;
110 enetaddr[3] = (die_id_0 & 0x00ff0000) >> 16; 111 enetaddr[3] = (die_id_0 & 0x00ff0000) >> 16;
111 enetaddr[4] = (die_id_0 & 0x0000ff00) >> 8; 112 enetaddr[4] = (die_id_0 & 0x0000ff00) >> 8;
112 enetaddr[5] = (die_id_0 & 0x000000ff); 113 enetaddr[5] = (die_id_0 & 0x000000ff);
113 eth_setenv_enetaddr("ethaddr", enetaddr); 114 eth_setenv_enetaddr("ethaddr", enetaddr);
114 } 115 }
115 #endif 116 #endif
116 117
117 omap_die_id_display(); 118 omap_die_id_display();
118 119
119 return 0; 120 return 0;
120 } 121 }
121 122
122 /* 123 /*
123 * Routine: set_muxconf_regs 124 * Routine: set_muxconf_regs
124 * Description: Setting up the configuration Mux registers specific to the 125 * Description: Setting up the configuration Mux registers specific to the
125 * hardware. Many pins need to be moved from protect to primary 126 * hardware. Many pins need to be moved from protect to primary
126 * mode. 127 * mode.
127 */ 128 */
128 void set_muxconf_regs(void) 129 void set_muxconf_regs(void)
129 { 130 {
130 MUX_DEVKIT8000(); 131 MUX_DEVKIT8000();
131 } 132 }
132 133
133 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 134 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
134 int board_mmc_init(bd_t *bis) 135 int board_mmc_init(bd_t *bis)
135 { 136 {
136 return omap_mmc_init(0, 0, 0, -1, -1); 137 return omap_mmc_init(0, 0, 0, -1, -1);
137 } 138 }
138 #endif 139 #endif
139 140
140 #if defined(CONFIG_GENERIC_MMC) 141 #if defined(CONFIG_GENERIC_MMC)
141 void board_mmc_power_init(void) 142 void board_mmc_power_init(void)
142 { 143 {
143 twl4030_power_mmc_init(0); 144 twl4030_power_mmc_init(0);
144 } 145 }
145 #endif 146 #endif
146 147
147 #if defined(CONFIG_DRIVER_DM9000) & !defined(CONFIG_SPL_BUILD) 148 #if defined(CONFIG_DRIVER_DM9000) & !defined(CONFIG_SPL_BUILD)
148 /* 149 /*
149 * Routine: board_eth_init 150 * Routine: board_eth_init
150 * Description: Setting up the Ethernet hardware. 151 * Description: Setting up the Ethernet hardware.
151 */ 152 */
152 int board_eth_init(bd_t *bis) 153 int board_eth_init(bd_t *bis)
153 { 154 {
154 return dm9000_initialize(bis); 155 return dm9000_initialize(bis);
155 } 156 }
156 #endif 157 #endif
157 158
158 #ifdef CONFIG_SPL_OS_BOOT 159 #ifdef CONFIG_SPL_OS_BOOT
159 /* 160 /*
160 * Do board specific preparation before SPL 161 * Do board specific preparation before SPL
161 * Linux boot 162 * Linux boot
162 */ 163 */
163 void spl_board_prepare_for_linux(void) 164 void spl_board_prepare_for_linux(void)
164 { 165 {
165 gpmc_dm9000_config(); 166 gpmc_dm9000_config();
166 } 167 }
167 168
168 /* 169 /*
169 * devkit8000 specific implementation of spl_start_uboot() 170 * devkit8000 specific implementation of spl_start_uboot()
170 * 171 *
171 * RETURN 172 * RETURN
172 * 0 if the button is not pressed 173 * 0 if the button is not pressed
173 * 1 if the button is pressed 174 * 1 if the button is pressed
174 */ 175 */
175 int spl_start_uboot(void) 176 int spl_start_uboot(void)
176 { 177 {
177 int val = 0; 178 int val = 0;
178 if (!gpio_request(SPL_OS_BOOT_KEY, "U-Boot key")) { 179 if (!gpio_request(SPL_OS_BOOT_KEY, "U-Boot key")) {
179 gpio_direction_input(SPL_OS_BOOT_KEY); 180 gpio_direction_input(SPL_OS_BOOT_KEY);
180 val = gpio_get_value(SPL_OS_BOOT_KEY); 181 val = gpio_get_value(SPL_OS_BOOT_KEY);
181 gpio_free(SPL_OS_BOOT_KEY); 182 gpio_free(SPL_OS_BOOT_KEY);
182 } 183 }
183 return !val; 184 return !val;
184 } 185 }
185 #endif 186 #endif
186 187
187 /* 188 /*
188 * Routine: get_board_mem_timings 189 * Routine: get_board_mem_timings
189 * Description: If we use SPL then there is no x-loader nor config header 190 * Description: If we use SPL then there is no x-loader nor config header
190 * so we have to setup the DDR timings ourself on the first bank. This 191 * so we have to setup the DDR timings ourself on the first bank. This
191 * provides the timing values back to the function that configures 192 * provides the timing values back to the function that configures
192 * the memory. We have either one or two banks of 128MB DDR. 193 * the memory. We have either one or two banks of 128MB DDR.
193 */ 194 */
194 void get_board_mem_timings(struct board_sdrc_timings *timings) 195 void get_board_mem_timings(struct board_sdrc_timings *timings)
195 { 196 {
196 /* General SDRC config */ 197 /* General SDRC config */
197 timings->mcfg = MICRON_V_MCFG_165(128 << 20); 198 timings->mcfg = MICRON_V_MCFG_165(128 << 20);
198 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 199 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
199 200
200 /* AC timings */ 201 /* AC timings */
201 timings->ctrla = MICRON_V_ACTIMA_165; 202 timings->ctrla = MICRON_V_ACTIMA_165;
202 timings->ctrlb = MICRON_V_ACTIMB_165; 203 timings->ctrlb = MICRON_V_ACTIMB_165;
203 204
204 timings->mr = MICRON_V_MR_165; 205 timings->mr = MICRON_V_MR_165;
205 } 206 }
206 207
drivers/serial/ns16550.c
Diff comments   View file @ 17fa032
1 /* 1 /*
2 * COM1 NS16550 support 2 * COM1 NS16550 support
3 * originally from linux source (arch/powerpc/boot/ns16550.c) 3 * originally from linux source (arch/powerpc/boot/ns16550.c)
4 * modified to use CONFIG_SYS_ISA_MEM and new defines 4 * modified to use CONFIG_SYS_ISA_MEM and new defines
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <clk.h> 8 #include <clk.h>
9 #include <dm.h> 9 #include <dm.h>
10 #include <errno.h> 10 #include <errno.h>
11 #include <fdtdec.h> 11 #include <fdtdec.h>
12 #include <ns16550.h> 12 #include <ns16550.h>
13 #include <serial.h> 13 #include <serial.h>
14 #include <watchdog.h> 14 #include <watchdog.h>
15 #include <linux/types.h> 15 #include <linux/types.h>
16 #include <asm/io.h> 16 #include <asm/io.h>
17 17
18 DECLARE_GLOBAL_DATA_PTR; 18 DECLARE_GLOBAL_DATA_PTR;
19 19
20 #define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */ 20 #define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */
21 #define UART_MCRVAL (UART_MCR_DTR | \ 21 #define UART_MCRVAL (UART_MCR_DTR | \
22 UART_MCR_RTS) /* RTS/DTR */ 22 UART_MCR_RTS) /* RTS/DTR */
23 #define UART_FCRVAL (UART_FCR_FIFO_EN | \
24 UART_FCR_RXSR | \
25 UART_FCR_TXSR) /* Clear & enable FIFOs */
26 23
27 #ifndef CONFIG_DM_SERIAL 24 #ifndef CONFIG_DM_SERIAL
28 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED 25 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
29 #define serial_out(x, y) outb(x, (ulong)y) 26 #define serial_out(x, y) outb(x, (ulong)y)
30 #define serial_in(y) inb((ulong)y) 27 #define serial_in(y) inb((ulong)y)
31 #elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE > 0) 28 #elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE > 0)
32 #define serial_out(x, y) out_be32(y, x) 29 #define serial_out(x, y) out_be32(y, x)
33 #define serial_in(y) in_be32(y) 30 #define serial_in(y) in_be32(y)
34 #elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE < 0) 31 #elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE < 0)
35 #define serial_out(x, y) out_le32(y, x) 32 #define serial_out(x, y) out_le32(y, x)
36 #define serial_in(y) in_le32(y) 33 #define serial_in(y) in_le32(y)
37 #else 34 #else
38 #define serial_out(x, y) writeb(x, y) 35 #define serial_out(x, y) writeb(x, y)
39 #define serial_in(y) readb(y) 36 #define serial_in(y) readb(y)
40 #endif 37 #endif
41 #endif /* !CONFIG_DM_SERIAL */ 38 #endif /* !CONFIG_DM_SERIAL */
42 39
43 #if defined(CONFIG_SOC_KEYSTONE) 40 #if defined(CONFIG_SOC_KEYSTONE)
44 #define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0 41 #define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0
45 #define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0)) 42 #define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0))
46 #undef UART_MCRVAL 43 #undef UART_MCRVAL
47 #ifdef CONFIG_SERIAL_HW_FLOW_CONTROL 44 #ifdef CONFIG_SERIAL_HW_FLOW_CONTROL
48 #define UART_MCRVAL (UART_MCR_RTS | UART_MCR_AFE) 45 #define UART_MCRVAL (UART_MCR_RTS | UART_MCR_AFE)
49 #else 46 #else
50 #define UART_MCRVAL (UART_MCR_RTS) 47 #define UART_MCRVAL (UART_MCR_RTS)
51 #endif 48 #endif
52 #endif 49 #endif
53 50
54 #ifndef CONFIG_SYS_NS16550_IER 51 #ifndef CONFIG_SYS_NS16550_IER
55 #define CONFIG_SYS_NS16550_IER 0x00 52 #define CONFIG_SYS_NS16550_IER 0x00
56 #endif /* CONFIG_SYS_NS16550_IER */ 53 #endif /* CONFIG_SYS_NS16550_IER */
57 54
58 static inline void serial_out_shift(void *addr, int shift, int value) 55 static inline void serial_out_shift(void *addr, int shift, int value)
59 { 56 {
60 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED 57 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
61 outb(value, (ulong)addr); 58 outb(value, (ulong)addr);
62 #elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_SYS_BIG_ENDIAN) 59 #elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_SYS_BIG_ENDIAN)
63 out_le32(addr, value); 60 out_le32(addr, value);
64 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN) 61 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
65 out_be32(addr, value); 62 out_be32(addr, value);
66 #elif defined(CONFIG_SYS_NS16550_MEM32) 63 #elif defined(CONFIG_SYS_NS16550_MEM32)
67 writel(value, addr); 64 writel(value, addr);
68 #elif defined(CONFIG_SYS_BIG_ENDIAN) 65 #elif defined(CONFIG_SYS_BIG_ENDIAN)
69 writeb(value, addr + (1 << shift) - 1); 66 writeb(value, addr + (1 << shift) - 1);
70 #else 67 #else
71 writeb(value, addr); 68 writeb(value, addr);
72 #endif 69 #endif
73 } 70 }
74 71
75 static inline int serial_in_shift(void *addr, int shift) 72 static inline int serial_in_shift(void *addr, int shift)
76 { 73 {
77 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED 74 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
78 return inb((ulong)addr); 75 return inb((ulong)addr);
79 #elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_SYS_BIG_ENDIAN) 76 #elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_SYS_BIG_ENDIAN)
80 return in_le32(addr); 77 return in_le32(addr);
81 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN) 78 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
82 return in_be32(addr); 79 return in_be32(addr);
83 #elif defined(CONFIG_SYS_NS16550_MEM32) 80 #elif defined(CONFIG_SYS_NS16550_MEM32)
84 return readl(addr); 81 return readl(addr);
85 #elif defined(CONFIG_SYS_BIG_ENDIAN) 82 #elif defined(CONFIG_SYS_BIG_ENDIAN)
86 return readb(addr + (1 << shift) - 1); 83 return readb(addr + (1 << shift) - 1);
87 #else 84 #else
88 return readb(addr); 85 return readb(addr);
89 #endif 86 #endif
90 } 87 }
91 88
92 #ifdef CONFIG_DM_SERIAL 89 #ifdef CONFIG_DM_SERIAL
93 90
94 #ifndef CONFIG_SYS_NS16550_CLK 91 #ifndef CONFIG_SYS_NS16550_CLK
95 #define CONFIG_SYS_NS16550_CLK 0 92 #define CONFIG_SYS_NS16550_CLK 0
96 #endif 93 #endif
97 94
98 static void ns16550_writeb(NS16550_t port, int offset, int value) 95 static void ns16550_writeb(NS16550_t port, int offset, int value)
99 { 96 {
100 struct ns16550_platdata *plat = port->plat; 97 struct ns16550_platdata *plat = port->plat;
101 unsigned char *addr; 98 unsigned char *addr;
102 99
103 offset *= 1 << plat->reg_shift; 100 offset *= 1 << plat->reg_shift;
104 addr = (unsigned char *)plat->base + offset; 101 addr = (unsigned char *)plat->base + offset;
105 102
106 /* 103 /*
107 * As far as we know it doesn't make sense to support selection of 104 * As far as we know it doesn't make sense to support selection of
108 * these options at run-time, so use the existing CONFIG options. 105 * these options at run-time, so use the existing CONFIG options.
109 */ 106 */
110 serial_out_shift(addr + plat->reg_offset, plat->reg_shift, value); 107 serial_out_shift(addr + plat->reg_offset, plat->reg_shift, value);
111 } 108 }
112 109
113 static int ns16550_readb(NS16550_t port, int offset) 110 static int ns16550_readb(NS16550_t port, int offset)
114 { 111 {
115 struct ns16550_platdata *plat = port->plat; 112 struct ns16550_platdata *plat = port->plat;
116 unsigned char *addr; 113 unsigned char *addr;
117 114
118 offset *= 1 << plat->reg_shift; 115 offset *= 1 << plat->reg_shift;
119 addr = (unsigned char *)plat->base + offset; 116 addr = (unsigned char *)plat->base + offset;
120 117
121 return serial_in_shift(addr + plat->reg_offset, plat->reg_shift); 118 return serial_in_shift(addr + plat->reg_offset, plat->reg_shift);
122 } 119 }
123 120
124 static u32 ns16550_getfcr(NS16550_t port) 121 static u32 ns16550_getfcr(NS16550_t port)
125 { 122 {
126 struct ns16550_platdata *plat = port->plat; 123 struct ns16550_platdata *plat = port->plat;
127 124
128 return plat->fcr; 125 return plat->fcr;
129 } 126 }
130 127
131 /* We can clean these up once everything is moved to driver model */ 128 /* We can clean these up once everything is moved to driver model */
132 #define serial_out(value, addr) \ 129 #define serial_out(value, addr) \
133 ns16550_writeb(com_port, \ 130 ns16550_writeb(com_port, \
134 (unsigned char *)addr - (unsigned char *)com_port, value) 131 (unsigned char *)addr - (unsigned char *)com_port, value)
135 #define serial_in(addr) \ 132 #define serial_in(addr) \
136 ns16550_readb(com_port, \ 133 ns16550_readb(com_port, \
137 (unsigned char *)addr - (unsigned char *)com_port) 134 (unsigned char *)addr - (unsigned char *)com_port)
138 #else 135 #else
139 static u32 ns16550_getfcr(NS16550_t port) 136 static u32 ns16550_getfcr(NS16550_t port)
140 { 137 {
141 return UART_FCRVAL; 138 return UART_FCR_DEFVAL;
142 } 139 }
143 #endif 140 #endif
144 141
145 int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate) 142 int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate)
146 { 143 {
147 const unsigned int mode_x_div = 16; 144 const unsigned int mode_x_div = 16;
148 145
149 return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate); 146 return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate);
150 } 147 }
151 148
152 static void NS16550_setbrg(NS16550_t com_port, int baud_divisor) 149 static void NS16550_setbrg(NS16550_t com_port, int baud_divisor)
153 { 150 {
154 serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr); 151 serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr);
155 serial_out(baud_divisor & 0xff, &com_port->dll); 152 serial_out(baud_divisor & 0xff, &com_port->dll);
156 serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm); 153 serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
157 serial_out(UART_LCRVAL, &com_port->lcr); 154 serial_out(UART_LCRVAL, &com_port->lcr);
158 } 155 }
159 156
160 void NS16550_init(NS16550_t com_port, int baud_divisor) 157 void NS16550_init(NS16550_t com_port, int baud_divisor)
161 { 158 {
162 #if (defined(CONFIG_SPL_BUILD) && \ 159 #if (defined(CONFIG_SPL_BUILD) && \
163 (defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX))) 160 (defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX)))
164 /* 161 /*
165 * On some OMAP3/OMAP4 devices when UART3 is configured for boot mode 162 * On some OMAP3/OMAP4 devices when UART3 is configured for boot mode
166 * before SPL starts only THRE bit is set. We have to empty the 163 * before SPL starts only THRE bit is set. We have to empty the
167 * transmitter before initialization starts. 164 * transmitter before initialization starts.
168 */ 165 */
169 if ((serial_in(&com_port->lsr) & (UART_LSR_TEMT | UART_LSR_THRE)) 166 if ((serial_in(&com_port->lsr) & (UART_LSR_TEMT | UART_LSR_THRE))
170 == UART_LSR_THRE) { 167 == UART_LSR_THRE) {
171 if (baud_divisor != -1) 168 if (baud_divisor != -1)
172 NS16550_setbrg(com_port, baud_divisor); 169 NS16550_setbrg(com_port, baud_divisor);
173 serial_out(0, &com_port->mdr1); 170 serial_out(0, &com_port->mdr1);
174 } 171 }
175 #endif 172 #endif
176 173
177 while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT)) 174 while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT))
178 ; 175 ;
179 176
180 serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); 177 serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
181 #if defined(CONFIG_OMAP) || defined(CONFIG_AM33XX) || \ 178 #if defined(CONFIG_OMAP) || defined(CONFIG_AM33XX) || \
182 defined(CONFIG_TI81XX) || defined(CONFIG_AM43XX) 179 defined(CONFIG_TI81XX) || defined(CONFIG_AM43XX)
183 serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/ 180 serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/
184 #endif 181 #endif
185 serial_out(UART_MCRVAL, &com_port->mcr); 182 serial_out(UART_MCRVAL, &com_port->mcr);
186 serial_out(ns16550_getfcr(com_port), &com_port->fcr); 183 serial_out(ns16550_getfcr(com_port), &com_port->fcr);
187 if (baud_divisor != -1) 184 if (baud_divisor != -1)
188 NS16550_setbrg(com_port, baud_divisor); 185 NS16550_setbrg(com_port, baud_divisor);
189 #if defined(CONFIG_OMAP) || \ 186 #if defined(CONFIG_OMAP) || \
190 defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX) || \ 187 defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX) || \
191 defined(CONFIG_TI81XX) || defined(CONFIG_AM43XX) 188 defined(CONFIG_TI81XX) || defined(CONFIG_AM43XX)
192 189
193 /* /16 is proper to hit 115200 with 48MHz */ 190 /* /16 is proper to hit 115200 with 48MHz */
194 serial_out(0, &com_port->mdr1); 191 serial_out(0, &com_port->mdr1);
195 #endif /* CONFIG_OMAP */ 192 #endif /* CONFIG_OMAP */
196 #if defined(CONFIG_SOC_KEYSTONE) 193 #if defined(CONFIG_SOC_KEYSTONE)
197 serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->regC); 194 serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->regC);
198 #endif 195 #endif
199 } 196 }
200 197
201 #ifndef CONFIG_NS16550_MIN_FUNCTIONS 198 #ifndef CONFIG_NS16550_MIN_FUNCTIONS
202 void NS16550_reinit(NS16550_t com_port, int baud_divisor) 199 void NS16550_reinit(NS16550_t com_port, int baud_divisor)
203 { 200 {
204 serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); 201 serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
205 NS16550_setbrg(com_port, 0); 202 NS16550_setbrg(com_port, 0);
206 serial_out(UART_MCRVAL, &com_port->mcr); 203 serial_out(UART_MCRVAL, &com_port->mcr);
207 serial_out(ns16550_getfcr(com_port), &com_port->fcr); 204 serial_out(ns16550_getfcr(com_port), &com_port->fcr);
208 NS16550_setbrg(com_port, baud_divisor); 205 NS16550_setbrg(com_port, baud_divisor);
209 } 206 }
210 #endif /* CONFIG_NS16550_MIN_FUNCTIONS */ 207 #endif /* CONFIG_NS16550_MIN_FUNCTIONS */
211 208
212 void NS16550_putc(NS16550_t com_port, char c) 209 void NS16550_putc(NS16550_t com_port, char c)
213 { 210 {
214 while ((serial_in(&com_port->lsr) & UART_LSR_THRE) == 0) 211 while ((serial_in(&com_port->lsr) & UART_LSR_THRE) == 0)
215 ; 212 ;
216 serial_out(c, &com_port->thr); 213 serial_out(c, &com_port->thr);
217 214
218 /* 215 /*
219 * Call watchdog_reset() upon newline. This is done here in putc 216 * Call watchdog_reset() upon newline. This is done here in putc
220 * since the environment code uses a single puts() to print the complete 217 * since the environment code uses a single puts() to print the complete
221 * environment upon "printenv". So we can't put this watchdog call 218 * environment upon "printenv". So we can't put this watchdog call
222 * in puts(). 219 * in puts().
223 */ 220 */
224 if (c == '\n') 221 if (c == '\n')
225 WATCHDOG_RESET(); 222 WATCHDOG_RESET();
226 } 223 }
227 224
228 #ifndef CONFIG_NS16550_MIN_FUNCTIONS 225 #ifndef CONFIG_NS16550_MIN_FUNCTIONS
229 char NS16550_getc(NS16550_t com_port) 226 char NS16550_getc(NS16550_t com_port)
230 { 227 {
231 while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0) { 228 while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0) {
232 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_TTY) 229 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_TTY)
233 extern void usbtty_poll(void); 230 extern void usbtty_poll(void);
234 usbtty_poll(); 231 usbtty_poll();
235 #endif 232 #endif
236 WATCHDOG_RESET(); 233 WATCHDOG_RESET();
237 } 234 }
238 return serial_in(&com_port->rbr); 235 return serial_in(&com_port->rbr);
239 } 236 }
240 237
241 int NS16550_tstc(NS16550_t com_port) 238 int NS16550_tstc(NS16550_t com_port)
242 { 239 {
243 return (serial_in(&com_port->lsr) & UART_LSR_DR) != 0; 240 return (serial_in(&com_port->lsr) & UART_LSR_DR) != 0;
244 } 241 }
245 242
246 #endif /* CONFIG_NS16550_MIN_FUNCTIONS */ 243 #endif /* CONFIG_NS16550_MIN_FUNCTIONS */
247 244
248 #ifdef CONFIG_DEBUG_UART_NS16550 245 #ifdef CONFIG_DEBUG_UART_NS16550
249 246
250 #include <debug_uart.h> 247 #include <debug_uart.h>
251 248
252 #define serial_dout(reg, value) \ 249 #define serial_dout(reg, value) \
253 serial_out_shift((char *)com_port + \ 250 serial_out_shift((char *)com_port + \
254 ((char *)reg - (char *)com_port) * \ 251 ((char *)reg - (char *)com_port) * \
255 (1 << CONFIG_DEBUG_UART_SHIFT), \ 252 (1 << CONFIG_DEBUG_UART_SHIFT), \
256 CONFIG_DEBUG_UART_SHIFT, value) 253 CONFIG_DEBUG_UART_SHIFT, value)
257 #define serial_din(reg) \ 254 #define serial_din(reg) \
258 serial_in_shift((char *)com_port + \ 255 serial_in_shift((char *)com_port + \
259 ((char *)reg - (char *)com_port) * \ 256 ((char *)reg - (char *)com_port) * \
260 (1 << CONFIG_DEBUG_UART_SHIFT), \ 257 (1 << CONFIG_DEBUG_UART_SHIFT), \
261 CONFIG_DEBUG_UART_SHIFT) 258 CONFIG_DEBUG_UART_SHIFT)
262 259
263 static inline void _debug_uart_init(void) 260 static inline void _debug_uart_init(void)
264 { 261 {
265 struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE; 262 struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE;
266 int baud_divisor; 263 int baud_divisor;
267 264
268 /* 265 /*
269 * We copy the code from above because it is already horribly messy. 266 * We copy the code from above because it is already horribly messy.
270 * Trying to refactor to nicely remove the duplication doesn't seem 267 * Trying to refactor to nicely remove the duplication doesn't seem
271 * feasible. The better fix is to move all users of this driver to 268 * feasible. The better fix is to move all users of this driver to
272 * driver model. 269 * driver model.
273 */ 270 */
274 baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK, 271 baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK,
275 CONFIG_BAUDRATE); 272 CONFIG_BAUDRATE);
276 serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER); 273 serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER);
277 serial_dout(&com_port->mcr, UART_MCRVAL); 274 serial_dout(&com_port->mcr, UART_MCRVAL);
278 serial_dout(&com_port->fcr, UART_FCRVAL); 275 serial_dout(&com_port->fcr, UART_FCR_DEFVAL);
279 276
280 serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL); 277 serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL);
281 serial_dout(&com_port->dll, baud_divisor & 0xff); 278 serial_dout(&com_port->dll, baud_divisor & 0xff);
282 serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff); 279 serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff);
283 serial_dout(&com_port->lcr, UART_LCRVAL); 280 serial_dout(&com_port->lcr, UART_LCRVAL);
284 } 281 }
285 282
286 static inline void _debug_uart_putc(int ch) 283 static inline void _debug_uart_putc(int ch)
287 { 284 {
288 struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE; 285 struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE;
289 286
290 while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) 287 while (!(serial_din(&com_port->lsr) & UART_LSR_THRE))
291 ; 288 ;
292 serial_dout(&com_port->thr, ch); 289 serial_dout(&com_port->thr, ch);
293 } 290 }
294 291
295 DEBUG_UART_FUNCS 292 DEBUG_UART_FUNCS
296 293
297 #endif 294 #endif
298 295
299 #ifdef CONFIG_DM_SERIAL 296 #ifdef CONFIG_DM_SERIAL
300 static int ns16550_serial_putc(struct udevice *dev, const char ch) 297 static int ns16550_serial_putc(struct udevice *dev, const char ch)
301 { 298 {
302 struct NS16550 *const com_port = dev_get_priv(dev); 299 struct NS16550 *const com_port = dev_get_priv(dev);
303 300
304 if (!(serial_in(&com_port->lsr) & UART_LSR_THRE)) 301 if (!(serial_in(&com_port->lsr) & UART_LSR_THRE))
305 return -EAGAIN; 302 return -EAGAIN;
306 serial_out(ch, &com_port->thr); 303 serial_out(ch, &com_port->thr);
307 304
308 /* 305 /*
309 * Call watchdog_reset() upon newline. This is done here in putc 306 * Call watchdog_reset() upon newline. This is done here in putc
310 * since the environment code uses a single puts() to print the complete 307 * since the environment code uses a single puts() to print the complete
311 * environment upon "printenv". So we can't put this watchdog call 308 * environment upon "printenv". So we can't put this watchdog call
312 * in puts(). 309 * in puts().
313 */ 310 */
314 if (ch == '\n') 311 if (ch == '\n')
315 WATCHDOG_RESET(); 312 WATCHDOG_RESET();
316 313
317 return 0; 314 return 0;
318 } 315 }
319 316
320 static int ns16550_serial_pending(struct udevice *dev, bool input) 317 static int ns16550_serial_pending(struct udevice *dev, bool input)
321 { 318 {
322 struct NS16550 *const com_port = dev_get_priv(dev); 319 struct NS16550 *const com_port = dev_get_priv(dev);
323 320
324 if (input) 321 if (input)
325 return serial_in(&com_port->lsr) & UART_LSR_DR ? 1 : 0; 322 return serial_in(&com_port->lsr) & UART_LSR_DR ? 1 : 0;
326 else 323 else
327 return serial_in(&com_port->lsr) & UART_LSR_THRE ? 0 : 1; 324 return serial_in(&com_port->lsr) & UART_LSR_THRE ? 0 : 1;
328 } 325 }
329 326
330 static int ns16550_serial_getc(struct udevice *dev) 327 static int ns16550_serial_getc(struct udevice *dev)
331 { 328 {
332 struct NS16550 *const com_port = dev_get_priv(dev); 329 struct NS16550 *const com_port = dev_get_priv(dev);
333 330
334 if (!(serial_in(&com_port->lsr) & UART_LSR_DR)) 331 if (!(serial_in(&com_port->lsr) & UART_LSR_DR))
335 return -EAGAIN; 332 return -EAGAIN;
336 333
337 return serial_in(&com_port->rbr); 334 return serial_in(&com_port->rbr);
338 } 335 }
339 336
340 static int ns16550_serial_setbrg(struct udevice *dev, int baudrate) 337 static int ns16550_serial_setbrg(struct udevice *dev, int baudrate)
341 { 338 {
342 struct NS16550 *const com_port = dev_get_priv(dev); 339 struct NS16550 *const com_port = dev_get_priv(dev);
343 struct ns16550_platdata *plat = com_port->plat; 340 struct ns16550_platdata *plat = com_port->plat;
344 int clock_divisor; 341 int clock_divisor;
345 342
346 clock_divisor = ns16550_calc_divisor(com_port, plat->clock, baudrate); 343 clock_divisor = ns16550_calc_divisor(com_port, plat->clock, baudrate);
347 344
348 NS16550_setbrg(com_port, clock_divisor); 345 NS16550_setbrg(com_port, clock_divisor);
349 346
350 return 0; 347 return 0;
351 } 348 }
352 349
353 int ns16550_serial_probe(struct udevice *dev) 350 int ns16550_serial_probe(struct udevice *dev)
354 { 351 {
355 struct NS16550 *const com_port = dev_get_priv(dev); 352 struct NS16550 *const com_port = dev_get_priv(dev);
356 353
357 com_port->plat = dev_get_platdata(dev); 354 com_port->plat = dev_get_platdata(dev);
358 NS16550_init(com_port, -1); 355 NS16550_init(com_port, -1);
359 356
360 return 0; 357 return 0;
361 } 358 }
362 359
363 #if CONFIG_IS_ENABLED(OF_CONTROL) 360 #if CONFIG_IS_ENABLED(OF_CONTROL)
364 enum { 361 enum {
365 PORT_NS16550 = 0, 362 PORT_NS16550 = 0,
366 PORT_JZ4780, 363 PORT_JZ4780,
367 }; 364 };
368 #endif 365 #endif
369 366
370 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 367 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
371 int ns16550_serial_ofdata_to_platdata(struct udevice *dev) 368 int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
372 { 369 {
373 struct ns16550_platdata *plat = dev->platdata; 370 struct ns16550_platdata *plat = dev->platdata;
374 const u32 port_type = dev_get_driver_data(dev); 371 const u32 port_type = dev_get_driver_data(dev);
375 fdt_addr_t addr; 372 fdt_addr_t addr;
376 struct clk clk; 373 struct clk clk;
377 int err; 374 int err;
378 375
379 /* try Processor Local Bus device first */ 376 /* try Processor Local Bus device first */
380 addr = dev_get_addr(dev); 377 addr = dev_get_addr(dev);
381 #if defined(CONFIG_PCI) && defined(CONFIG_DM_PCI) 378 #if defined(CONFIG_PCI) && defined(CONFIG_DM_PCI)
382 if (addr == FDT_ADDR_T_NONE) { 379 if (addr == FDT_ADDR_T_NONE) {
383 /* then try pci device */ 380 /* then try pci device */
384 struct fdt_pci_addr pci_addr; 381 struct fdt_pci_addr pci_addr;
385 u32 bar; 382 u32 bar;
386 int ret; 383 int ret;
387 384
388 /* we prefer to use a memory-mapped register */ 385 /* we prefer to use a memory-mapped register */
389 ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset, 386 ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset,
390 FDT_PCI_SPACE_MEM32, "reg", 387 FDT_PCI_SPACE_MEM32, "reg",
391 &pci_addr); 388 &pci_addr);
392 if (ret) { 389 if (ret) {
393 /* try if there is any i/o-mapped register */ 390 /* try if there is any i/o-mapped register */
394 ret = fdtdec_get_pci_addr(gd->fdt_blob, 391 ret = fdtdec_get_pci_addr(gd->fdt_blob,
395 dev->of_offset, 392 dev->of_offset,
396 FDT_PCI_SPACE_IO, 393 FDT_PCI_SPACE_IO,
397 "reg", &pci_addr); 394 "reg", &pci_addr);
398 if (ret) 395 if (ret)
399 return ret; 396 return ret;
400 } 397 }
401 398
402 ret = fdtdec_get_pci_bar32(dev, &pci_addr, &bar); 399 ret = fdtdec_get_pci_bar32(dev, &pci_addr, &bar);
403 if (ret) 400 if (ret)
404 return ret; 401 return ret;
405 402
406 addr = bar; 403 addr = bar;
407 } 404 }
408 #endif 405 #endif
409 406
410 if (addr == FDT_ADDR_T_NONE) 407 if (addr == FDT_ADDR_T_NONE)
411 return -EINVAL; 408 return -EINVAL;
412 409
413 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED 410 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
414 plat->base = addr; 411 plat->base = addr;
415 #else 412 #else
416 plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE); 413 plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE);
417 #endif 414 #endif
418 415
419 plat->reg_offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, 416 plat->reg_offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
420 "reg-offset", 0); 417 "reg-offset", 0);
421 plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset, 418 plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
422 "reg-shift", 0); 419 "reg-shift", 0);
423 420
424 err = clk_get_by_index(dev, 0, &clk); 421 err = clk_get_by_index(dev, 0, &clk);
425 if (!err) { 422 if (!err) {
426 err = clk_get_rate(&clk); 423 err = clk_get_rate(&clk);
427 if (!IS_ERR_VALUE(err)) 424 if (!IS_ERR_VALUE(err))
428 plat->clock = err; 425 plat->clock = err;
429 } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) { 426 } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
430 debug("ns16550 failed to get clock\n"); 427 debug("ns16550 failed to get clock\n");
431 return err; 428 return err;
432 } 429 }
433 430
434 if (!plat->clock) 431 if (!plat->clock)
435 plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset, 432 plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
436 "clock-frequency", 433 "clock-frequency",
437 CONFIG_SYS_NS16550_CLK); 434 CONFIG_SYS_NS16550_CLK);
438 if (!plat->clock) { 435 if (!plat->clock) {
439 debug("ns16550 clock not defined\n"); 436 debug("ns16550 clock not defined\n");
440 return -EINVAL; 437 return -EINVAL;
441 } 438 }
442 439
443 plat->fcr = UART_FCRVAL; 440 plat->fcr = UART_FCR_DEFVAL;
444 if (port_type == PORT_JZ4780) 441 if (port_type == PORT_JZ4780)
445 plat->fcr |= UART_FCR_UME; 442 plat->fcr |= UART_FCR_UME;
446 443
447 return 0; 444 return 0;
448 } 445 }
449 #endif 446 #endif
450 447
451 const struct dm_serial_ops ns16550_serial_ops = { 448 const struct dm_serial_ops ns16550_serial_ops = {
452 .putc = ns16550_serial_putc, 449 .putc = ns16550_serial_putc,
453 .pending = ns16550_serial_pending, 450 .pending = ns16550_serial_pending,
454 .getc = ns16550_serial_getc, 451 .getc = ns16550_serial_getc,
455 .setbrg = ns16550_serial_setbrg, 452 .setbrg = ns16550_serial_setbrg,
456 }; 453 };
457 454
458 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 455 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
459 #if CONFIG_IS_ENABLED(OF_CONTROL) 456 #if CONFIG_IS_ENABLED(OF_CONTROL)
460 /* 457 /*
461 * Please consider existing compatible strings before adding a new 458 * Please consider existing compatible strings before adding a new
462 * one to keep this table compact. Or you may add a generic "ns16550" 459 * one to keep this table compact. Or you may add a generic "ns16550"
463 * compatible string to your dts. 460 * compatible string to your dts.
464 */ 461 */
465 static const struct udevice_id ns16550_serial_ids[] = { 462 static const struct udevice_id ns16550_serial_ids[] = {
466 { .compatible = "ns16550", .data = PORT_NS16550 }, 463 { .compatible = "ns16550", .data = PORT_NS16550 },
467 { .compatible = "ns16550a", .data = PORT_NS16550 }, 464 { .compatible = "ns16550a", .data = PORT_NS16550 },
468 { .compatible = "ingenic,jz4780-uart", .data = PORT_JZ4780 }, 465 { .compatible = "ingenic,jz4780-uart", .data = PORT_JZ4780 },
469 { .compatible = "nvidia,tegra20-uart", .data = PORT_NS16550 }, 466 { .compatible = "nvidia,tegra20-uart", .data = PORT_NS16550 },
470 { .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 }, 467 { .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 },
471 { .compatible = "ti,omap2-uart", .data = PORT_NS16550 }, 468 { .compatible = "ti,omap2-uart", .data = PORT_NS16550 },
472 { .compatible = "ti,omap3-uart", .data = PORT_NS16550 }, 469 { .compatible = "ti,omap3-uart", .data = PORT_NS16550 },
473 { .compatible = "ti,omap4-uart", .data = PORT_NS16550 }, 470 { .compatible = "ti,omap4-uart", .data = PORT_NS16550 },
474 { .compatible = "ti,am3352-uart", .data = PORT_NS16550 }, 471 { .compatible = "ti,am3352-uart", .data = PORT_NS16550 },
475 { .compatible = "ti,am4372-uart", .data = PORT_NS16550 }, 472 { .compatible = "ti,am4372-uart", .data = PORT_NS16550 },
476 { .compatible = "ti,dra742-uart", .data = PORT_NS16550 }, 473 { .compatible = "ti,dra742-uart", .data = PORT_NS16550 },
477 {} 474 {}
478 }; 475 };
479 #endif 476 #endif
480 477
481 #if CONFIG_IS_ENABLED(SERIAL_PRESENT) 478 #if CONFIG_IS_ENABLED(SERIAL_PRESENT)
482 U_BOOT_DRIVER(ns16550_serial) = { 479 U_BOOT_DRIVER(ns16550_serial) = {
483 .name = "ns16550_serial", 480 .name = "ns16550_serial",
484 .id = UCLASS_SERIAL, 481 .id = UCLASS_SERIAL,
485 #if CONFIG_IS_ENABLED(OF_CONTROL) 482 #if CONFIG_IS_ENABLED(OF_CONTROL)
486 .of_match = ns16550_serial_ids, 483 .of_match = ns16550_serial_ids,
487 .ofdata_to_platdata = ns16550_serial_ofdata_to_platdata, 484 .ofdata_to_platdata = ns16550_serial_ofdata_to_platdata,
488 .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), 485 .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
489 #endif 486 #endif
490 .priv_auto_alloc_size = sizeof(struct NS16550), 487 .priv_auto_alloc_size = sizeof(struct NS16550),
491 .probe = ns16550_serial_probe, 488 .probe = ns16550_serial_probe,
492 .ops = &ns16550_serial_ops, 489 .ops = &ns16550_serial_ops,
493 .flags = DM_FLAG_PRE_RELOC, 490 .flags = DM_FLAG_PRE_RELOC,
494 }; 491 };
495 #endif 492 #endif
496 #endif /* !OF_PLATDATA */ 493 #endif /* !OF_PLATDATA */
497 #endif /* CONFIG_DM_SERIAL */ 494 #endif /* CONFIG_DM_SERIAL */
498 495
drivers/serial/serial_rockchip.c
Diff comments   View file @ 17fa032
1 /* 1 /*
2 * Copyright (c) 2015 Google, Inc 2 * Copyright (c) 2015 Google, Inc
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <debug_uart.h> 8 #include <debug_uart.h>
9 #include <dm.h> 9 #include <dm.h>
10 #include <dt-structs.h> 10 #include <dt-structs.h>
11 #include <ns16550.h> 11 #include <ns16550.h>
12 #include <serial.h> 12 #include <serial.h>
13 #include <asm/arch/clock.h> 13 #include <asm/arch/clock.h>
14 14
15 struct rockchip_uart_platdata { 15 struct rockchip_uart_platdata {
16 struct dtd_rockchip_rk3288_uart dtplat; 16 struct dtd_rockchip_rk3288_uart dtplat;
17 struct ns16550_platdata plat; 17 struct ns16550_platdata plat;
18 }; 18 };
19 19
20 struct dtd_rockchip_rk3288_uart *dtplat, s_dtplat; 20 struct dtd_rockchip_rk3288_uart *dtplat, s_dtplat;
21 21
22 static int rockchip_serial_probe(struct udevice *dev) 22 static int rockchip_serial_probe(struct udevice *dev)
23 { 23 {
24 struct rockchip_uart_platdata *plat = dev_get_platdata(dev); 24 struct rockchip_uart_platdata *plat = dev_get_platdata(dev);
25 25
26 /* Create some new platform data for the standard driver */ 26 /* Create some new platform data for the standard driver */
27 plat->plat.base = plat->dtplat.reg[0]; 27 plat->plat.base = plat->dtplat.reg[0];
28 plat->plat.reg_shift = plat->dtplat.reg_shift; 28 plat->plat.reg_shift = plat->dtplat.reg_shift;
29 plat->plat.clock = plat->dtplat.clock_frequency; 29 plat->plat.clock = plat->dtplat.clock_frequency;
30 plat->plat.fcr = UART_FCR_DEFVAL;
30 dev->platdata = &plat->plat; 31 dev->platdata = &plat->plat;
31 32
32 return ns16550_serial_probe(dev); 33 return ns16550_serial_probe(dev);
33 } 34 }
34 35
35 U_BOOT_DRIVER(rockchip_rk3288_uart) = { 36 U_BOOT_DRIVER(rockchip_rk3288_uart) = {
36 .name = "rockchip_rk3288_uart", 37 .name = "rockchip_rk3288_uart",
37 .id = UCLASS_SERIAL, 38 .id = UCLASS_SERIAL,
38 .priv_auto_alloc_size = sizeof(struct NS16550), 39 .priv_auto_alloc_size = sizeof(struct NS16550),
39 .platdata_auto_alloc_size = sizeof(struct rockchip_uart_platdata), 40 .platdata_auto_alloc_size = sizeof(struct rockchip_uart_platdata),
40 .probe = rockchip_serial_probe, 41 .probe = rockchip_serial_probe,
41 .ops = &ns16550_serial_ops, 42 .ops = &ns16550_serial_ops,
42 .flags = DM_FLAG_PRE_RELOC, 43 .flags = DM_FLAG_PRE_RELOC,
43 }; 44 };
44 45
1 /* 1 /*
2 * NS16550 Serial Port 2 * NS16550 Serial Port
3 * originally from linux source (arch/powerpc/boot/ns16550.h) 3 * originally from linux source (arch/powerpc/boot/ns16550.h)
4 * 4 *
5 * Cleanup and unification 5 * Cleanup and unification
6 * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH 6 * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH
7 * 7 *
8 * modified slightly to 8 * modified slightly to
9 * have addresses as offsets from CONFIG_SYS_ISA_BASE 9 * have addresses as offsets from CONFIG_SYS_ISA_BASE
10 * added a few more definitions 10 * added a few more definitions
11 * added prototypes for ns16550.c 11 * added prototypes for ns16550.c
12 * reduced no of com ports to 2 12 * reduced no of com ports to 2
13 * modifications (c) Rob Taylor, Flying Pig Systems. 2000. 13 * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
14 * 14 *
15 * added support for port on 64-bit bus 15 * added support for port on 64-bit bus
16 * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems 16 * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
17 */ 17 */
18 18
19 /* 19 /*
20 * Note that the following macro magic uses the fact that the compiler 20 * Note that the following macro magic uses the fact that the compiler
21 * will not allocate storage for arrays of size 0 21 * will not allocate storage for arrays of size 0
22 */ 22 */
23 23
24 #include <linux/types.h> 24 #include <linux/types.h>
25 25
26 #ifdef CONFIG_DM_SERIAL 26 #ifdef CONFIG_DM_SERIAL
27 /* 27 /*
28 * For driver model we always use one byte per register, and sort out the 28 * For driver model we always use one byte per register, and sort out the
29 * differences in the driver 29 * differences in the driver
30 */ 30 */
31 #define CONFIG_SYS_NS16550_REG_SIZE (-1) 31 #define CONFIG_SYS_NS16550_REG_SIZE (-1)
32 #endif 32 #endif
33 33
34 #if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0) 34 #if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0)
35 #error "Please define NS16550 registers size." 35 #error "Please define NS16550 registers size."
36 #elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_DM_SERIAL) 36 #elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_DM_SERIAL)
37 #define UART_REG(x) u32 x 37 #define UART_REG(x) u32 x
38 #elif (CONFIG_SYS_NS16550_REG_SIZE > 0) 38 #elif (CONFIG_SYS_NS16550_REG_SIZE > 0)
39 #define UART_REG(x) \ 39 #define UART_REG(x) \
40 unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \ 40 unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \
41 unsigned char x; 41 unsigned char x;
42 #elif (CONFIG_SYS_NS16550_REG_SIZE < 0) 42 #elif (CONFIG_SYS_NS16550_REG_SIZE < 0)
43 #define UART_REG(x) \ 43 #define UART_REG(x) \
44 unsigned char x; \ 44 unsigned char x; \
45 unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1]; 45 unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1];
46 #endif 46 #endif
47 47
48 /** 48 /**
49 * struct ns16550_platdata - information about a NS16550 port 49 * struct ns16550_platdata - information about a NS16550 port
50 * 50 *
51 * @base: Base register address 51 * @base: Base register address
52 * @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...) 52 * @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...)
53 * @clock: UART base clock speed in Hz 53 * @clock: UART base clock speed in Hz
54 */ 54 */
55 struct ns16550_platdata { 55 struct ns16550_platdata {
56 unsigned long base; 56 unsigned long base;
57 int reg_shift; 57 int reg_shift;
58 int clock; 58 int clock;
59 int reg_offset; 59 int reg_offset;
60 u32 fcr; 60 u32 fcr;
61 }; 61 };
62 62
63 struct udevice; 63 struct udevice;
64 64
65 struct NS16550 { 65 struct NS16550 {
66 UART_REG(rbr); /* 0 */ 66 UART_REG(rbr); /* 0 */
67 UART_REG(ier); /* 1 */ 67 UART_REG(ier); /* 1 */
68 UART_REG(fcr); /* 2 */ 68 UART_REG(fcr); /* 2 */
69 UART_REG(lcr); /* 3 */ 69 UART_REG(lcr); /* 3 */
70 UART_REG(mcr); /* 4 */ 70 UART_REG(mcr); /* 4 */
71 UART_REG(lsr); /* 5 */ 71 UART_REG(lsr); /* 5 */
72 UART_REG(msr); /* 6 */ 72 UART_REG(msr); /* 6 */
73 UART_REG(spr); /* 7 */ 73 UART_REG(spr); /* 7 */
74 #ifdef CONFIG_SOC_DA8XX 74 #ifdef CONFIG_SOC_DA8XX
75 UART_REG(reg8); /* 8 */ 75 UART_REG(reg8); /* 8 */
76 UART_REG(reg9); /* 9 */ 76 UART_REG(reg9); /* 9 */
77 UART_REG(revid1); /* A */ 77 UART_REG(revid1); /* A */
78 UART_REG(revid2); /* B */ 78 UART_REG(revid2); /* B */
79 UART_REG(pwr_mgmt); /* C */ 79 UART_REG(pwr_mgmt); /* C */
80 UART_REG(mdr1); /* D */ 80 UART_REG(mdr1); /* D */
81 #else 81 #else
82 UART_REG(mdr1); /* 8 */ 82 UART_REG(mdr1); /* 8 */
83 UART_REG(reg9); /* 9 */ 83 UART_REG(reg9); /* 9 */
84 UART_REG(regA); /* A */ 84 UART_REG(regA); /* A */
85 UART_REG(regB); /* B */ 85 UART_REG(regB); /* B */
86 UART_REG(regC); /* C */ 86 UART_REG(regC); /* C */
87 UART_REG(regD); /* D */ 87 UART_REG(regD); /* D */
88 UART_REG(regE); /* E */ 88 UART_REG(regE); /* E */
89 UART_REG(uasr); /* F */ 89 UART_REG(uasr); /* F */
90 UART_REG(scr); /* 10*/ 90 UART_REG(scr); /* 10*/
91 UART_REG(ssr); /* 11*/ 91 UART_REG(ssr); /* 11*/
92 #endif 92 #endif
93 #ifdef CONFIG_DM_SERIAL 93 #ifdef CONFIG_DM_SERIAL
94 struct ns16550_platdata *plat; 94 struct ns16550_platdata *plat;
95 #endif 95 #endif
96 }; 96 };
97 97
98 #define thr rbr 98 #define thr rbr
99 #define iir fcr 99 #define iir fcr
100 #define dll rbr 100 #define dll rbr
101 #define dlm ier 101 #define dlm ier
102 102
103 typedef struct NS16550 *NS16550_t; 103 typedef struct NS16550 *NS16550_t;
104 104
105 /* 105 /*
106 * These are the definitions for the FIFO Control Register 106 * These are the definitions for the FIFO Control Register
107 */ 107 */
108 #define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ 108 #define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
109 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ 109 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
110 #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ 110 #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
111 #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ 111 #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
112 #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ 112 #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
113 #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ 113 #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
114 #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ 114 #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
115 #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ 115 #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
116 #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ 116 #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
117 117
118 #define UART_FCR_RXSR 0x02 /* Receiver soft reset */ 118 #define UART_FCR_RXSR 0x02 /* Receiver soft reset */
119 #define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ 119 #define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
120 120
121 /* Ingenic JZ47xx specific UART-enable bit. */ 121 /* Ingenic JZ47xx specific UART-enable bit. */
122 #define UART_FCR_UME 0x10 122 #define UART_FCR_UME 0x10
123 123
124 /* Clear & enable FIFOs */
125 #define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | \
126 UART_FCR_RXSR | \
127 UART_FCR_TXSR)
128
124 /* 129 /*
125 * These are the definitions for the Modem Control Register 130 * These are the definitions for the Modem Control Register
126 */ 131 */
127 #define UART_MCR_DTR 0x01 /* DTR */ 132 #define UART_MCR_DTR 0x01 /* DTR */
128 #define UART_MCR_RTS 0x02 /* RTS */ 133 #define UART_MCR_RTS 0x02 /* RTS */
129 #define UART_MCR_OUT1 0x04 /* Out 1 */ 134 #define UART_MCR_OUT1 0x04 /* Out 1 */
130 #define UART_MCR_OUT2 0x08 /* Out 2 */ 135 #define UART_MCR_OUT2 0x08 /* Out 2 */
131 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ 136 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
132 #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */ 137 #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */
133 138
134 #define UART_MCR_DMA_EN 0x04 139 #define UART_MCR_DMA_EN 0x04
135 #define UART_MCR_TX_DFR 0x08 140 #define UART_MCR_TX_DFR 0x08
136 141
137 /* 142 /*
138 * These are the definitions for the Line Control Register 143 * These are the definitions for the Line Control Register
139 * 144 *
140 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting 145 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
141 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. 146 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
142 */ 147 */
143 #define UART_LCR_WLS_MSK 0x03 /* character length select mask */ 148 #define UART_LCR_WLS_MSK 0x03 /* character length select mask */
144 #define UART_LCR_WLS_5 0x00 /* 5 bit character length */ 149 #define UART_LCR_WLS_5 0x00 /* 5 bit character length */
145 #define UART_LCR_WLS_6 0x01 /* 6 bit character length */ 150 #define UART_LCR_WLS_6 0x01 /* 6 bit character length */
146 #define UART_LCR_WLS_7 0x02 /* 7 bit character length */ 151 #define UART_LCR_WLS_7 0x02 /* 7 bit character length */
147 #define UART_LCR_WLS_8 0x03 /* 8 bit character length */ 152 #define UART_LCR_WLS_8 0x03 /* 8 bit character length */
148 #define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */ 153 #define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */
149 #define UART_LCR_PEN 0x08 /* Parity eneble */ 154 #define UART_LCR_PEN 0x08 /* Parity eneble */
150 #define UART_LCR_EPS 0x10 /* Even Parity Select */ 155 #define UART_LCR_EPS 0x10 /* Even Parity Select */
151 #define UART_LCR_STKP 0x20 /* Stick Parity */ 156 #define UART_LCR_STKP 0x20 /* Stick Parity */
152 #define UART_LCR_SBRK 0x40 /* Set Break */ 157 #define UART_LCR_SBRK 0x40 /* Set Break */
153 #define UART_LCR_BKSE 0x80 /* Bank select enable */ 158 #define UART_LCR_BKSE 0x80 /* Bank select enable */
154 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ 159 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
155 160
156 /* 161 /*
157 * These are the definitions for the Line Status Register 162 * These are the definitions for the Line Status Register
158 */ 163 */
159 #define UART_LSR_DR 0x01 /* Data ready */ 164 #define UART_LSR_DR 0x01 /* Data ready */
160 #define UART_LSR_OE 0x02 /* Overrun */ 165 #define UART_LSR_OE 0x02 /* Overrun */
161 #define UART_LSR_PE 0x04 /* Parity error */ 166 #define UART_LSR_PE 0x04 /* Parity error */
162 #define UART_LSR_FE 0x08 /* Framing error */ 167 #define UART_LSR_FE 0x08 /* Framing error */
163 #define UART_LSR_BI 0x10 /* Break */ 168 #define UART_LSR_BI 0x10 /* Break */
164 #define UART_LSR_THRE 0x20 /* Xmit holding register empty */ 169 #define UART_LSR_THRE 0x20 /* Xmit holding register empty */
165 #define UART_LSR_TEMT 0x40 /* Xmitter empty */ 170 #define UART_LSR_TEMT 0x40 /* Xmitter empty */
166 #define UART_LSR_ERR 0x80 /* Error */ 171 #define UART_LSR_ERR 0x80 /* Error */
167 172
168 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ 173 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
169 #define UART_MSR_RI 0x40 /* Ring Indicator */ 174 #define UART_MSR_RI 0x40 /* Ring Indicator */
170 #define UART_MSR_DSR 0x20 /* Data Set Ready */ 175 #define UART_MSR_DSR 0x20 /* Data Set Ready */
171 #define UART_MSR_CTS 0x10 /* Clear to Send */ 176 #define UART_MSR_CTS 0x10 /* Clear to Send */
172 #define UART_MSR_DDCD 0x08 /* Delta DCD */ 177 #define UART_MSR_DDCD 0x08 /* Delta DCD */
173 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ 178 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
174 #define UART_MSR_DDSR 0x02 /* Delta DSR */ 179 #define UART_MSR_DDSR 0x02 /* Delta DSR */
175 #define UART_MSR_DCTS 0x01 /* Delta CTS */ 180 #define UART_MSR_DCTS 0x01 /* Delta CTS */
176 181
177 /* 182 /*
178 * These are the definitions for the Interrupt Identification Register 183 * These are the definitions for the Interrupt Identification Register
179 */ 184 */
180 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ 185 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
181 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ 186 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
182 187
183 #define UART_IIR_MSI 0x00 /* Modem status interrupt */ 188 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
184 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ 189 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
185 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ 190 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
186 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ 191 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
187 192
188 /* 193 /*
189 * These are the definitions for the Interrupt Enable Register 194 * These are the definitions for the Interrupt Enable Register
190 */ 195 */
191 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ 196 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
192 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ 197 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
193 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ 198 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
194 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ 199 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
195 200
196 /* useful defaults for LCR */ 201 /* useful defaults for LCR */
197 #define UART_LCR_8N1 0x03 202 #define UART_LCR_8N1 0x03
198 203
199 void NS16550_init(NS16550_t com_port, int baud_divisor); 204 void NS16550_init(NS16550_t com_port, int baud_divisor);
200 void NS16550_putc(NS16550_t com_port, char c); 205 void NS16550_putc(NS16550_t com_port, char c);
201 char NS16550_getc(NS16550_t com_port); 206 char NS16550_getc(NS16550_t com_port);
202 int NS16550_tstc(NS16550_t com_port); 207 int NS16550_tstc(NS16550_t com_port);
203 void NS16550_reinit(NS16550_t com_port, int baud_divisor); 208 void NS16550_reinit(NS16550_t com_port, int baud_divisor);
204 209
205 /** 210 /**
206 * ns16550_calc_divisor() - calculate the divisor given clock and baud rate 211 * ns16550_calc_divisor() - calculate the divisor given clock and baud rate
207 * 212 *
208 * Given the UART input clock and required baudrate, calculate the divisor 213 * Given the UART input clock and required baudrate, calculate the divisor
209 * that should be used. 214 * that should be used.
210 * 215 *
211 * @port: UART port 216 * @port: UART port
212 * @clock: UART input clock speed in Hz 217 * @clock: UART input clock speed in Hz
213 * @baudrate: Required baud rate 218 * @baudrate: Required baud rate
214 * @return baud rate divisor that should be used 219 * @return baud rate divisor that should be used
215 */ 220 */
216 int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate); 221 int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate);
217 222
218 /** 223 /**
219 * ns16550_serial_ofdata_to_platdata() - convert DT to platform data 224 * ns16550_serial_ofdata_to_platdata() - convert DT to platform data
220 * 225 *
221 * Decode a device tree node for an ns16550 device. This includes the 226 * Decode a device tree node for an ns16550 device. This includes the
222 * register base address and register shift properties. The caller must set 227 * register base address and register shift properties. The caller must set
223 * up the clock frequency. 228 * up the clock frequency.
224 * 229 *
225 * @dev: dev to decode platform data for 230 * @dev: dev to decode platform data for
226 * @return: 0 if OK, -EINVAL on error 231 * @return: 0 if OK, -EINVAL on error
227 */ 232 */
228 int ns16550_serial_ofdata_to_platdata(struct udevice *dev); 233 int ns16550_serial_ofdata_to_platdata(struct udevice *dev);
229 234
230 /** 235 /**
231 * ns16550_serial_probe() - probe a serial port 236 * ns16550_serial_probe() - probe a serial port
232 * 237 *
233 * This sets up the serial port ready for use, except for the baud rate 238 * This sets up the serial port ready for use, except for the baud rate
234 * @return 0, or -ve on error 239 * @return 0, or -ve on error
235 */ 240 */
236 int ns16550_serial_probe(struct udevice *dev); 241 int ns16550_serial_probe(struct udevice *dev);
237 242
238 /** 243 /**
239 * struct ns16550_serial_ops - ns16550 serial operations 244 * struct ns16550_serial_ops - ns16550 serial operations
240 * 245 *
241 * These should be used by the client driver for the driver's 'ops' member 246 * These should be used by the client driver for the driver's 'ops' member
242 */ 247 */
243 extern const struct dm_serial_ops ns16550_serial_ops; 248 extern const struct dm_serial_ops ns16550_serial_ops;
244 249