Eric Lee / smarc-uboot

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Commit 17fa032671f7981628fe16b30399638842a4b1bb

Authored by Heiko Schocher
Committed by Tom Rini
1 parent 0675f992db
Exists in smarc_8mq_lf_v2020.04 and in 22 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

serial, ns16550: bugfix: ns16550 fifo not enabled 

commit: 65f83802b7a5b "serial: 16550: Add getfcr accessor"
breaks u-boot commandline working with long commands
sending to the board.

Since the above patch, you have to setup the fcr register.

For board/archs which enable OF_PLATDATA, the new field
fcr in struct ns16550_platdata is not filled with a
default value ...

This leads in not setting up the uarts fifo, which ends
in problems, when you send long commands to u-boots
commandline.

Detected this issue with automated tbot tests on am335x
based shc board.

The error does not popup, if you type commands. You need
to copy&paste a long command to u-boots commandshell
(or send a long command with tbot)

Possible boards/plattforms with problems:
./arch/arm/cpu/arm926ejs/lpc32xx/devices.c
./arch/arm/mach-tegra/board.c
./board/overo/overo.c
./board/quipos/cairo/cairo.c
./board/logicpd/omap3som/omap3logic.c
./board/logicpd/zoom1/zoom1.c
./board/timll/devkit8000/devkit8000.c
./board/lg/sniper/sniper.c
./board/ti/beagle/beagle.c
./drivers/serial/serial_rockchip.c

Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

Showing 14 changed files with 46 additions and 24 deletions Side-by-side Diff

arch/arm/cpu/arm926ejs/lpc32xx/devices.c
Diff comments   View file @ 17fa032
... ... @@ -45,10 +45,14 @@
45 45  
46 46 #if !CONFIG_IS_ENABLED(OF_CONTROL)
47 47 static const struct ns16550_platdata lpc32xx_uart[] = {
48   - { .base = UART3_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
49   - { .base = UART4_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
50   - { .base = UART5_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
51   - { .base = UART6_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
  48 + { .base = UART3_BASE, .reg_shift = 2,
  49 + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  50 + { .base = UART4_BASE, .reg_shift = 2,
  51 + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  52 + { .base = UART5_BASE, .reg_shift = 2,
  53 + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  54 + { .base = UART6_BASE, .reg_shift = 2,
  55 + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
52 56 };
53 57  
54 58 #if defined(CONFIG_LPC32XX_HSUART)
arch/arm/mach-omap2/am33xx/board.c
Diff comments   View file @ 17fa032
... ... @@ -40,14 +40,20 @@
40 40  
41 41 #if !CONFIG_IS_ENABLED(OF_CONTROL)
42 42 static const struct ns16550_platdata am33xx_serial[] = {
43   - { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
  43 + { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
  44 + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
44 45 # ifdef CONFIG_SYS_NS16550_COM2
45   - { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
  46 + { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2,
  47 + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
46 48 # ifdef CONFIG_SYS_NS16550_COM3
47   - { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
48   - { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
49   - { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
50   - { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
  49 + { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2,
  50 + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  51 + { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2,
  52 + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  53 + { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2,
  54 + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  55 + { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2,
  56 + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
51 57 # endif
52 58 # endif
53 59 };
arch/arm/mach-tegra/board.c
Diff comments   View file @ 17fa032
... ... @@ -219,6 +219,7 @@
219 219 .base = CONFIG_SYS_NS16550_COM1,
220 220 .reg_shift = 2,
221 221 .clock = CONFIG_SYS_NS16550_CLK,
  222 + .fcr = UART_FCR_DEFVAL,
222 223 };
223 224  
224 225 U_BOOT_DEVICE(ns16550_com1) = {
board/isee/igep00x0/igep00x0.c
Diff comments   View file @ 17fa032
... ... @@ -32,7 +32,8 @@
32 32 static const struct ns16550_platdata igep_serial = {
33 33 .base = OMAP34XX_UART3,
34 34 .reg_shift = 2,
35   - .clock = V_NS16550_CLK
  35 + .clock = V_NS16550_CLK,
  36 + .fcr = UART_FCR_DEFVAL,
36 37 };
37 38  
38 39 U_BOOT_DEVICE(igep_uart) = {
board/lg/sniper/sniper.c
Diff comments   View file @ 17fa032
... ... @@ -31,7 +31,8 @@
31 31 static const struct ns16550_platdata serial_omap_platdata = {
32 32 .base = OMAP34XX_UART3,
33 33 .reg_shift = 2,
34   - .clock = V_NS16550_CLK
  34 + .clock = V_NS16550_CLK,
  35 + .fcr = UART_FCR_DEFVAL,
35 36 };
36 37  
37 38 U_BOOT_DEVICE(sniper_serial) = {
board/logicpd/omap3som/omap3logic.c
Diff comments   View file @ 17fa032
... ... @@ -49,7 +49,8 @@
49 49 static const struct ns16550_platdata omap3logic_serial = {
50 50 .base = OMAP34XX_UART1,
51 51 .reg_shift = 2,
52   - .clock = V_NS16550_CLK
  52 + .clock = V_NS16550_CLK,
  53 + .fcr = UART_FCR_DEFVAL,
53 54 };
54 55  
55 56 U_BOOT_DEVICE(omap3logic_uart) = {
board/logicpd/zoom1/zoom1.c
Diff comments   View file @ 17fa032
... ... @@ -47,7 +47,8 @@
47 47 static const struct ns16550_platdata zoom1_serial = {
48 48 .base = OMAP34XX_UART3,
49 49 .reg_shift = 2,
50   - .clock = V_NS16550_CLK
  50 + .clock = V_NS16550_CLK,
  51 + .fcr = UART_FCR_DEFVAL,
51 52 };
52 53  
53 54 U_BOOT_DEVICE(zoom1_uart) = {
... ... @@ -70,7 +70,8 @@
70 70 static const struct ns16550_platdata overo_serial = {
71 71 .base = OMAP34XX_UART3,
72 72 .reg_shift = 2,
73   - .clock = V_NS16550_CLK
  73 + .clock = V_NS16550_CLK,
  74 + .fcr = UART_FCR_DEFVAL,
74 75 };
75 76  
76 77 U_BOOT_DEVICE(overo_uart) = {
board/quipos/cairo/cairo.c
Diff comments   View file @ 17fa032
... ... @@ -93,7 +93,8 @@
93 93 static const struct ns16550_platdata cairo_serial = {
94 94 .base = OMAP34XX_UART2,
95 95 .reg_shift = 2,
96   - .clock = V_NS16550_CLK
  96 + .clock = V_NS16550_CLK,
  97 + .fcr = UART_FCR_DEFVAL,
97 98 };
98 99  
99 100 U_BOOT_DEVICE(cairo_uart) = {
board/ti/beagle/beagle.c
Diff comments   View file @ 17fa032
... ... @@ -75,7 +75,8 @@
75 75 static const struct ns16550_platdata beagle_serial = {
76 76 .base = OMAP34XX_UART3,
77 77 .reg_shift = 2,
78   - .clock = V_NS16550_CLK
  78 + .clock = V_NS16550_CLK,
  79 + .fcr = UART_FCR_DEFVAL,
79 80 };
80 81  
81 82 U_BOOT_DEVICE(beagle_uart) = {
board/timll/devkit8000/devkit8000.c
Diff comments   View file @ 17fa032
... ... @@ -48,7 +48,8 @@
48 48 static const struct ns16550_platdata devkit8000_serial = {
49 49 .base = OMAP34XX_UART3,
50 50 .reg_shift = 2,
51   - .clock = V_NS16550_CLK
  51 + .clock = V_NS16550_CLK,
  52 + .fcr = UART_FCR_DEFVAL,
52 53 };
53 54  
54 55 U_BOOT_DEVICE(devkit8000_uart) = {
drivers/serial/ns16550.c
Diff comments   View file @ 17fa032
... ... @@ -20,9 +20,6 @@
20 20 #define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */
21 21 #define UART_MCRVAL (UART_MCR_DTR | \
22 22 UART_MCR_RTS) /* RTS/DTR */
23   -#define UART_FCRVAL (UART_FCR_FIFO_EN | \
24   - UART_FCR_RXSR | \
25   - UART_FCR_TXSR) /* Clear & enable FIFOs */
26 23  
27 24 #ifndef CONFIG_DM_SERIAL
28 25 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
... ... @@ -138,7 +135,7 @@
138 135 #else
139 136 static u32 ns16550_getfcr(NS16550_t port)
140 137 {
141   - return UART_FCRVAL;
  138 + return UART_FCR_DEFVAL;
142 139 }
143 140 #endif
144 141  
... ... @@ -275,7 +272,7 @@
275 272 CONFIG_BAUDRATE);
276 273 serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER);
277 274 serial_dout(&com_port->mcr, UART_MCRVAL);
278   - serial_dout(&com_port->fcr, UART_FCRVAL);
  275 + serial_dout(&com_port->fcr, UART_FCR_DEFVAL);
279 276  
280 277 serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL);
281 278 serial_dout(&com_port->dll, baud_divisor & 0xff);
... ... @@ -440,7 +437,7 @@
440 437 return -EINVAL;
441 438 }
442 439  
443   - plat->fcr = UART_FCRVAL;
  440 + plat->fcr = UART_FCR_DEFVAL;
444 441 if (port_type == PORT_JZ4780)
445 442 plat->fcr |= UART_FCR_UME;
446 443  
drivers/serial/serial_rockchip.c
Diff comments   View file @ 17fa032
... ... @@ -27,6 +27,7 @@
27 27 plat->plat.base = plat->dtplat.reg[0];
28 28 plat->plat.reg_shift = plat->dtplat.reg_shift;
29 29 plat->plat.clock = plat->dtplat.clock_frequency;
  30 + plat->plat.fcr = UART_FCR_DEFVAL;
30 31 dev->platdata = &plat->plat;
31 32  
32 33 return ns16550_serial_probe(dev);
... ... @@ -121,6 +121,11 @@
121 121 /* Ingenic JZ47xx specific UART-enable bit. */
122 122 #define UART_FCR_UME 0x10
123 123  
  124 +/* Clear & enable FIFOs */
  125 +#define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | \
  126 + UART_FCR_RXSR | \
  127 + UART_FCR_TXSR)
  128 +
124 129 /*
125 130 * These are the definitions for the Modem Control Register
126 131 */