Commit 180b8688dca2a7731a291a7660ae188e6eec84b8
Committed by
York Sun
York Sun
1 parent
ec245fd74d
Exists in
v2017.01-smarct4x
and in
37 other branches
arm/ls1021a: add PCIe settings
The patch enables and adds PCIe settings for boards LS1021AQDS and LS1021ATWR. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Showing 2 changed files with 48 additions and 0 deletions Side-by-side Diff
include/configs/ls1021aqds.h
| ... | ... | @@ -510,6 +510,30 @@ |
| 510 | 510 | #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ |
| 511 | 511 | #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" |
| 512 | 512 | |
| 513 | +#define CONFIG_SYS_PCI_64BIT | |
| 514 | + | |
| 515 | +#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 | |
| 516 | +#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ | |
| 517 | +#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 | |
| 518 | +#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ | |
| 519 | + | |
| 520 | +#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 | |
| 521 | +#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 | |
| 522 | +#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ | |
| 523 | + | |
| 524 | +#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 | |
| 525 | +#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 | |
| 526 | +#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ | |
| 527 | + | |
| 528 | +#ifdef CONFIG_PCI | |
| 529 | +#define CONFIG_NET_MULTI | |
| 530 | +#define CONFIG_PCI_PNP | |
| 531 | +#define CONFIG_E1000 | |
| 532 | +#define CONFIG_PCI_SCAN_SHOW | |
| 533 | +#define CONFIG_CMD_PCI | |
| 534 | +#define CONFIG_CMD_NET | |
| 535 | +#endif | |
| 536 | + | |
| 513 | 537 | #define CONFIG_CMD_PING |
| 514 | 538 | #define CONFIG_CMD_DHCP |
| 515 | 539 | #define CONFIG_CMD_MII |
include/configs/ls1021atwr.h
| ... | ... | @@ -303,6 +303,30 @@ |
| 303 | 303 | #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ |
| 304 | 304 | #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" |
| 305 | 305 | |
| 306 | +#define CONFIG_SYS_PCI_64BIT | |
| 307 | + | |
| 308 | +#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 | |
| 309 | +#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ | |
| 310 | +#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 | |
| 311 | +#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ | |
| 312 | + | |
| 313 | +#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 | |
| 314 | +#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 | |
| 315 | +#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ | |
| 316 | + | |
| 317 | +#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 | |
| 318 | +#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 | |
| 319 | +#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ | |
| 320 | + | |
| 321 | +#ifdef CONFIG_PCI | |
| 322 | +#define CONFIG_NET_MULTI | |
| 323 | +#define CONFIG_PCI_PNP | |
| 324 | +#define CONFIG_E1000 | |
| 325 | +#define CONFIG_PCI_SCAN_SHOW | |
| 326 | +#define CONFIG_CMD_PCI | |
| 327 | +#define CONFIG_CMD_NET | |
| 328 | +#endif | |
| 329 | + | |
| 306 | 330 | #define CONFIG_CMD_PING |
| 307 | 331 | #define CONFIG_CMD_DHCP |
| 308 | 332 | #define CONFIG_CMD_MII |