Commit 181c65b814b29a9e12f5fd034e259c891f3bbb64
Committed by
Peng Fan
1 parent
ac76dd0836
Exists in
smarc_8mq_lf_v2020.04
and in
9 other branches
configs: ls1028a: use default SDHC clock divider value
The SDHC clock divider value for LS1028A should be default 2, not 1. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Showing 4 changed files with 0 additions and 4 deletions Side-by-side Diff
configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
configs/ls1028aqds_tfa_defconfig
configs/ls1028ardb_tfa_SECURE_BOOT_defconfig