Eric Lee / smarc-uboot

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Commit 18c1850717678a6a701641cc3d6d740624b2560e

Authored by Ye Li
1 parent 3121091350
Exists in smarc_8mq_lf_v2020.04 and in 4 other branches pitx_8mp_lf_v2020.04, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mp_lf_v2020.04

MLK-24971-1 imx8mp_evk: Change to nominal voltage on DDR4 EVK 

Because DDR4 runs at 3200MTS, this speed does not require to use overdrive
voltage for VDD_SOC, so set VDD_SOC to nominal 0.85v on DDR4 EVK.
The VDD_ARM was set to 0.95v to avoid timing risk from SOC to ARM when
VDD_SOC is 0.95v, set it back to 0.85v as well.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 5d556b8e214739deb5c3c71efa2ea8fc28f2a643)

Showing 1 changed file with 4 additions and 1 deletions Side-by-side Diff

board/freescale/imx8mp_evk/spl.c
Diff comments   View file @ 18c1850
... ... @@ -187,6 +187,7 @@
187 187 /* BUCKxOUT_DVS0/1 control BUCK123 output */
188 188 pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
189 189  
  190 +#ifdef CONFIG_IMX8M_LPDDR4
190 191 /*
191 192 * increase VDD_SOC to typical value 0.95V before first
192 193 * DRAM access, set DVS1 to 0.85v for suspend.
193 194  
... ... @@ -200,8 +201,10 @@
200 201 /* Kernel uses OD/OD freq for SOC */
201 202 /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
202 203 pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
  204 +#elif defined(CONFIG_IMX8M_DDR4)
  205 + /* DDR4 runs at 3200MTS, uses default ND 0.85v for VDD_SOC and VDD_ARM */
  206 + pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
203 207  
204   -#ifdef CONFIG_IMX8M_DDR4
205 208 /* Set NVCC_DRAM to 1.2v for DDR4 */
206 209 pmic_reg_write(p, PCA9450_BUCK6OUT, 0x18);
207 210 #endif