Commit 18d62cf12e4c736d1a7cf2c9e7404ba0cac270fa
1 parent
4daafb3509
Exists in
smarc_8mm-imx_v2019.04_4.19.35_1.1.0
and in
1 other branch
MLK-22851-1 mmc: fsl_esdhc: reduce unnecessary clock change
In mmc initial state, the mmc framework sets clock to 0, so the fsl_esdhc driver converts to use min clock 400Khz. But the priv->clock is logged 400Khz not 0, and cause following calls to set_ios to set clock again. Each set to clock has 10ms delay for stable, then the problem accumulates some unnecessary delay. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 151ab3bef2b1ec1c142c31048f3005ebce2a7a18)
Showing 1 changed file with 7 additions and 5 deletions Side-by-side Diff
drivers/mmc/fsl_esdhc.c
... | ... | @@ -636,9 +636,6 @@ |
636 | 636 | sdhc_clk >>= 1; |
637 | 637 | } |
638 | 638 | |
639 | - if (clock < mmc->cfg->f_min) | |
640 | - clock = mmc->cfg->f_min; | |
641 | - | |
642 | 639 | if (sdhc_clk / 16 > clock) { |
643 | 640 | for (; pre_div < 256; pre_div *= 2) |
644 | 641 | if ((sdhc_clk / pre_div) <= (clock * 16)) |
... | ... | @@ -971,6 +968,7 @@ |
971 | 968 | { |
972 | 969 | struct fsl_esdhc *regs = priv->esdhc_regs; |
973 | 970 | int ret __maybe_unused; |
971 | + uint clock; | |
974 | 972 | |
975 | 973 | #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK |
976 | 974 | /* Select to use peripheral clock */ |
... | ... | @@ -979,8 +977,12 @@ |
979 | 977 | esdhc_clock_control(priv, true); |
980 | 978 | #endif |
981 | 979 | /* Set the clock speed */ |
982 | - if (priv->clock != mmc->clock) | |
983 | - set_sysctl(priv, mmc, mmc->clock); | |
980 | + clock = mmc->clock; | |
981 | + if (clock < mmc->cfg->f_min) | |
982 | + clock = mmc->cfg->f_min; | |
983 | + | |
984 | + if (priv->clock != clock) | |
985 | + set_sysctl(priv, mmc, clock); | |
984 | 986 | |
985 | 987 | #ifdef MMC_SUPPORTS_TUNING |
986 | 988 | if (mmc->clk_disable) { |