Eric Lee / smarc-uboot

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Commit 1a048cd65645338069d591108031fa4ebe96d53f

Authored by Pankaj Bansal
Committed by Joe Hershberger
1 parent 1ed19a1421
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

driver: net: fsl-mc: Add support of multiple phys for dpmac 

Till now we have had cases where we had one phy device per dpmac.
Now, with the upcoming products (LX2160AQDS), we have cases, where there
are sometimes two phy devices for one dpmac. One phy for TX lanes and
one phy for RX lanes. to handle such cases, add the support for multiple
phys in ethernet driver. The ethernet link is up if all the phy devices
connected to one dpmac report link up. also the link capabilities are
limited by the weakest phy device.

i.e. say if there are two phys for one dpmac. one operates at 10G without
autoneg and other operate at 1G with autoneg. Then the ethernet interface
will operate at 1G without autoneg.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Showing 7 changed files with 162 additions and 109 deletions Side-by-side Diff

board/freescale/ls1088a/eth_ls1088aqds.c
Diff comments   View file @ 1a048cd
... ... @@ -487,16 +487,16 @@
487 487 case 0x3A:
488 488 switch (dpmac_id) {
489 489 case 1:
490   - wriop_set_phy_address(dpmac_id, riser_phy_addr[1]);
  490 + wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[1]);
491 491 break;
492 492 case 2:
493   - wriop_set_phy_address(dpmac_id, riser_phy_addr[0]);
  493 + wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[0]);
494 494 break;
495 495 case 3:
496   - wriop_set_phy_address(dpmac_id, riser_phy_addr[3]);
  496 + wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[3]);
497 497 break;
498 498 case 7:
499   - wriop_set_phy_address(dpmac_id, riser_phy_addr[2]);
  499 + wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[2]);
500 500 break;
501 501 default:
502 502 printf("WRIOP: Wrong DPMAC%d set to SGMII", dpmac_id);
503 503  
... ... @@ -532,13 +532,13 @@
532 532 case 4:
533 533 case 5:
534 534 case 6:
535   - wriop_set_phy_address(dpmac_id, dpmac_id + 9);
  535 + wriop_set_phy_address(dpmac_id, 0, dpmac_id + 9);
536 536 break;
537 537 case 7:
538 538 case 8:
539 539 case 9:
540 540 case 10:
541   - wriop_set_phy_address(dpmac_id, dpmac_id + 1);
  541 + wriop_set_phy_address(dpmac_id, 0, dpmac_id + 1);
542 542 break;
543 543 }
544 544  
... ... @@ -567,7 +567,7 @@
567 567 case 0x15:
568 568 case 0x1D:
569 569 case 0x1E:
570   - wriop_set_phy_address(i, i + 26);
  570 + wriop_set_phy_address(i, 0, i + 26);
571 571 ls1088a_qds_enable_SFP_TX(SFP_TX);
572 572 break;
573 573 default:
574 574  
... ... @@ -590,13 +590,13 @@
590 590  
591 591 switch (dpmac_id) {
592 592 case 4:
593   - wriop_set_phy_address(dpmac_id, RGMII_PHY1_ADDR);
  593 + wriop_set_phy_address(dpmac_id, 0, RGMII_PHY1_ADDR);
594 594 dpmac_info[dpmac_id].board_mux = EMI1_RGMII1;
595 595 bus = mii_dev_for_muxval(EMI1_RGMII1);
596 596 wriop_set_mdio(dpmac_id, bus);
597 597 break;
598 598 case 5:
599   - wriop_set_phy_address(dpmac_id, RGMII_PHY2_ADDR);
  599 + wriop_set_phy_address(dpmac_id, 0, RGMII_PHY2_ADDR);
600 600 dpmac_info[dpmac_id].board_mux = EMI1_RGMII2;
601 601 bus = mii_dev_for_muxval(EMI1_RGMII2);
602 602 wriop_set_mdio(dpmac_id, bus);
board/freescale/ls1088a/eth_ls1088ardb.c
Diff comments   View file @ 1a048cd
... ... @@ -55,16 +55,17 @@
55 55 * a MAC has no PHY address, we give a PHY address to XFI
56 56 * MAC error.
57 57 */
58   - wriop_set_phy_address(WRIOP1_DPMAC1, 0x0a);
59   - wriop_set_phy_address(WRIOP1_DPMAC2, AQ_PHY_ADDR1);
60   - wriop_set_phy_address(WRIOP1_DPMAC3, QSGMII1_PORT1_PHY_ADDR);
61   - wriop_set_phy_address(WRIOP1_DPMAC4, QSGMII1_PORT2_PHY_ADDR);
62   - wriop_set_phy_address(WRIOP1_DPMAC5, QSGMII1_PORT3_PHY_ADDR);
63   - wriop_set_phy_address(WRIOP1_DPMAC6, QSGMII1_PORT4_PHY_ADDR);
64   - wriop_set_phy_address(WRIOP1_DPMAC7, QSGMII2_PORT1_PHY_ADDR);
65   - wriop_set_phy_address(WRIOP1_DPMAC8, QSGMII2_PORT2_PHY_ADDR);
66   - wriop_set_phy_address(WRIOP1_DPMAC9, QSGMII2_PORT3_PHY_ADDR);
67   - wriop_set_phy_address(WRIOP1_DPMAC10, QSGMII2_PORT4_PHY_ADDR);
  58 + wriop_set_phy_address(WRIOP1_DPMAC1, 0, 0x0a);
  59 + wriop_set_phy_address(WRIOP1_DPMAC2, 0, AQ_PHY_ADDR1);
  60 + wriop_set_phy_address(WRIOP1_DPMAC3, 0, QSGMII1_PORT1_PHY_ADDR);
  61 + wriop_set_phy_address(WRIOP1_DPMAC4, 0, QSGMII1_PORT2_PHY_ADDR);
  62 + wriop_set_phy_address(WRIOP1_DPMAC5, 0, QSGMII1_PORT3_PHY_ADDR);
  63 + wriop_set_phy_address(WRIOP1_DPMAC6, 0, QSGMII1_PORT4_PHY_ADDR);
  64 + wriop_set_phy_address(WRIOP1_DPMAC7, 0, QSGMII2_PORT1_PHY_ADDR);
  65 + wriop_set_phy_address(WRIOP1_DPMAC8, 0, QSGMII2_PORT2_PHY_ADDR);
  66 + wriop_set_phy_address(WRIOP1_DPMAC9, 0, QSGMII2_PORT3_PHY_ADDR);
  67 + wriop_set_phy_address(WRIOP1_DPMAC10, 0,
  68 + QSGMII2_PORT4_PHY_ADDR);
68 69  
69 70 break;
70 71 default:
board/freescale/ls2080aqds/eth.c
Diff comments   View file @ 1a048cd
... ... @@ -623,7 +623,7 @@
623 623 switch (++slot) {
624 624 case 1:
625 625 /* Slot housing a SGMII riser card? */
626   - wriop_set_phy_address(dpmac_id,
  626 + wriop_set_phy_address(dpmac_id, 0,
627 627 riser_phy_addr[dpmac_id - 1]);
628 628 dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
629 629 bus = mii_dev_for_muxval(EMI1_SLOT1);
... ... @@ -631,7 +631,7 @@
631 631 break;
632 632 case 2:
633 633 /* Slot housing a SGMII riser card? */
634   - wriop_set_phy_address(dpmac_id,
  634 + wriop_set_phy_address(dpmac_id, 0,
635 635 riser_phy_addr[dpmac_id - 1]);
636 636 dpmac_info[dpmac_id].board_mux = EMI1_SLOT2;
637 637 bus = mii_dev_for_muxval(EMI1_SLOT2);
638 638  
639 639  
640 640  
... ... @@ -641,18 +641,18 @@
641 641 if (slot == EMI_NONE)
642 642 return;
643 643 if (serdes1_prtcl == 0x39) {
644   - wriop_set_phy_address(dpmac_id,
  644 + wriop_set_phy_address(dpmac_id, 0,
645 645 riser_phy_addr[dpmac_id - 2]);
646 646 if (dpmac_id >= 6 && hwconfig_f("xqsgmii",
647 647 env_hwconfig))
648   - wriop_set_phy_address(dpmac_id,
  648 + wriop_set_phy_address(dpmac_id, 0,
649 649 riser_phy_addr[dpmac_id - 3]);
650 650 } else {
651   - wriop_set_phy_address(dpmac_id,
  651 + wriop_set_phy_address(dpmac_id, 0,
652 652 riser_phy_addr[dpmac_id - 2]);
653 653 if (dpmac_id >= 7 && hwconfig_f("xqsgmii",
654 654 env_hwconfig))
655   - wriop_set_phy_address(dpmac_id,
  655 + wriop_set_phy_address(dpmac_id, 0,
656 656 riser_phy_addr[dpmac_id - 3]);
657 657 }
658 658 dpmac_info[dpmac_id].board_mux = EMI1_SLOT3;
... ... @@ -691,7 +691,7 @@
691 691 break;
692 692 case 4:
693 693 /* Slot housing a SGMII riser card? */
694   - wriop_set_phy_address(dpmac_id,
  694 + wriop_set_phy_address(dpmac_id, 0,
695 695 riser_phy_addr[dpmac_id - 9]);
696 696 dpmac_info[dpmac_id].board_mux = EMI1_SLOT4;
697 697 bus = mii_dev_for_muxval(EMI1_SLOT4);
698 698  
699 699  
... ... @@ -701,14 +701,14 @@
701 701 if (slot == EMI_NONE)
702 702 return;
703 703 if (serdes2_prtcl == 0x47) {
704   - wriop_set_phy_address(dpmac_id,
  704 + wriop_set_phy_address(dpmac_id, 0,
705 705 riser_phy_addr[dpmac_id - 10]);
706 706 if (dpmac_id >= 14 && hwconfig_f("xqsgmii",
707 707 env_hwconfig))
708   - wriop_set_phy_address(dpmac_id,
  708 + wriop_set_phy_address(dpmac_id, 0,
709 709 riser_phy_addr[dpmac_id - 11]);
710 710 } else {
711   - wriop_set_phy_address(dpmac_id,
  711 + wriop_set_phy_address(dpmac_id, 0,
712 712 riser_phy_addr[dpmac_id - 11]);
713 713 }
714 714 dpmac_info[dpmac_id].board_mux = EMI1_SLOT5;
... ... @@ -717,7 +717,7 @@
717 717 break;
718 718 case 6:
719 719 /* Slot housing a SGMII riser card? */
720   - wriop_set_phy_address(dpmac_id,
  720 + wriop_set_phy_address(dpmac_id, 0,
721 721 riser_phy_addr[dpmac_id - 13]);
722 722 dpmac_info[dpmac_id].board_mux = EMI1_SLOT6;
723 723 bus = mii_dev_for_muxval(EMI1_SLOT6);
... ... @@ -775,7 +775,7 @@
775 775 switch (++slot) {
776 776 case 1:
777 777 /* Slot housing a QSGMII riser card? */
778   - wriop_set_phy_address(dpmac_id, dpmac_id - 1);
  778 + wriop_set_phy_address(dpmac_id, 0, dpmac_id - 1);
779 779 dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
780 780 bus = mii_dev_for_muxval(EMI1_SLOT1);
781 781 wriop_set_mdio(dpmac_id, bus);
... ... @@ -819,7 +819,7 @@
819 819 * the XAUI card is used for the XFI MAC, which will cause
820 820 * error.
821 821 */
822   - wriop_set_phy_address(i, i + 4);
  822 + wriop_set_phy_address(i, 0, i + 4);
823 823 ls2080a_qds_enable_SFP_TX(SFP_TX);
824 824  
825 825 break;
board/freescale/ls2080ardb/eth_ls2080rdb.c
Diff comments   View file @ 1a048cd
... ... @@ -50,21 +50,21 @@
50 50  
51 51 switch (srds_s1) {
52 52 case 0x2A:
53   - wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
54   - wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
55   - wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
56   - wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
57   - wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1);
58   - wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2);
59   - wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3);
60   - wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);
  53 + wriop_set_phy_address(WRIOP1_DPMAC1, 0, CORTINA_PHY_ADDR1);
  54 + wriop_set_phy_address(WRIOP1_DPMAC2, 0, CORTINA_PHY_ADDR2);
  55 + wriop_set_phy_address(WRIOP1_DPMAC3, 0, CORTINA_PHY_ADDR3);
  56 + wriop_set_phy_address(WRIOP1_DPMAC4, 0, CORTINA_PHY_ADDR4);
  57 + wriop_set_phy_address(WRIOP1_DPMAC5, 0, AQ_PHY_ADDR1);
  58 + wriop_set_phy_address(WRIOP1_DPMAC6, 0, AQ_PHY_ADDR2);
  59 + wriop_set_phy_address(WRIOP1_DPMAC7, 0, AQ_PHY_ADDR3);
  60 + wriop_set_phy_address(WRIOP1_DPMAC8, 0, AQ_PHY_ADDR4);
61 61  
62 62 break;
63 63 case 0x4B:
64   - wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
65   - wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
66   - wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
67   - wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
  64 + wriop_set_phy_address(WRIOP1_DPMAC1, 0, CORTINA_PHY_ADDR1);
  65 + wriop_set_phy_address(WRIOP1_DPMAC2, 0, CORTINA_PHY_ADDR2);
  66 + wriop_set_phy_address(WRIOP1_DPMAC3, 0, CORTINA_PHY_ADDR3);
  67 + wriop_set_phy_address(WRIOP1_DPMAC4, 0, CORTINA_PHY_ADDR4);
68 68  
69 69 break;
70 70 default:
drivers/net/ldpaa_eth/ldpaa_eth.c
Diff comments   View file @ 1a048cd
... ... @@ -23,26 +23,40 @@
23 23 struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)dev->priv;
24 24 struct phy_device *phydev = NULL;
25 25 struct mii_dev *bus;
26   - int ret;
  26 + int phy_addr, phy_num;
  27 + int ret = 0;
27 28  
28 29 bus = wriop_get_mdio(priv->dpmac_id);
29 30 if (bus == NULL)
30 31 return 0;
31 32  
32   - phydev = phy_connect(bus, wriop_get_phy_address(priv->dpmac_id),
33   - dev, wriop_get_enet_if(priv->dpmac_id));
34   - if (!phydev) {
35   - printf("Failed to connect\n");
36   - return -1;
  33 + for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
  34 + phy_addr = wriop_get_phy_address(priv->dpmac_id, phy_num);
  35 + if (phy_addr < 0)
  36 + continue;
  37 +
  38 + phydev = phy_connect(bus, phy_addr, dev,
  39 + wriop_get_enet_if(priv->dpmac_id));
  40 + if (!phydev) {
  41 + printf("Failed to connect\n");
  42 + ret = -ENODEV;
  43 + break;
  44 + }
  45 + wriop_set_phy_dev(priv->dpmac_id, phy_num, phydev);
  46 + ret = phy_config(phydev);
  47 + if (ret)
  48 + break;
37 49 }
38 50  
39   - wriop_set_phy_dev(priv->dpmac_id, phydev);
40   -
41   - ret = phy_config(phydev);
42   -
43 51 if (ret) {
44   - free(phydev);
45   - wriop_set_phy_dev(priv->dpmac_id, NULL);
  52 + for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
  53 + phydev = wriop_get_phy_dev(priv->dpmac_id, phy_num);
  54 + if (!phydev)
  55 + continue;
  56 +
  57 + free(phydev);
  58 + wriop_set_phy_dev(priv->dpmac_id, phy_num, NULL);
  59 + }
46 60 }
47 61  
48 62 return ret;
49 63  
... ... @@ -390,10 +404,10 @@
390 404 {
391 405 struct phy_device *phydev = NULL;
392 406 phy_interface_t enet_if;
  407 + int phy_num, phys_detected;
393 408 int err;
394 409  
395   - /* let's start off with maximum capabilities
396   - */
  410 + /* let's start off with maximum capabilities */
397 411 enet_if = wriop_get_enet_if(priv->dpmac_id);
398 412 switch (enet_if) {
399 413 case PHY_INTERFACE_MODE_XGMII:
400 414  
401 415  
... ... @@ -405,15 +419,22 @@
405 419 }
406 420 state->up = 1;
407 421  
  422 + phys_detected = 0;
408 423 #ifdef CONFIG_PHYLIB
409 424 state->options |= DPMAC_LINK_OPT_AUTONEG;
410 425  
411   - phydev = wriop_get_phy_dev(priv->dpmac_id);
412   - if (phydev) {
  426 + /* start the phy devices one by one and update the dpmac state */
  427 + for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
  428 + phydev = wriop_get_phy_dev(priv->dpmac_id, phy_num);
  429 + if (!phydev)
  430 + continue;
  431 +
  432 + phys_detected++;
413 433 err = phy_startup(phydev);
414 434 if (err) {
415 435 printf("%s: Could not initialize\n", phydev->dev->name);
416 436 state->up = 0;
  437 + break;
417 438 }
418 439 if (phydev->link) {
419 440 state->rate = min(state->rate, (uint32_t)phydev->speed);
420 441  
421 442  
... ... @@ -422,11 +443,13 @@
422 443 if (!phydev->autoneg)
423 444 state->options &= ~DPMAC_LINK_OPT_AUTONEG;
424 445 } else {
  446 + /* break out of loop even if one phy is down */
425 447 state->up = 0;
  448 + break;
426 449 }
427 450 }
428 451 #endif
429   - if (!phydev)
  452 + if (!phys_detected)
430 453 state->options &= ~DPMAC_LINK_OPT_AUTONEG;
431 454  
432 455 if (!state->up) {
... ... @@ -568,6 +591,7 @@
568 591 struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
569 592 int err = 0;
570 593 struct phy_device *phydev = NULL;
  594 + int phy_num;
571 595  
572 596 if ((net_dev->state == ETH_STATE_PASSIVE) ||
573 597 (net_dev->state == ETH_STATE_INIT))
... ... @@ -600,9 +624,11 @@
600 624 printf("dpni_disable() failed\n");
601 625  
602 626 #ifdef CONFIG_PHYLIB
603   - phydev = wriop_get_phy_dev(priv->dpmac_id);
604   - if (phydev)
605   - phy_shutdown(phydev);
  627 + for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
  628 + phydev = wriop_get_phy_dev(priv->dpmac_id, phy_num);
  629 + if (phydev)
  630 + phy_shutdown(phydev);
  631 + }
606 632 #endif
607 633  
608 634 /* Free DPBP handle and reset. */
drivers/net/ldpaa_eth/ldpaa_wriop.c
Diff comments   View file @ 1a048cd
... ... @@ -22,11 +22,10 @@
22 22 void wriop_init_dpmac(int sd, int dpmac_id, int lane_prtcl)
23 23 {
24 24 phy_interface_t enet_if;
  25 + int phy_num;
25 26  
26 27 dpmac_info[dpmac_id].enabled = 0;
27 28 dpmac_info[dpmac_id].id = 0;
28   - dpmac_info[dpmac_id].phy_addr = -1;
29   - dpmac_info[dpmac_id].phydev = NULL;
30 29 dpmac_info[dpmac_id].enet_if = PHY_INTERFACE_MODE_NONE;
31 30  
32 31 enet_if = wriop_dpmac_enet_if(dpmac_id, lane_prtcl);
33 32  
34 33  
35 34  
... ... @@ -35,15 +34,23 @@
35 34 dpmac_info[dpmac_id].id = dpmac_id;
36 35 dpmac_info[dpmac_id].enet_if = enet_if;
37 36 }
  37 + for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
  38 + dpmac_info[dpmac_id].phydev[phy_num] = NULL;
  39 + dpmac_info[dpmac_id].phy_addr[phy_num] = -1;
  40 + }
38 41 }
39 42  
40 43 void wriop_init_dpmac_enet_if(int dpmac_id, phy_interface_t enet_if)
41 44 {
  45 + int phy_num;
  46 +
42 47 dpmac_info[dpmac_id].enabled = 1;
43 48 dpmac_info[dpmac_id].id = dpmac_id;
44   - dpmac_info[dpmac_id].phy_addr = -1;
45 49 dpmac_info[dpmac_id].enet_if = enet_if;
46   - dpmac_info[dpmac_id].phydev = NULL;
  50 + for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
  51 + dpmac_info[dpmac_id].phydev[phy_num] = NULL;
  52 + dpmac_info[dpmac_id].phy_addr[phy_num] = -1;
  53 + }
47 54 }
48 55  
49 56  
50 57  
51 58  
52 59  
53 60  
54 61  
55 62  
56 63  
57 64  
58 65  
59 66  
... ... @@ -60,47 +67,53 @@
60 67 return -1;
61 68 }
62 69  
63   -void wriop_disable_dpmac(int dpmac_id)
  70 +int wriop_disable_dpmac(int dpmac_id)
64 71 {
65 72 int i = wriop_dpmac_to_index(dpmac_id);
66 73  
67 74 if (i == -1)
68   - return;
  75 + return -ENODEV;
69 76  
70 77 dpmac_info[i].enabled = 0;
71 78 wriop_dpmac_disable(dpmac_id);
  79 +
  80 + return 0;
72 81 }
73 82  
74   -void wriop_enable_dpmac(int dpmac_id)
  83 +int wriop_enable_dpmac(int dpmac_id)
75 84 {
76 85 int i = wriop_dpmac_to_index(dpmac_id);
77 86  
78 87 if (i == -1)
79   - return;
  88 + return -ENODEV;
80 89  
81 90 dpmac_info[i].enabled = 1;
82 91 wriop_dpmac_enable(dpmac_id);
  92 +
  93 + return 0;
83 94 }
84 95  
85   -u8 wriop_is_enabled_dpmac(int dpmac_id)
  96 +int wriop_is_enabled_dpmac(int dpmac_id)
86 97 {
87 98 int i = wriop_dpmac_to_index(dpmac_id);
88 99  
89 100 if (i == -1)
90   - return -1;
  101 + return -ENODEV;
91 102  
92 103 return dpmac_info[i].enabled;
93 104 }
94 105  
95 106  
96   -void wriop_set_mdio(int dpmac_id, struct mii_dev *bus)
  107 +int wriop_set_mdio(int dpmac_id, struct mii_dev *bus)
97 108 {
98 109 int i = wriop_dpmac_to_index(dpmac_id);
99 110  
100 111 if (i == -1)
101   - return;
  112 + return -ENODEV;
102 113  
103 114 dpmac_info[i].bus = bus;
  115 +
  116 + return 0;
104 117 }
105 118  
106 119 struct mii_dev *wriop_get_mdio(int dpmac_id)
107 120  
108 121  
109 122  
110 123  
111 124  
112 125  
113 126  
114 127  
115 128  
116 129  
117 130  
... ... @@ -113,44 +126,56 @@
113 126 return dpmac_info[i].bus;
114 127 }
115 128  
116   -void wriop_set_phy_address(int dpmac_id, int address)
  129 +int wriop_set_phy_address(int dpmac_id, int phy_num, int address)
117 130 {
118 131 int i = wriop_dpmac_to_index(dpmac_id);
119 132  
120 133 if (i == -1)
121   - return;
  134 + return -ENODEV;
  135 + if (phy_num < 0 || phy_num >= WRIOP_MAX_PHY_NUM)
  136 + return -EINVAL;
122 137  
123   - dpmac_info[i].phy_addr = address;
  138 + dpmac_info[i].phy_addr[phy_num] = address;
  139 +
  140 + return 0;
124 141 }
125 142  
126   -int wriop_get_phy_address(int dpmac_id)
  143 +int wriop_get_phy_address(int dpmac_id, int phy_num)
127 144 {
128 145 int i = wriop_dpmac_to_index(dpmac_id);
129 146  
130 147 if (i == -1)
131   - return -1;
  148 + return -ENODEV;
  149 + if (phy_num < 0 || phy_num >= WRIOP_MAX_PHY_NUM)
  150 + return -EINVAL;
132 151  
133   - return dpmac_info[i].phy_addr;
  152 + return dpmac_info[i].phy_addr[phy_num];
134 153 }
135 154  
136   -void wriop_set_phy_dev(int dpmac_id, struct phy_device *phydev)
  155 +int wriop_set_phy_dev(int dpmac_id, int phy_num, struct phy_device *phydev)
137 156 {
138 157 int i = wriop_dpmac_to_index(dpmac_id);
139 158  
140 159 if (i == -1)
141   - return;
  160 + return -ENODEV;
  161 + if (phy_num < 0 || phy_num >= WRIOP_MAX_PHY_NUM)
  162 + return -EINVAL;
142 163  
143   - dpmac_info[i].phydev = phydev;
  164 + dpmac_info[i].phydev[phy_num] = phydev;
  165 +
  166 + return 0;
144 167 }
145 168  
146   -struct phy_device *wriop_get_phy_dev(int dpmac_id)
  169 +struct phy_device *wriop_get_phy_dev(int dpmac_id, int phy_num)
147 170 {
148 171 int i = wriop_dpmac_to_index(dpmac_id);
149 172  
150 173 if (i == -1)
151 174 return NULL;
  175 + if (phy_num < 0 || phy_num >= WRIOP_MAX_PHY_NUM)
  176 + return NULL;
152 177  
153   - return dpmac_info[i].phydev;
  178 + return dpmac_info[i].phydev[phy_num];
154 179 }
155 180  
156 181 phy_interface_t wriop_get_enet_if(int dpmac_id)
include/fsl-mc/ldpaa_wriop.h
Diff comments   View file @ 1a048cd
... ... @@ -6,8 +6,12 @@
6 6 #ifndef __LDPAA_WRIOP_H
7 7 #define __LDPAA_WRIOP_H
8 8  
9   - #include <phy.h>
  9 +#include <phy.h>
10 10  
  11 +#define DEFAULT_WRIOP_MDIO1_NAME "FSL_MDIO0"
  12 +#define DEFAULT_WRIOP_MDIO2_NAME "FSL_MDIO1"
  13 +#define WRIOP_MAX_PHY_NUM 2
  14 +
11 15 enum wriop_port {
12 16 WRIOP1_DPMAC1 = 1,
13 17 WRIOP1_DPMAC2,
14 18  
15 19  
16 20  
17 21  
... ... @@ -40,34 +44,31 @@
40 44 u8 enabled;
41 45 u8 id;
42 46 u8 board_mux;
43   - int phy_addr;
  47 + int phy_addr[WRIOP_MAX_PHY_NUM];
44 48 phy_interface_t enet_if;
45   - struct phy_device *phydev;
  49 + struct phy_device *phydev[WRIOP_MAX_PHY_NUM];
46 50 struct mii_dev *bus;
47 51 };
48 52  
49 53 extern struct wriop_dpmac_info dpmac_info[NUM_WRIOP_PORTS];
50 54  
51   -#define DEFAULT_WRIOP_MDIO1_NAME "FSL_MDIO0"
52   -#define DEFAULT_WRIOP_MDIO2_NAME "FSL_MDIO1"
  55 +void wriop_init_dpmac(int sd, int dpmac_id, int lane_prtcl);
  56 +void wriop_init_dpmac_enet_if(int dpmac_id, phy_interface_t enet_if);
  57 +int wriop_disable_dpmac(int dpmac_id);
  58 +int wriop_enable_dpmac(int dpmac_id);
  59 +int wriop_is_enabled_dpmac(int dpmac_id);
  60 +int wriop_set_mdio(int dpmac_id, struct mii_dev *bus);
  61 +struct mii_dev *wriop_get_mdio(int dpmac_id);
  62 +int wriop_set_phy_address(int dpmac_id, int phy_num, int address);
  63 +int wriop_get_phy_address(int dpmac_id, int phy_num);
  64 +int wriop_set_phy_dev(int dpmac_id, int phy_num, struct phy_device *phydev);
  65 +struct phy_device *wriop_get_phy_dev(int dpmac_id, int phy_num);
  66 +phy_interface_t wriop_get_enet_if(int dpmac_id);
53 67  
54   -void wriop_init_dpmac(int, int, int);
55   -void wriop_disable_dpmac(int);
56   -void wriop_enable_dpmac(int);
57   -u8 wriop_is_enabled_dpmac(int dpmac_id);
58   -void wriop_set_mdio(int, struct mii_dev *);
59   -struct mii_dev *wriop_get_mdio(int);
60   -void wriop_set_phy_address(int, int);
61   -int wriop_get_phy_address(int);
62   -void wriop_set_phy_dev(int, struct phy_device *);
63   -struct phy_device *wriop_get_phy_dev(int);
64   -phy_interface_t wriop_get_enet_if(int);
65   -
66   -void wriop_dpmac_disable(int);
67   -void wriop_dpmac_enable(int);
68   -phy_interface_t wriop_dpmac_enet_if(int, int);
69   -void wriop_init_dpmac_qsgmii(int, int);
  68 +void wriop_dpmac_disable(int dpmac_id);
  69 +void wriop_dpmac_enable(int dpmac_id);
  70 +phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl);
  71 +void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl);
70 72 void wriop_init_rgmii(void);
71   -void wriop_init_dpmac_enet_if(int , phy_interface_t);
72 73 #endif /* __LDPAA_WRIOP_H */