Eric Lee / smarc-uboot

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Commit 1a2621bab89c3fd6bd09a601b0b94dc26e238d7c

Authored by Yoshihiro Shimoda
Committed by Nobuhiro Iwamatsu
1 parent 095728803e
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

sh: add support for sh7752evb board 

The R0P7752C00000RZ board has SH7752, 512MB DDR3-SDRAM, SPI ROM,
Gigabit Ethernet, and eMMC.

This patch supports the following functions:
 - 512MB DDR3-SDRAM, SCIF4, SPI ROM, Gigabit Ethernet, eMMC

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Showing 11 changed files with 1474 additions and 0 deletions Side-by-side Diff

... ... @@ -1202,6 +1202,7 @@
1202 1202 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
1203 1203  
1204 1204 MS7720SE SH7720
  1205 + R0P77520000RZ SH7752
1205 1206 R0P77570030RL SH7757
1206 1207 R0P77850011RL SH7785
1207 1208  
arch/sh/include/asm/cpu_sh4.h
Diff comments   View file @ 1a2621b
... ... @@ -48,6 +48,8 @@
48 48 # include <asm/cpu_sh7724.h>
49 49 #elif defined (CONFIG_CPU_SH7734)
50 50 # include <asm/cpu_sh7734.h>
  51 +#elif defined (CONFIG_CPU_SH7752)
  52 +# include <asm/cpu_sh7752.h>
51 53 #elif defined (CONFIG_CPU_SH7757)
52 54 # include <asm/cpu_sh7757.h>
53 55 #elif defined (CONFIG_CPU_SH7763)
arch/sh/include/asm/cpu_sh7752.h
Diff comments   View file @ 1a2621b
  1 +/*
  2 + * Copyright (C) 2012 Renesas Solutions Corp.
  3 + *
  4 + * This program is free software; you can redistribute it and/or
  5 + * modify it under the terms of the GNU General Public License as
  6 + * published by the Free Software Foundation; either version 2 of
  7 + * the License, or (at your option) any later version.
  8 + *
  9 + * This program is distributed in the hope that it will be useful,
  10 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12 + * GNU General Public License for more details.
  13 + *
  14 + * You should have received a copy of the GNU General Public License
  15 + * along with this program; if not, write to the Free Software
  16 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17 + * MA 02111-1307 USA
  18 + *
  19 + */
  20 +
  21 +#ifndef _ASM_CPU_SH7752_H_
  22 +#define _ASM_CPU_SH7752_H_
  23 +
  24 +#define CCR 0xFF00001C
  25 +#define WTCNT 0xFFCC0000
  26 +#define CCR_CACHE_INIT 0x0000090b
  27 +#define CACHE_OC_NUM_WAYS 1
  28 +
  29 +#ifndef __ASSEMBLY__ /* put C only stuff in this section */
  30 +/* MMU */
  31 +struct mmu_regs {
  32 + unsigned int reserved[4];
  33 + unsigned int mmucr;
  34 +};
  35 +#define MMU_BASE ((struct mmu_regs *)0xff000000)
  36 +
  37 +/* Watchdog */
  38 +#define WTCSR0 0xffcc0002
  39 +#define WRSTCSR_R 0xffcc0003
  40 +#define WRSTCSR_W 0xffcc0002
  41 +#define WTCSR_PREFIX 0xa500
  42 +#define WRSTCSR_PREFIX 0x6900
  43 +#define WRSTCSR_WOVF_PREFIX 0x9600
  44 +
  45 +/* SCIF */
  46 +#define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */
  47 +#define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */
  48 +#define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */
  49 +
  50 +/* TMU0 */
  51 +#define TMU_BASE 0xFE430000
  52 +
  53 +/* ETHER, GETHER MAC address */
  54 +struct ether_mac_regs {
  55 + unsigned int reserved[114];
  56 + unsigned int mahr;
  57 + unsigned int reserved2;
  58 + unsigned int malr;
  59 +};
  60 +#define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee0400)
  61 +#define GETHER1_MAC_BASE ((struct ether_mac_regs *)0xfee0c00)
  62 +#define ETHER0_MAC_BASE ((struct ether_mac_regs *)0xfef0000)
  63 +#define ETHER1_MAC_BASE ((struct ether_mac_regs *)0xfef0800)
  64 +
  65 +/* GETHER */
  66 +struct gether_control_regs {
  67 + unsigned int gbecont;
  68 +};
  69 +#define GETHER_CONTROL_BASE ((struct gether_control_regs *)0xffc10100)
  70 +#define GBECONT_RMII1 0x00020000
  71 +#define GBECONT_RMII0 0x00010000
  72 +
  73 +/* SerMux */
  74 +struct sermux_regs {
  75 + unsigned char smr0;
  76 + unsigned char smr1;
  77 + unsigned char smr2;
  78 + unsigned char smr3;
  79 + unsigned char smr4;
  80 + unsigned char smr5;
  81 +};
  82 +#define SERMUX_BASE ((struct sermux_regs *)0xfe470000)
  83 +
  84 +
  85 +/* USB0/1 */
  86 +struct usb_common_regs {
  87 + unsigned short reserved[129];
  88 + unsigned short suspmode;
  89 +};
  90 +#define USB0_COMMON_BASE ((struct usb_common_regs *)0xfe450000)
  91 +#define USB1_COMMON_BASE ((struct usb_common_regs *)0xfe4f0000)
  92 +
  93 +struct usb0_phy_regs {
  94 + unsigned short reset;
  95 + unsigned short reserved[4];
  96 + unsigned short portsel;
  97 +};
  98 +#define USB0_PHY_BASE ((struct usb0_phy_regs *)0xfe5f0000)
  99 +
  100 +struct usb1_port_regs {
  101 + unsigned int port1sel;
  102 + unsigned int reserved;
  103 + unsigned int usb1intsts;
  104 +};
  105 +#define USB1_PORT_BASE ((struct usb1_port_regs *)0xfe4f2000)
  106 +
  107 +struct usb1_alignment_regs {
  108 + unsigned int ehcidatac; /* 0xfe4fe018 */
  109 + unsigned int reserved[63];
  110 + unsigned int ohcidatac;
  111 +};
  112 +#define USB1_ALIGNMENT_BASE ((struct usb1_alignment_regs *)0xfe4fe018)
  113 +
  114 +/* GPIO */
  115 +struct gpio_regs {
  116 + unsigned short pacr;
  117 + unsigned short pbcr;
  118 + unsigned short pccr;
  119 + unsigned short pdcr;
  120 + unsigned short pecr;
  121 + unsigned short pfcr;
  122 + unsigned short pgcr;
  123 + unsigned short phcr;
  124 + unsigned short picr;
  125 + unsigned short pjcr;
  126 + unsigned short pkcr;
  127 + unsigned short plcr;
  128 + unsigned short pmcr;
  129 + unsigned short pncr;
  130 + unsigned short pocr;
  131 + unsigned short reserved;
  132 + unsigned short pqcr;
  133 + unsigned short prcr;
  134 + unsigned short pscr;
  135 + unsigned short ptcr;
  136 + unsigned short pucr;
  137 + unsigned short pvcr;
  138 + unsigned short pwcr;
  139 + unsigned short pxcr;
  140 + unsigned short pycr;
  141 + unsigned short pzcr;
  142 + unsigned char padr;
  143 + unsigned char reserved_a;
  144 + unsigned char pbdr;
  145 + unsigned char reserved_b;
  146 + unsigned char pcdr;
  147 + unsigned char reserved_c;
  148 + unsigned char pddr;
  149 + unsigned char reserved_d;
  150 + unsigned char pedr;
  151 + unsigned char reserved_e;
  152 + unsigned char pfdr;
  153 + unsigned char reserved_f;
  154 + unsigned char pgdr;
  155 + unsigned char reserved_g;
  156 + unsigned char phdr;
  157 + unsigned char reserved_h;
  158 + unsigned char pidr;
  159 + unsigned char reserved_i;
  160 + unsigned char pjdr;
  161 + unsigned char reserved_j;
  162 + unsigned char pkdr;
  163 + unsigned char reserved_k;
  164 + unsigned char pldr;
  165 + unsigned char reserved_l;
  166 + unsigned char pmdr;
  167 + unsigned char reserved_m;
  168 + unsigned char pndr;
  169 + unsigned char reserved_n;
  170 + unsigned char podr;
  171 + unsigned char reserved_o;
  172 + unsigned char ppdr;
  173 + unsigned char reserved_p;
  174 + unsigned char pqdr;
  175 + unsigned char reserved_q;
  176 + unsigned char prdr;
  177 + unsigned char reserved_r;
  178 + unsigned char psdr;
  179 + unsigned char reserved_s;
  180 + unsigned char ptdr;
  181 + unsigned char reserved_t;
  182 + unsigned char pudr;
  183 + unsigned char reserved_u;
  184 + unsigned char pvdr;
  185 + unsigned char reserved_v;
  186 + unsigned char pwdr;
  187 + unsigned char reserved_w;
  188 + unsigned char pxdr;
  189 + unsigned char reserved_x;
  190 + unsigned char pydr;
  191 + unsigned char reserved_y;
  192 + unsigned char pzdr;
  193 + unsigned char reserved_z;
  194 + unsigned short ncer;
  195 + unsigned short ncmcr;
  196 + unsigned short nccsr;
  197 + unsigned char reserved2[2];
  198 + unsigned short psel0; /* +0x70 */
  199 + unsigned short psel1;
  200 + unsigned short psel2;
  201 + unsigned short psel3;
  202 + unsigned short psel4;
  203 + unsigned short psel5;
  204 + unsigned short psel6;
  205 + unsigned short reserved3[2];
  206 + unsigned short psel7;
  207 +};
  208 +#define GPIO_BASE ((struct gpio_regs *)0xffec0000)
  209 +
  210 +#endif /* ifndef __ASSEMBLY__ */
  211 +#endif /* _ASM_CPU_SH7752_H_ */
board/renesas/sh7752evb/Makefile
Diff comments   View file @ 1a2621b
  1 +#
  2 +# Copyright (C) 2012 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
  3 +#
  4 +# This program is free software; you can redistribute it and/or
  5 +# modify it under the terms of the GNU General Public License as
  6 +# published by the Free Software Foundation; either version 2 of
  7 +# the License, or (at your option) any later version.
  8 +#
  9 +# This program is distributed in the hope that it will be useful,
  10 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12 +# GNU General Public License for more details.
  13 +#
  14 +# You should have received a copy of the GNU General Public License
  15 +# along with this program; if not, write to the Free Software
  16 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17 +# MA 02111-1307 USA
  18 +
  19 +include $(TOPDIR)/config.mk
  20 +
  21 +LIB = $(obj)lib$(BOARD).o
  22 +
  23 +COBJS := sh7752evb.o spi-boot.o
  24 +SOBJS := lowlevel_init.o
  25 +
  26 +$(LIB): $(obj).depend $(COBJS) $(SOBJS)
  27 + $(call cmd_link_o_target, $(COBJS) $(SOBJS))
  28 +
  29 +#########################################################################
  30 +
  31 +# defines $(obj).depend target
  32 +include $(SRCTREE)/rules.mk
  33 +
  34 +sinclude $(obj).depend
  35 +
  36 +#########################################################################
board/renesas/sh7752evb/lowlevel_init.S
Diff comments   View file @ 1a2621b
  1 +/*
  2 + * Copyright (C) 2012 Renesas Solutions Corp.
  3 + *
  4 + * This program is free software; you can redistribute it and/or
  5 + * modify it under the terms of the GNU General Public License as
  6 + * published by the Free Software Foundation; either version 2 of
  7 + * the License, or (at your option) any later version.
  8 + *
  9 + * This program is distributed in the hope that it will be useful,
  10 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12 + * GNU General Public License for more details.
  13 + *
  14 + * You should have received a copy of the GNU General Public License
  15 + * along with this program; if not, write to the Free Software
  16 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17 + * MA 02111-1307 USA
  18 + */
  19 +
  20 +#include <config.h>
  21 +#include <version.h>
  22 +#include <asm/processor.h>
  23 +#include <asm/macro.h>
  24 +
  25 +.macro or32, addr, data
  26 + mov.l \addr, r1
  27 + mov.l \data, r0
  28 + mov.l @r1, r2
  29 + or r2, r0
  30 + mov.l r0, @r1
  31 +.endm
  32 +
  33 +.macro wait_DBCMD
  34 + mov.l DBWAIT_A, r0
  35 + mov.l @r0, r1
  36 +.endm
  37 +
  38 + .global lowlevel_init
  39 + .section .spiboot1.text
  40 + .align 2
  41 +
  42 +lowlevel_init:
  43 + /*------- GPIO -------*/
  44 + write16 PDCR_A, PDCR_D ! SPI0
  45 + write16 PGCR_A, PGCR_D ! SPI0, GETHER MDIO gate(PTG1)
  46 + write16 PJCR_A, PJCR_D ! SCIF4
  47 + write16 PTCR_A, PTCR_D ! STATUS
  48 + write16 PSEL1_A, PSEL1_D ! SPI0
  49 + write16 PSEL2_A, PSEL2_D ! SPI0
  50 + write16 PSEL5_A, PSEL5_D ! STATUS
  51 +
  52 + bra exit_gpio
  53 + nop
  54 +
  55 + .align 2
  56 +
  57 +/*------- GPIO -------*/
  58 +PDCR_A: .long 0xffec0006
  59 +PGCR_A: .long 0xffec000c
  60 +PJCR_A: .long 0xffec0012
  61 +PTCR_A: .long 0xffec0026
  62 +PSEL1_A: .long 0xffec0072
  63 +PSEL2_A: .long 0xffec0074
  64 +PSEL5_A: .long 0xffec007a
  65 +
  66 +PDCR_D: .long 0x0000
  67 +PGCR_D: .long 0x0004
  68 +PJCR_D: .long 0x0000
  69 +PTCR_D: .long 0x0000
  70 +PSEL1_D: .long 0x0000
  71 +PSEL2_D: .long 0x3000
  72 +PSEL5_D: .long 0x0ffc
  73 +
  74 + .align 2
  75 +
  76 +exit_gpio:
  77 + mov #0, r14
  78 + mova 2f, r0
  79 + mov.l PC_MASK, r1
  80 + tst r0, r1
  81 + bf 2f
  82 +
  83 + bra exit_pmb
  84 + nop
  85 +
  86 + .align 2
  87 +
  88 +/* If CPU runs on SDRAM (PC=0x5???????) or not. */
  89 +PC_MASK: .long 0x20000000
  90 +
  91 +2:
  92 + mov #1, r14
  93 +
  94 + mov.l EXPEVT_A, r0
  95 + mov.l @r0, r0
  96 + mov.l EXPEVT_POWER_ON_RESET, r1
  97 + cmp/eq r0, r1
  98 + bt 1f
  99 +
  100 + /*
  101 + * If EXPEVT value is manual reset or tlb multipul-hit,
  102 + * initialization of DDR3IF is not necessary.
  103 + */
  104 + bra exit_ddr
  105 + nop
  106 +
  107 +1:
  108 + /*------- Reset -------*/
  109 + write32 MRSTCR0_A, MRSTCR0_D
  110 + write32 MRSTCR1_A, MRSTCR1_D
  111 +
  112 + /* For Core Reset */
  113 + mov.l DBACEN_A, r0
  114 + mov.l @r0, r0
  115 + cmp/eq #0, r0
  116 + bt 3f
  117 +
  118 + /*
  119 + * If DBACEN == 1(DBSC was already enabled), we have to avoid the
  120 + * initialization of DDR3-SDRAM.
  121 + */
  122 + bra exit_ddr
  123 + nop
  124 +
  125 +3:
  126 + /*------- DDR3IF -------*/
  127 + /* oscillation stabilization time */
  128 + wait_timer WAIT_OSC_TIME
  129 +
  130 + /* step 3 */
  131 + write32 DBCMD_A, DBCMD_RSTL_VAL
  132 + wait_timer WAIT_30US
  133 +
  134 + /* step 4 */
  135 + write32 DBCMD_A, DBCMD_PDEN_VAL
  136 +
  137 + /* step 5 */
  138 + write32 DBKIND_A, DBKIND_D
  139 +
  140 + /* step 6 */
  141 + write32 DBCONF_A, DBCONF_D
  142 + write32 DBTR0_A, DBTR0_D
  143 + write32 DBTR1_A, DBTR1_D
  144 + write32 DBTR2_A, DBTR2_D
  145 + write32 DBTR3_A, DBTR3_D
  146 + write32 DBTR4_A, DBTR4_D
  147 + write32 DBTR5_A, DBTR5_D
  148 + write32 DBTR6_A, DBTR6_D
  149 + write32 DBTR7_A, DBTR7_D
  150 + write32 DBTR8_A, DBTR8_D
  151 + write32 DBTR9_A, DBTR9_D
  152 + write32 DBTR10_A, DBTR10_D
  153 + write32 DBTR11_A, DBTR11_D
  154 + write32 DBTR12_A, DBTR12_D
  155 + write32 DBTR13_A, DBTR13_D
  156 + write32 DBTR14_A, DBTR14_D
  157 + write32 DBTR15_A, DBTR15_D
  158 + write32 DBTR16_A, DBTR16_D
  159 + write32 DBTR17_A, DBTR17_D
  160 + write32 DBTR18_A, DBTR18_D
  161 + write32 DBTR19_A, DBTR19_D
  162 + write32 DBRNK0_A, DBRNK0_D
  163 +
  164 + /* step 7 */
  165 + write32 DBPDCNT3_A, DBPDCNT3_D
  166 +
  167 + /* step 8 */
  168 + write32 DBPDCNT1_A, DBPDCNT1_D
  169 + write32 DBPDCNT2_A, DBPDCNT2_D
  170 + write32 DBPDLCK_A, DBPDLCK_D
  171 + write32 DBPDRGA_A, DBPDRGA_D
  172 + write32 DBPDRGD_A, DBPDRGD_D
  173 +
  174 + /* step 9 */
  175 + wait_timer WAIT_30US
  176 +
  177 + /* step 10 */
  178 + write32 DBPDCNT0_A, DBPDCNT0_D
  179 +
  180 + /* step 11 */
  181 + wait_timer WAIT_30US
  182 + wait_timer WAIT_30US
  183 +
  184 + /* step 12 */
  185 + write32 DBCMD_A, DBCMD_WAIT_VAL
  186 + wait_DBCMD
  187 +
  188 + /* step 13 */
  189 + write32 DBCMD_A, DBCMD_RSTH_VAL
  190 + wait_DBCMD
  191 +
  192 + /* step 14 */
  193 + write32 DBCMD_A, DBCMD_WAIT_VAL
  194 + write32 DBCMD_A, DBCMD_WAIT_VAL
  195 + write32 DBCMD_A, DBCMD_WAIT_VAL
  196 + write32 DBCMD_A, DBCMD_WAIT_VAL
  197 +
  198 + /* step 15 */
  199 + write32 DBCMD_A, DBCMD_PDXT_VAL
  200 +
  201 + /* step 16 */
  202 + write32 DBCMD_A, DBCMD_MRS2_VAL
  203 +
  204 + /* step 17 */
  205 + write32 DBCMD_A, DBCMD_MRS3_VAL
  206 +
  207 + /* step 18 */
  208 + write32 DBCMD_A, DBCMD_MRS1_VAL
  209 +
  210 + /* step 19 */
  211 + write32 DBCMD_A, DBCMD_MRS0_VAL
  212 +
  213 + /* step 20 */
  214 + write32 DBCMD_A, DBCMD_ZQCL_VAL
  215 +
  216 + write32 DBCMD_A, DBCMD_REF_VAL
  217 + write32 DBCMD_A, DBCMD_REF_VAL
  218 + wait_DBCMD
  219 +
  220 + /* step 21 */
  221 + write32 DBADJ0_A, DBADJ0_D
  222 + write32 DBADJ1_A, DBADJ1_D
  223 + write32 DBADJ2_A, DBADJ2_D
  224 +
  225 + /* step 22 */
  226 + write32 DBRFCNF0_A, DBRFCNF0_D
  227 + write32 DBRFCNF1_A, DBRFCNF1_D
  228 + write32 DBRFCNF2_A, DBRFCNF2_D
  229 +
  230 + /* step 23 */
  231 + write32 DBCALCNF_A, DBCALCNF_D
  232 +
  233 + /* step 24 */
  234 + write32 DBRFEN_A, DBRFEN_D
  235 + write32 DBCMD_A, DBCMD_SRXT_VAL
  236 +
  237 + /* step 25 */
  238 + write32 DBACEN_A, DBACEN_D
  239 +
  240 + /* step 26 */
  241 + wait_DBCMD
  242 +
  243 + bra exit_ddr
  244 + nop
  245 +
  246 + .align 2
  247 +
  248 +EXPEVT_A: .long 0xff000024
  249 +EXPEVT_POWER_ON_RESET: .long 0x00000000
  250 +
  251 +/*------- Reset -------*/
  252 +MRSTCR0_A: .long 0xffd50030
  253 +MRSTCR0_D: .long 0xfe1ffe7f
  254 +MRSTCR1_A: .long 0xffd50034
  255 +MRSTCR1_D: .long 0xfff3ffff
  256 +
  257 +/*------- DDR3IF -------*/
  258 +DBCMD_A: .long 0xfe800018
  259 +DBKIND_A: .long 0xfe800020
  260 +DBCONF_A: .long 0xfe800024
  261 +DBTR0_A: .long 0xfe800040
  262 +DBTR1_A: .long 0xfe800044
  263 +DBTR2_A: .long 0xfe800048
  264 +DBTR3_A: .long 0xfe800050
  265 +DBTR4_A: .long 0xfe800054
  266 +DBTR5_A: .long 0xfe800058
  267 +DBTR6_A: .long 0xfe80005c
  268 +DBTR7_A: .long 0xfe800060
  269 +DBTR8_A: .long 0xfe800064
  270 +DBTR9_A: .long 0xfe800068
  271 +DBTR10_A: .long 0xfe80006c
  272 +DBTR11_A: .long 0xfe800070
  273 +DBTR12_A: .long 0xfe800074
  274 +DBTR13_A: .long 0xfe800078
  275 +DBTR14_A: .long 0xfe80007c
  276 +DBTR15_A: .long 0xfe800080
  277 +DBTR16_A: .long 0xfe800084
  278 +DBTR17_A: .long 0xfe800088
  279 +DBTR18_A: .long 0xfe80008c
  280 +DBTR19_A: .long 0xfe800090
  281 +DBRNK0_A: .long 0xfe800100
  282 +DBPDCNT0_A: .long 0xfe800200
  283 +DBPDCNT1_A: .long 0xfe800204
  284 +DBPDCNT2_A: .long 0xfe800208
  285 +DBPDCNT3_A: .long 0xfe80020c
  286 +DBPDLCK_A: .long 0xfe800280
  287 +DBPDRGA_A: .long 0xfe800290
  288 +DBPDRGD_A: .long 0xfe8002a0
  289 +DBADJ0_A: .long 0xfe8000c0
  290 +DBADJ1_A: .long 0xfe8000c4
  291 +DBADJ2_A: .long 0xfe8000c8
  292 +DBRFCNF0_A: .long 0xfe8000e0
  293 +DBRFCNF1_A: .long 0xfe8000e4
  294 +DBRFCNF2_A: .long 0xfe8000e8
  295 +DBCALCNF_A: .long 0xfe8000f4
  296 +DBRFEN_A: .long 0xfe800014
  297 +DBACEN_A: .long 0xfe800010
  298 +DBWAIT_A: .long 0xfe80001c
  299 +
  300 +WAIT_OSC_TIME: .long 6000
  301 +WAIT_30US: .long 13333
  302 +
  303 +DBCMD_RSTL_VAL: .long 0x20000000
  304 +DBCMD_PDEN_VAL: .long 0x1000d73c
  305 +DBCMD_WAIT_VAL: .long 0x0000d73c
  306 +DBCMD_RSTH_VAL: .long 0x2100d73c
  307 +DBCMD_PDXT_VAL: .long 0x110000c8
  308 +DBCMD_MRS0_VAL: .long 0x28000930
  309 +DBCMD_MRS1_VAL: .long 0x29000004
  310 +DBCMD_MRS2_VAL: .long 0x2a000008
  311 +DBCMD_MRS3_VAL: .long 0x2b000000
  312 +DBCMD_ZQCL_VAL: .long 0x03000200
  313 +DBCMD_REF_VAL: .long 0x0c000000
  314 +DBCMD_SRXT_VAL: .long 0x19000000
  315 +DBKIND_D: .long 0x00000007
  316 +DBCONF_D: .long 0x0f030a01
  317 +DBTR0_D: .long 0x00000007
  318 +DBTR1_D: .long 0x00000006
  319 +DBTR2_D: .long 0x00000000
  320 +DBTR3_D: .long 0x00000007
  321 +DBTR4_D: .long 0x00070007
  322 +DBTR5_D: .long 0x0000001b
  323 +DBTR6_D: .long 0x00000014
  324 +DBTR7_D: .long 0x00000005
  325 +DBTR8_D: .long 0x00000015
  326 +DBTR9_D: .long 0x00000006
  327 +DBTR10_D: .long 0x00000008
  328 +DBTR11_D: .long 0x00000007
  329 +DBTR12_D: .long 0x0000000e
  330 +DBTR13_D: .long 0x00000056
  331 +DBTR14_D: .long 0x00000006
  332 +DBTR15_D: .long 0x00000004
  333 +DBTR16_D: .long 0x00150002
  334 +DBTR17_D: .long 0x000c0017
  335 +DBTR18_D: .long 0x00000200
  336 +DBTR19_D: .long 0x00000040
  337 +DBRNK0_D: .long 0x00000001
  338 +DBPDCNT0_D: .long 0x00000001
  339 +DBPDCNT1_D: .long 0x00000001
  340 +DBPDCNT2_D: .long 0x00000000
  341 +DBPDCNT3_D: .long 0x00004010
  342 +DBPDLCK_D: .long 0x0000a55a
  343 +DBPDRGA_D: .long 0x00000028
  344 +DBPDRGD_D: .long 0x00017100
  345 +
  346 +DBADJ0_D: .long 0x00000000
  347 +DBADJ1_D: .long 0x00000000
  348 +DBADJ2_D: .long 0x18061806
  349 +DBRFCNF0_D: .long 0x000001ff
  350 +DBRFCNF1_D: .long 0x08001000
  351 +DBRFCNF2_D: .long 0x00000000
  352 +DBCALCNF_D: .long 0x0000ffff
  353 +DBRFEN_D: .long 0x00000001
  354 +DBACEN_D: .long 0x00000001
  355 +
  356 + .align 2
  357 +exit_ddr:
  358 +#if defined(CONFIG_SH_32BIT)
  359 + /*------- set PMB -------*/
  360 + write32 PASCR_A, PASCR_29BIT_D
  361 + write32 MMUCR_A, MMUCR_D
  362 +
  363 + /*****************************************************************
  364 + * ent virt phys v sz c wt
  365 + * 0 0xa0000000 0x00000000 1 128M 0 1
  366 + * 1 0xa8000000 0x48000000 1 128M 0 1
  367 + * 5 0x88000000 0x48000000 1 128M 1 1
  368 + */
  369 + write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D
  370 + write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D
  371 + write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
  372 + write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
  373 + write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
  374 + write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
  375 +
  376 + write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D
  377 + write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D
  378 + write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D
  379 + write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D
  380 + write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D
  381 + write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D
  382 + write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D
  383 + write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D
  384 + write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D
  385 + write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D
  386 + write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D
  387 + write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D
  388 + write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D
  389 +
  390 + write32 PASCR_A, PASCR_INIT
  391 + mov.l DUMMY_ADDR, r0
  392 + icbi @r0
  393 +#endif /* if defined(CONFIG_SH_32BIT) */
  394 +
  395 +exit_pmb:
  396 + /* CPU is running on ILRAM? */
  397 + mov r14, r0
  398 + tst #1, r0
  399 + bt 1f
  400 +
  401 + mov.l _stack_ilram, r15
  402 + mov.l _spiboot_main, r0
  403 +100: bsrf r0
  404 + nop
  405 +
  406 + .align 2
  407 +_spiboot_main: .long (spiboot_main - (100b + 4))
  408 +_stack_ilram: .long 0xe5204000
  409 +
  410 +1:
  411 + write32 CCR_A, CCR_D
  412 +
  413 + rts
  414 + nop
  415 +
  416 + .align 2
  417 +
  418 +#if defined(CONFIG_SH_32BIT)
  419 +/*------- set PMB -------*/
  420 +PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0)
  421 +PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1)
  422 +PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5)
  423 +PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2)
  424 +PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3)
  425 +PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4)
  426 +PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6)
  427 +PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7)
  428 +PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8)
  429 +PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9)
  430 +PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10)
  431 +PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11)
  432 +PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12)
  433 +PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13)
  434 +PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14)
  435 +PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15)
  436 +
  437 +PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0)
  438 +PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
  439 +PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
  440 +PMB_ADDR_NOT_USE_D: .long 0x00000000
  441 +
  442 +PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0)
  443 +PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1)
  444 +PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5)
  445 +
  446 +/* ppn ub v s1 s0 c wt */
  447 +PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
  448 +PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
  449 +PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
  450 +
  451 +PASCR_A: .long 0xff000070
  452 +DUMMY_ADDR: .long 0xa0000000
  453 +PASCR_29BIT_D: .long 0x00000000
  454 +PASCR_INIT: .long 0x80000080
  455 +MMUCR_A: .long 0xff000010
  456 +MMUCR_D: .long 0x00000004 /* clear ITLB */
  457 +#endif /* CONFIG_SH_32BIT */
  458 +
  459 +CCR_A: .long CCR
  460 +CCR_D: .long CCR_CACHE_INIT
board/renesas/sh7752evb/sh7752evb.c
Diff comments   View file @ 1a2621b
  1 +/*
  2 + * Copyright (C) 2012 Renesas Solutions Corp.
  3 + *
  4 + * See file CREDITS for list of people who contributed to this
  5 + * project.
  6 + *
  7 + * This program is free software; you can redistribute it and/or
  8 + * modify it under the terms of the GNU General Public License as
  9 + * published by the Free Software Foundation; either version 2 of
  10 + * the License, or (at your option) any later version.
  11 + *
  12 + * This program is distributed in the hope that it will be useful,
  13 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * GNU General Public License for more details.
  16 + *
  17 + * You should have received a copy of the GNU General Public License
  18 + * along with this program; if not, write to the Free Software
  19 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 + * MA 02111-1307 USA
  21 + */
  22 +
  23 +#include <common.h>
  24 +#include <malloc.h>
  25 +#include <asm/processor.h>
  26 +#include <asm/io.h>
  27 +#include <asm/mmc.h>
  28 +#include <spi_flash.h>
  29 +
  30 +int checkboard(void)
  31 +{
  32 + puts("BOARD: SH7752 evaluation board (R0P7752C00000RZ)\n");
  33 +
  34 + return 0;
  35 +}
  36 +
  37 +static void init_gpio(void)
  38 +{
  39 + struct gpio_regs *gpio = GPIO_BASE;
  40 + struct sermux_regs *sermux = SERMUX_BASE;
  41 +
  42 + /* GPIO */
  43 + writew(0x0000, &gpio->pacr); /* GETHER */
  44 + writew(0x0001, &gpio->pbcr); /* INTC */
  45 + writew(0x0000, &gpio->pccr); /* PWMU, INTC */
  46 + writew(0xeaff, &gpio->pecr); /* GPIO */
  47 + writew(0x0000, &gpio->pfcr); /* WDT */
  48 + writew(0x0000, &gpio->phcr); /* SPI1 */
  49 + writew(0x0000, &gpio->picr); /* SDHI */
  50 + writew(0x0003, &gpio->pkcr); /* SerMux */
  51 + writew(0x0000, &gpio->plcr); /* SerMux */
  52 + writew(0x0000, &gpio->pmcr); /* RIIC */
  53 + writew(0x0000, &gpio->pncr); /* USB, SGPIO */
  54 + writew(0x0000, &gpio->pocr); /* SGPIO */
  55 + writew(0xd555, &gpio->pqcr); /* GPIO */
  56 + writew(0x0000, &gpio->prcr); /* RIIC */
  57 + writew(0x0000, &gpio->pscr); /* RIIC */
  58 + writeb(0x00, &gpio->pudr);
  59 + writew(0x5555, &gpio->pucr); /* Debug LED */
  60 + writew(0x0000, &gpio->pvcr); /* RSPI */
  61 + writew(0x0000, &gpio->pwcr); /* EVC */
  62 + writew(0x0000, &gpio->pxcr); /* LBSC */
  63 + writew(0x0000, &gpio->pycr); /* LBSC */
  64 + writew(0x0000, &gpio->pzcr); /* eMMC */
  65 + writew(0xfe00, &gpio->psel0);
  66 + writew(0xff00, &gpio->psel3);
  67 + writew(0x771f, &gpio->psel4);
  68 + writew(0x00ff, &gpio->psel6);
  69 + writew(0xfc00, &gpio->psel7);
  70 +
  71 + writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */
  72 +}
  73 +
  74 +static void init_usb_phy(void)
  75 +{
  76 + struct usb_common_regs *common0 = USB0_COMMON_BASE;
  77 + struct usb_common_regs *common1 = USB1_COMMON_BASE;
  78 + struct usb0_phy_regs *phy = USB0_PHY_BASE;
  79 + struct usb1_port_regs *port = USB1_PORT_BASE;
  80 + struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
  81 +
  82 + writew(0x0100, &phy->reset); /* set reset */
  83 + /* port0 = USB0, port1 = USB1 */
  84 + writew(0x0002, &phy->portsel);
  85 + writel(0x0001, &port->port1sel); /* port1 = Host */
  86 + writew(0x0111, &phy->reset); /* clear reset */
  87 +
  88 + writew(0x4000, &common0->suspmode);
  89 + writew(0x4000, &common1->suspmode);
  90 +
  91 +#if defined(__LITTLE_ENDIAN)
  92 + writel(0x00000000, &align->ehcidatac);
  93 + writel(0x00000000, &align->ohcidatac);
  94 +#endif
  95 +}
  96 +
  97 +static void init_gether_mdio(void)
  98 +{
  99 + struct gpio_regs *gpio = GPIO_BASE;
  100 +
  101 + writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);
  102 + writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */
  103 +}
  104 +
  105 +static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
  106 +{
  107 + struct ether_mac_regs *ether;
  108 + unsigned char mac[6];
  109 + unsigned long val;
  110 +
  111 + eth_parse_enetaddr(mac_string, mac);
  112 +
  113 + if (!channel)
  114 + ether = GETHER0_MAC_BASE;
  115 + else
  116 + ether = GETHER1_MAC_BASE;
  117 +
  118 + val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
  119 + writel(val, &ether->mahr);
  120 + val = (mac[4] << 8) | mac[5];
  121 + writel(val, &ether->malr);
  122 +}
  123 +
  124 +/*****************************************************************
  125 + * This PMB must be set on this timing. The lowlevel_init is run on
  126 + * Area 0(phys 0x00000000), so we have to map it.
  127 + *
  128 + * The new PMB table is following:
  129 + * ent virt phys v sz c wt
  130 + * 0 0xa0000000 0x40000000 1 128M 0 1
  131 + * 1 0xa8000000 0x48000000 1 128M 0 1
  132 + * 2 0xb0000000 0x50000000 1 128M 0 1
  133 + * 3 0xb8000000 0x58000000 1 128M 0 1
  134 + * 4 0x80000000 0x40000000 1 128M 1 1
  135 + * 5 0x88000000 0x48000000 1 128M 1 1
  136 + * 6 0x90000000 0x50000000 1 128M 1 1
  137 + * 7 0x98000000 0x58000000 1 128M 1 1
  138 + */
  139 +static void set_pmb_on_board_init(void)
  140 +{
  141 + struct mmu_regs *mmu = MMU_BASE;
  142 +
  143 + /* clear ITLB */
  144 + writel(0x00000004, &mmu->mmucr);
  145 +
  146 + /* delete PMB for SPIBOOT */
  147 + writel(0, PMB_ADDR_BASE(0));
  148 + writel(0, PMB_DATA_BASE(0));
  149 +
  150 + /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
  151 + /* ppn ub v s1 s0 c wt */
  152 + writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
  153 + writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
  154 + writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
  155 + writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
  156 + writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
  157 + writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
  158 + writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
  159 + writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
  160 + writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
  161 + writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
  162 + writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
  163 + writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
  164 +}
  165 +
  166 +int board_init(void)
  167 +{
  168 + init_gpio();
  169 + set_pmb_on_board_init();
  170 +
  171 + init_usb_phy();
  172 + init_gether_mdio();
  173 +
  174 + return 0;
  175 +}
  176 +
  177 +int dram_init(void)
  178 +{
  179 + DECLARE_GLOBAL_DATA_PTR;
  180 +
  181 + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
  182 + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
  183 + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
  184 +
  185 + return 0;
  186 +}
  187 +
  188 +int board_mmc_init(bd_t *bis)
  189 +{
  190 + struct gpio_regs *gpio = GPIO_BASE;
  191 +
  192 + writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);
  193 + writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
  194 + udelay(1);
  195 + writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */
  196 + udelay(200);
  197 +
  198 + return mmcif_mmc_init();
  199 +}
  200 +
  201 +static int get_sh_eth_mac_raw(unsigned char *buf, int size)
  202 +{
  203 + struct spi_flash *spi;
  204 + int ret;
  205 +
  206 + spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
  207 + if (spi == NULL) {
  208 + printf("%s: spi_flash probe failed.\n", __func__);
  209 + return 1;
  210 + }
  211 +
  212 + ret = spi_flash_read(spi, SH7752EVB_ETHERNET_MAC_BASE, size, buf);
  213 + if (ret) {
  214 + printf("%s: spi_flash read failed.\n", __func__);
  215 + spi_flash_free(spi);
  216 + return 1;
  217 + }
  218 + spi_flash_free(spi);
  219 +
  220 + return 0;
  221 +}
  222 +
  223 +static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
  224 +{
  225 + memcpy(mac_string, &buf[channel * (SH7752EVB_ETHERNET_MAC_SIZE + 1)],
  226 + SH7752EVB_ETHERNET_MAC_SIZE);
  227 + mac_string[SH7752EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
  228 +
  229 + return 0;
  230 +}
  231 +
  232 +static void init_ethernet_mac(void)
  233 +{
  234 + char mac_string[64];
  235 + char env_string[64];
  236 + int i;
  237 + unsigned char *buf;
  238 +
  239 + buf = malloc(256);
  240 + if (!buf) {
  241 + printf("%s: malloc failed.\n", __func__);
  242 + return;
  243 + }
  244 + get_sh_eth_mac_raw(buf, 256);
  245 +
  246 + /* Gigabit Ethernet */
  247 + for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
  248 + get_sh_eth_mac(i, mac_string, buf);
  249 + if (i == 0)
  250 + setenv("ethaddr", mac_string);
  251 + else {
  252 + sprintf(env_string, "eth%daddr", i);
  253 + setenv(env_string, mac_string);
  254 + }
  255 + set_mac_to_sh_giga_eth_register(i, mac_string);
  256 + }
  257 +
  258 + free(buf);
  259 +}
  260 +
  261 +int board_late_init(void)
  262 +{
  263 + init_ethernet_mac();
  264 +
  265 + return 0;
  266 +}
  267 +
  268 +int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  269 +{
  270 + int i, ret;
  271 + char mac_string[256];
  272 + struct spi_flash *spi;
  273 + unsigned char *buf;
  274 +
  275 + if (argc != 3) {
  276 + buf = malloc(256);
  277 + if (!buf) {
  278 + printf("%s: malloc failed.\n", __func__);
  279 + return 1;
  280 + }
  281 +
  282 + get_sh_eth_mac_raw(buf, 256);
  283 +
  284 + /* print current MAC address */
  285 + for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
  286 + get_sh_eth_mac(i, mac_string, buf);
  287 + printf("GETHERC ch%d = %s\n", i, mac_string);
  288 + }
  289 + free(buf);
  290 + return 0;
  291 + }
  292 +
  293 + /* new setting */
  294 + memset(mac_string, 0xff, sizeof(mac_string));
  295 + sprintf(mac_string, "%s\t%s",
  296 + argv[1], argv[2]);
  297 +
  298 + /* write MAC data to SPI rom */
  299 + spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
  300 + if (!spi) {
  301 + printf("%s: spi_flash probe failed.\n", __func__);
  302 + return 1;
  303 + }
  304 +
  305 + ret = spi_flash_erase(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
  306 + SH7752EVB_SPI_SECTOR_SIZE);
  307 + if (ret) {
  308 + printf("%s: spi_flash erase failed.\n", __func__);
  309 + return 1;
  310 + }
  311 +
  312 + ret = spi_flash_write(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
  313 + sizeof(mac_string), mac_string);
  314 + if (ret) {
  315 + printf("%s: spi_flash write failed.\n", __func__);
  316 + spi_flash_free(spi);
  317 + return 1;
  318 + }
  319 + spi_flash_free(spi);
  320 +
  321 + puts("The writing of the MAC address to SPI ROM was completed.\n");
  322 +
  323 + return 0;
  324 +}
  325 +
  326 +U_BOOT_CMD(
  327 + write_mac, 3, 1, do_write_mac,
  328 + "write MAC address for GETHERC",
  329 + "[GETHERC ch0] [GETHERC ch1]\n"
  330 +);
board/renesas/sh7752evb/spi-boot.c
Diff comments   View file @ 1a2621b
  1 +/*
  2 + * Copyright (C) 2012 Renesas Solutions Corp.
  3 + *
  4 + * This file is subject to the terms and conditions of the GNU Lesser
  5 + * General Public License. See the file "COPYING.LIB" in the main
  6 + * directory of this archive for more details.
  7 + */
  8 +
  9 +#include <common.h>
  10 +
  11 +#define CONFIG_RAM_BOOT_PHYS CONFIG_SYS_TEXT_BASE
  12 +#define CONFIG_SPI_ADDR 0x00000000
  13 +#define CONFIG_SPI_LENGTH CONFIG_SYS_MONITOR_LEN
  14 +#define CONFIG_RAM_BOOT CONFIG_SYS_TEXT_BASE
  15 +
  16 +#define SPIWDMADR 0xFE001018
  17 +#define SPIWDMCNTR 0xFE001020
  18 +#define SPIDMCOR 0xFE001028
  19 +#define SPIDMINTSR 0xFE001188
  20 +#define SPIDMINTMR 0xFE001190
  21 +
  22 +#define SPIDMINTSR_DMEND 0x00000004
  23 +
  24 +#define TBR 0xFE002000
  25 +#define RBR 0xFE002000
  26 +
  27 +#define CR1 0xFE002008
  28 +#define CR2 0xFE002010
  29 +#define CR3 0xFE002018
  30 +#define CR4 0xFE002020
  31 +
  32 +/* CR1 */
  33 +#define SPI_TBE 0x80
  34 +#define SPI_TBF 0x40
  35 +#define SPI_RBE 0x20
  36 +#define SPI_RBF 0x10
  37 +#define SPI_PFONRD 0x08
  38 +#define SPI_SSDB 0x04
  39 +#define SPI_SSD 0x02
  40 +#define SPI_SSA 0x01
  41 +
  42 +/* CR2 */
  43 +#define SPI_RSTF 0x80
  44 +#define SPI_LOOPBK 0x40
  45 +#define SPI_CPOL 0x20
  46 +#define SPI_CPHA 0x10
  47 +#define SPI_L1M0 0x08
  48 +
  49 +/* CR4 */
  50 +#define SPI_TBEI 0x80
  51 +#define SPI_TBFI 0x40
  52 +#define SPI_RBEI 0x20
  53 +#define SPI_RBFI 0x10
  54 +#define SPI_SpiS0 0x02
  55 +#define SPI_SSS 0x01
  56 +
  57 +#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val
  58 +#define spi_read(addr) (*(volatile unsigned long *)(addr))
  59 +
  60 +/* M25P80 */
  61 +#define M25_READ 0x03
  62 +
  63 +#define __uses_spiboot2 __attribute__((section(".spiboot2.text")))
  64 +static void __uses_spiboot2 spi_reset(void)
  65 +{
  66 + int timeout = 0x00100000;
  67 +
  68 + /* Make sure the last transaction is finalized */
  69 + spi_write(0x00, CR3);
  70 + spi_write(0x02, CR1);
  71 + while (!(spi_read(CR4) & SPI_SpiS0)) {
  72 + if (timeout-- < 0)
  73 + break;
  74 + }
  75 + spi_write(0x00, CR1);
  76 +
  77 + spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */
  78 + spi_write(spi_read(CR2) & ~SPI_RSTF, CR2);
  79 +
  80 + spi_write(0, SPIDMCOR);
  81 +}
  82 +
  83 +static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr,
  84 + unsigned long len)
  85 +{
  86 + spi_write(M25_READ, TBR);
  87 + spi_write((addr >> 16) & 0xFF, TBR);
  88 + spi_write((addr >> 8) & 0xFF, TBR);
  89 + spi_write(addr & 0xFF, TBR);
  90 +
  91 + spi_write(SPIDMINTSR_DMEND, SPIDMINTSR);
  92 + spi_write((unsigned long)buf, SPIWDMADR);
  93 + spi_write(len & 0xFFFFFFE0, SPIWDMCNTR);
  94 + spi_write(1, SPIDMCOR);
  95 +
  96 + spi_write(0xff, CR3);
  97 + spi_write(spi_read(CR1) | SPI_SSDB, CR1);
  98 + spi_write(spi_read(CR1) | SPI_SSA, CR1);
  99 +
  100 + while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND))
  101 + ;
  102 +
  103 + /* Nagate SP0-SS0 */
  104 + spi_write(0, CR1);
  105 +}
  106 +
  107 +void __uses_spiboot2 spiboot_main(void)
  108 +{
  109 + void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE;
  110 +
  111 + spi_reset();
  112 + spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR,
  113 + CONFIG_SPI_LENGTH);
  114 +
  115 + _start();
  116 +}
board/renesas/sh7752evb/u-boot.lds
Diff comments   View file @ 1a2621b
  1 +/*
  2 + * Copyright (C) 2007
  3 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
  4 + *
  5 + * Copyright (C) 2012
  6 + * Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
  7 + *
  8 + * See file CREDITS for list of people who contributed to this
  9 + * project.
  10 + *
  11 + * This program is free software; you can redistribute it and/or
  12 + * modify it under the terms of the GNU General Public License as
  13 + * published by the Free Software Foundation; either version 2 of
  14 + * the License, or (at your option) any later version.
  15 + *
  16 + * This program is distributed in the hope that it will be useful,
  17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19 + * GNU General Public License for more details.
  20 + *
  21 + * You should have received a copy of the GNU General Public License
  22 + * along with this program; if not, write to the Free Software
  23 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 + * MA 02111-1307 USA
  25 + */
  26 +
  27 +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
  28 +OUTPUT_ARCH(sh)
  29 +ENTRY(_start)
  30 +
  31 +SECTIONS
  32 +{
  33 + /*
  34 + * entry and reloct_dst will be provided via ldflags
  35 + */
  36 + . = .;
  37 +
  38 + PROVIDE (_ftext = .);
  39 + PROVIDE (_fcode = .);
  40 + PROVIDE (_start = .);
  41 +
  42 + .text :
  43 + {
  44 + KEEP(arch/sh/cpu/sh4/start.o (.text))
  45 + *(.spiboot1.text)
  46 + *(.spiboot2.text)
  47 + . = ALIGN(8192);
  48 + common/env_embedded.o (.ppcenv)
  49 + . = ALIGN(8192);
  50 + common/env_embedded.o (.ppcenvr)
  51 + . = ALIGN(8192);
  52 + *(.text)
  53 + . = ALIGN(4);
  54 + } =0xFF
  55 + PROVIDE (_ecode = .);
  56 + .rodata :
  57 + {
  58 + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
  59 + . = ALIGN(4);
  60 + }
  61 + PROVIDE (_etext = .);
  62 +
  63 +
  64 + PROVIDE (_fdata = .);
  65 + .data :
  66 + {
  67 + *(.data)
  68 + . = ALIGN(4);
  69 + }
  70 + PROVIDE (_edata = .);
  71 +
  72 + PROVIDE (_fgot = .);
  73 + .got :
  74 + {
  75 + *(.got)
  76 + . = ALIGN(4);
  77 + }
  78 + PROVIDE (_egot = .);
  79 +
  80 + .u_boot_list : {
  81 + #include <u-boot.lst>
  82 + }
  83 +
  84 + PROVIDE (reloc_dst_end = .);
  85 + /* _reloc_dst_end = .; */
  86 +
  87 + PROVIDE (bss_start = .);
  88 + PROVIDE (__bss_start = .);
  89 + .bss (NOLOAD) :
  90 + {
  91 + *(.bss)
  92 + . = ALIGN(4);
  93 + }
  94 + PROVIDE (bss_end = .);
  95 +
  96 + PROVIDE (__bss_end__ = .);
  97 +}
... ... @@ -1089,6 +1089,7 @@
1089 1089 MigoR sh sh4 MigoR renesas -
1090 1090 r2dplus sh sh4 r2dplus renesas -
1091 1091 r7780mp sh sh4 r7780mp renesas -
  1092 +sh7752evb sh sh4 sh7752evb renesas -
1092 1093 sh7757lcr sh sh4 sh7757lcr renesas -
1093 1094 sh7763rdp sh sh4 sh7763rdp renesas -
1094 1095 sh7785lcr sh sh4 sh7785lcr renesas -
doc/README.sh7752evb
Diff comments   View file @ 1a2621b
  1 +========================================
  2 +Renesas R0P7752C00000RZ board
  3 +========================================
  4 +
  5 +This board specification:
  6 +=========================
  7 +
  8 +The R0P7752C00000RZ(board config name:sh7752evb) has the following device:
  9 +
  10 + - SH7752 (SH-4A)
  11 + - DDR3-SDRAM 512MB
  12 + - SPI ROM 8MB
  13 + - Gigabit Ethernet controllers
  14 + - eMMC 4GB
  15 +
  16 +
  17 +Configuration for This board:
  18 +=============================
  19 +
  20 +You can select the configuration as follows:
  21 +
  22 + - make sh7752evb_config
  23 +
  24 +
  25 +This board specific command:
  26 +============================
  27 +
  28 +This board has the following its specific command:
  29 +
  30 + - write_mac
  31 +
  32 +
  33 +1. write_mac
  34 +
  35 +You can write MAC address to SPI ROM.
  36 +
  37 + Usage 1) Write MAC address
  38 +
  39 + write_mac [GETHERC ch0] [GETHERC ch1]
  40 +
  41 + For example)
  42 + => write_mac 74:90:50:00:33:9e 74:90:50:00:33:9f
  43 + *) We have to input the command as a single line
  44 + (without carriage return)
  45 + *) We have to reset after input the command.
  46 +
  47 + Usage 2) Show current data
  48 +
  49 + write_mac
  50 +
  51 + For example)
  52 + => write_mac
  53 + GETHERC ch0 = 74:90:50:00:33:9e
  54 + GETHERC ch1 = 74:90:50:00:33:9f
  55 +
  56 +
  57 +Update SPI ROM:
  58 +============================
  59 +
  60 +1. Copy u-boot image to RAM area.
  61 +2. Probe SPI device.
  62 + => sf probe 0
  63 + SF: Detected MX25L6405D with page size 64KiB, total 8 MiB
  64 +3. Erase SPI ROM.
  65 + => sf erase 0 80000
  66 +4. Write u-boot image to SPI ROM.
  67 + => sf write 0x48000000 0 80000
include/configs/sh7752evb.h
Diff comments   View file @ 1a2621b
  1 +/*
  2 + * Configuation settings for the sh7752evb board
  3 + *
  4 + * Copyright (C) 2012 Renesas Solutions Corp.
  5 + *
  6 + * See file CREDITS for list of people who contributed to this
  7 + * project.
  8 + *
  9 + * This program is free software; you can redistribute it and/or
  10 + * modify it under the terms of the GNU General Public License as
  11 + * published by the Free Software Foundation; either version 2 of
  12 + * the License, or (at your option) any later version.
  13 + *
  14 + * This program is distributed in the hope that it will be useful,
  15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 + * GNU General Public License for more details.
  18 + *
  19 + * You should have received a copy of the GNU General Public License
  20 + * along with this program; if not, write to the Free Software
  21 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 + * MA 02111-1307 USA
  23 + */
  24 +
  25 +#ifndef __SH7752EVB_H
  26 +#define __SH7752EVB_H
  27 +
  28 +#undef DEBUG
  29 +#define CONFIG_SH 1
  30 +#define CONFIG_SH4A 1
  31 +#define CONFIG_SH_32BIT 1
  32 +#define CONFIG_CPU_SH7752 1
  33 +#define CONFIG_SH7752EVB 1
  34 +
  35 +#define CONFIG_SYS_TEXT_BASE 0x5ff80000
  36 +#define CONFIG_SYS_LDSCRIPT "board/renesas/sh7752evb/u-boot.lds"
  37 +
  38 +#define CONFIG_CMD_MEMORY
  39 +#define CONFIG_CMD_NET
  40 +#define CONFIG_CMD_MII
  41 +#define CONFIG_CMD_PING
  42 +#define CONFIG_CMD_NFS
  43 +#define CONFIG_CMD_DFL
  44 +#define CONFIG_CMD_SDRAM
  45 +#define CONFIG_CMD_SF
  46 +#define CONFIG_CMD_RUN
  47 +#define CONFIG_CMD_SAVEENV
  48 +#define CONFIG_CMD_MD5SUM
  49 +#define CONFIG_MD5
  50 +#define CONFIG_CMD_LOADS
  51 +#define CONFIG_CMD_MMC
  52 +#define CONFIG_CMD_EXT2
  53 +#define CONFIG_DOS_PARTITION
  54 +#define CONFIG_MAC_PARTITION
  55 +
  56 +#define CONFIG_BAUDRATE 115200
  57 +#define CONFIG_BOOTDELAY 3
  58 +#define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp"
  59 +
  60 +#define CONFIG_VERSION_VARIABLE
  61 +#undef CONFIG_SHOW_BOOT_PROGRESS
  62 +#define CONFIG_CMDLINE_EDITING
  63 +#define CONFIG_AUTO_COMPLETE
  64 +
  65 +/* MEMORY */
  66 +#define SH7752EVB_SDRAM_BASE (0x40000000)
  67 +#define SH7752EVB_SDRAM_SIZE (512 * 1024 * 1024)
  68 +
  69 +#define CONFIG_SYS_LONGHELP
  70 +#define CONFIG_SYS_PROMPT "=> "
  71 +#define CONFIG_SYS_CBSIZE 256
  72 +#define CONFIG_SYS_PBSIZE 256
  73 +#define CONFIG_SYS_MAXARGS 16
  74 +#define CONFIG_SYS_BARGSIZE 512
  75 +#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
  76 +
  77 +/* SCIF */
  78 +#define CONFIG_SCIF_CONSOLE 1
  79 +#define CONFIG_CONS_SCIF2 1
  80 +#undef CONFIG_SYS_CONSOLE_INFO_QUIET
  81 +#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
  82 +#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
  83 +
  84 +#define CONFIG_SYS_MEMTEST_START (SH7752EVB_SDRAM_BASE)
  85 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
  86 + 480 * 1024 * 1024)
  87 +#undef CONFIG_SYS_ALT_MEMTEST
  88 +#undef CONFIG_SYS_MEMTEST_SCRATCH
  89 +#undef CONFIG_SYS_LOADS_BAUD_CHANGE
  90 +
  91 +#define CONFIG_SYS_SDRAM_BASE (SH7752EVB_SDRAM_BASE)
  92 +#define CONFIG_SYS_SDRAM_SIZE (SH7752EVB_SDRAM_SIZE)
  93 +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
  94 + 128 * 1024 * 1024)
  95 +
  96 +#define CONFIG_SYS_MONITOR_BASE 0x00000000
  97 +#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
  98 +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  99 +#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
  100 +
  101 +/* FLASH */
  102 +#define CONFIG_SYS_NO_FLASH
  103 +
  104 +/* Ether */
  105 +#define CONFIG_SH_ETHER 1
  106 +#define CONFIG_SH_ETHER_USE_PORT 0
  107 +#define CONFIG_SH_ETHER_PHY_ADDR 18
  108 +#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
  109 +#define CONFIG_SH_ETHER_USE_GETHER 1
  110 +#define CONFIG_PHYLIB
  111 +#define CONFIG_BITBANGMII
  112 +#define CONFIG_BITBANGMII_MULTI
  113 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
  114 +#define CONFIG_PHY_VITESSE
  115 +
  116 +#define SH7752EVB_ETHERNET_MAC_BASE_SPI 0x00090000
  117 +#define SH7752EVB_SPI_SECTOR_SIZE (64 * 1024)
  118 +#define SH7752EVB_ETHERNET_MAC_BASE SH7752EVB_ETHERNET_MAC_BASE_SPI
  119 +#define SH7752EVB_ETHERNET_MAC_SIZE 17
  120 +#define SH7752EVB_ETHERNET_NUM_CH 2
  121 +#define CONFIG_BOARD_LATE_INIT
  122 +
  123 +/* SPI */
  124 +#define CONFIG_SH_SPI 1
  125 +#define CONFIG_SH_SPI_BASE 0xfe002000
  126 +#define CONFIG_SPI_FLASH
  127 +#define CONFIG_SPI_FLASH_STMICRO 1
  128 +#define CONFIG_SPI_FLASH_MACRONIX 1
  129 +
  130 +/* MMCIF */
  131 +#define CONFIG_MMC 1
  132 +#define CONFIG_GENERIC_MMC 1
  133 +#define CONFIG_SH_MMCIF 1
  134 +#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
  135 +#define CONFIG_SH_MMCIF_CLK 48000000
  136 +
  137 +/* ENV setting */
  138 +#define CONFIG_ENV_IS_EMBEDDED
  139 +#define CONFIG_ENV_IS_IN_SPI_FLASH
  140 +#define CONFIG_ENV_SECT_SIZE (64 * 1024)
  141 +#define CONFIG_ENV_ADDR (0x00080000)
  142 +#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
  143 +#define CONFIG_ENV_OVERWRITE 1
  144 +#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
  145 +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
  146 +#define CONFIG_EXTRA_ENV_SETTINGS \
  147 + "netboot=bootp; bootm\0"
  148 +
  149 +/* Board Clock */
  150 +#define CONFIG_SYS_CLK_FREQ 48000000
  151 +#define CONFIG_SYS_TMU_CLK_DIV 4
  152 +#define CONFIG_SYS_HZ 1000
  153 +#endif /* __SH7752EVB_H */