driver/ifc:Change accessor function to take care of endianness

IFC registers can be of type Little Endian or big Endian depending upon Freescale SoC. Here SoC defines the register type of IFC IP. So update acessor functions with common IFC acessor functions to take care both type of endianness. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: York Sun <yorksun@freescale.com>

driver/ifc:Change accessor function to take care of endianness
IFC registers can be of type Little Endian or big Endian depending upon Freescale SoC. Here SoC defines the register type of IFC IP. So update acessor functions with common IFC acessor functions to take care both type of endianness. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
Prabhakar Kushwaha · York Sun
1 parent 27c78e06f2
Showing 5 changed files with 190 additions and 164 deletions Side-by-side Diff
README
arch/powerpc/include/asm/config_mpc85xx.h
drivers/mtd/nand/fsl_ifc_nand.c
drivers/mtd/nand/fsl_ifc_spl.c
include/fsl_ifc.h
@@ -472,6 +472,12 @@
 		Board config to use DDR3. It can be enabled for SoCs with
 		Freescale DDR3 controllers.
  
+		CONFIG_SYS_FSL_IFC_BE
+		Defines the IFC controller register space as Big Endian
+
+		CONFIG_SYS_FSL_IFC_LE
+		Defines the IFC controller register space as Little Endian
+
 		CONFIG_SYS_FSL_PBL_PBI
 		It enables addition of RCW (Power on reset configuration) in built image.
 		Please refer doc/README.pblimage for more details
@@ -22,6 +22,9 @@
 #define FSL_DDR_VER_4_7	47
 #define FSL_DDR_VER_5_0	50
  
+/* IP endianness */
+#define CONFIG_SYS_FSL_IFC_BE
+
 /* Number of TLB CAM entries we have on FSL Book-E chips */
 #if defined(CONFIG_E500MC)
 #define CONFIG_SYS_NUM_TLBCAMS		64
@@ -230,8 +230,8 @@
 	ctrl->page = page_addr;
  
 	/* Program ROW0/COL0 */
-	out_be32(&ifc->ifc_nand.row0, page_addr);
-	out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
+	ifc_out32(&ifc->ifc_nand.row0, page_addr);
+	ifc_out32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
  
 	buf_num = page_addr & priv->bufnum_mask;
  
  
  
  
@@ -294,23 +294,23 @@
 	int i;
  
 	/* set the chip select for NAND Transaction */
-	out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
+	ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
  
 	/* start read/write seq */
-	out_be32(&ifc->ifc_nand.nandseq_strt,
-		 IFC_NAND_SEQ_STRT_FIR_STRT);
+	ifc_out32(&ifc->ifc_nand.nandseq_strt,
+		  IFC_NAND_SEQ_STRT_FIR_STRT);
  
 	/* wait for NAND Machine complete flag or timeout */
 	end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
  
 	while (end_tick > get_ticks()) {
-		ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat);
+		ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
  
 		if (ctrl->status & IFC_NAND_EVTER_STAT_OPC)
 			break;
 	}
  
-	out_be32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
+	ifc_out32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
  
 	if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER)
 		printf("%s: Flash Time Out Error\n", __func__);
@@ -324,7 +324,7 @@
 		int sector_end = sector + chip->ecc.steps - 1;
  
 		for (i = sector / 4; i <= sector_end / 4; i++)
-			eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
+			eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
  
 		for (i = sector; i <= sector_end; i++) {
 			errors = check_read_ecc(mtd, ctrl, eccstat, i);
  
  
  
  
@@ -364,30 +364,30 @@
  
 	/* Program FIR/IFC_NAND_FCR0 for Small/Large page */
 	if (mtd->writesize > 512) {
-		out_be32(&ifc->ifc_nand.nand_fir0,
-			 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-			 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
-			 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
-			 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
-			 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
-		out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
+		ifc_out32(&ifc->ifc_nand.nand_fir0,
+			  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+			  (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
+			  (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
+			  (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
+			  (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
  
-		out_be32(&ifc->ifc_nand.nand_fcr0,
-			(NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
-			(NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fcr0,
+			  (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
+			  (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
 	} else {
-		out_be32(&ifc->ifc_nand.nand_fir0,
-			 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-			 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
-			 (IFC_FIR_OP_RA0  << IFC_NAND_FIR0_OP2_SHIFT) |
-			 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fir0,
+			  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+			  (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
+			  (IFC_FIR_OP_RA0  << IFC_NAND_FIR0_OP2_SHIFT) |
+			  (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
  
 		if (oob)
-			out_be32(&ifc->ifc_nand.nand_fcr0,
-				 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
+			ifc_out32(&ifc->ifc_nand.nand_fcr0,
+				  NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
 		else
-			out_be32(&ifc->ifc_nand.nand_fcr0,
-				NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
+			ifc_out32(&ifc->ifc_nand.nand_fcr0,
+				  NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
 	}
 }
  
@@ -408,7 +408,7 @@
 	switch (command) {
 	/* READ0 read the entire buffer to use hardware ECC. */
 	case NAND_CMD_READ0: {
-		out_be32(&ifc->ifc_nand.nand_fbcr, 0);
+		ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
 		set_addr(mtd, 0, page_addr, 0);
  
 		ctrl->read_bytes = mtd->writesize + mtd->oobsize;
@@ -424,7 +424,7 @@
  
 	/* READOOB reads only the OOB because no ECC is performed. */
 	case NAND_CMD_READOOB:
-		out_be32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
+		ifc_out32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
 		set_addr(mtd, column, page_addr, 1);
  
 		ctrl->read_bytes = mtd->writesize + mtd->oobsize;
  
@@ -441,19 +441,19 @@
 		if (command == NAND_CMD_PARAM)
 			timing = IFC_FIR_OP_RBCD;
  
-		out_be32(&ifc->ifc_nand.nand_fir0,
-				(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-				(IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
-				(timing << IFC_NAND_FIR0_OP2_SHIFT));
-		out_be32(&ifc->ifc_nand.nand_fcr0,
-				command << IFC_NAND_FCR0_CMD0_SHIFT);
-		out_be32(&ifc->ifc_nand.row3, column);
+		ifc_out32(&ifc->ifc_nand.nand_fir0,
+			  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+			  (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
+			  (timing << IFC_NAND_FIR0_OP2_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fcr0,
+			  command << IFC_NAND_FCR0_CMD0_SHIFT);
+		ifc_out32(&ifc->ifc_nand.row3, column);
  
 		/*
 		 * although currently it's 8 bytes for READID, we always read
 		 * the maximum 256 bytes(for PARAM)
 		 */
-		out_be32(&ifc->ifc_nand.nand_fbcr, 256);
+		ifc_out32(&ifc->ifc_nand.nand_fbcr, 256);
 		ctrl->read_bytes = 256;
  
 		set_addr(mtd, 0, 0, 0);
  
  
@@ -468,16 +468,16 @@
  
 	/* ERASE2 uses the block and page address from ERASE1 */
 	case NAND_CMD_ERASE2:
-		out_be32(&ifc->ifc_nand.nand_fir0,
-			 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-			 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
-			 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fir0,
+			  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+			  (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
+			  (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
  
-		out_be32(&ifc->ifc_nand.nand_fcr0,
-			 (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
-			 (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fcr0,
+			  (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
+			  (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
  
-		out_be32(&ifc->ifc_nand.nand_fbcr, 0);
+		ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
 		ctrl->read_bytes = 0;
 		fsl_ifc_run_command(mtd);
 		return;
  
@@ -494,17 +494,18 @@
 				(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
 				(NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
  
-			out_be32(&ifc->ifc_nand.nand_fir0,
-				 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-				 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
-				 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
-				 (IFC_FIR_OP_WBCD  << IFC_NAND_FIR0_OP3_SHIFT) |
-				 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT));
-			out_be32(&ifc->ifc_nand.nand_fir1,
-				 (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
-				 (IFC_FIR_OP_RDSTAT <<
+			ifc_out32(&ifc->ifc_nand.nand_fir0,
+				  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+				  (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
+				  (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
+				  (IFC_FIR_OP_WBCD  <<
+						IFC_NAND_FIR0_OP3_SHIFT) |
+				  (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT));
+			ifc_out32(&ifc->ifc_nand.nand_fir1,
+				  (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
+				  (IFC_FIR_OP_RDSTAT <<
 					IFC_NAND_FIR1_OP6_SHIFT) |
-				 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT));
+				  (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT));
 		} else {
 			nand_fcr0 = ((NAND_CMD_PAGEPROG <<
 					IFC_NAND_FCR0_CMD1_SHIFT) |
  
@@ -513,18 +514,18 @@
 				    (NAND_CMD_STATUS <<
 					IFC_NAND_FCR0_CMD3_SHIFT));
  
-			out_be32(&ifc->ifc_nand.nand_fir0,
-				 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-				 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
-				 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
-				 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
-				 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
-			out_be32(&ifc->ifc_nand.nand_fir1,
-				 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
-				 (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
-				 (IFC_FIR_OP_RDSTAT <<
+			ifc_out32(&ifc->ifc_nand.nand_fir0,
+				  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+				  (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
+				  (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
+				  (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
+				  (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
+			ifc_out32(&ifc->ifc_nand.nand_fir1,
+				  (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
+				  (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
+				  (IFC_FIR_OP_RDSTAT <<
 					IFC_NAND_FIR1_OP7_SHIFT) |
-				 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT));
+				  (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT));
  
 			if (column >= mtd->writesize)
 				nand_fcr0 |=
@@ -539,7 +540,7 @@
 			column -= mtd->writesize;
 			ctrl->oob = 1;
 		}
-		out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
+		ifc_out32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
 		set_addr(mtd, column, page_addr, ctrl->oob);
 		return;
 	}
  
  
@@ -547,21 +548,21 @@
 	/* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 	case NAND_CMD_PAGEPROG:
 		if (ctrl->oob)
-			out_be32(&ifc->ifc_nand.nand_fbcr,
-					ctrl->index - ctrl->column);
+			ifc_out32(&ifc->ifc_nand.nand_fbcr,
+				  ctrl->index - ctrl->column);
 		else
-			out_be32(&ifc->ifc_nand.nand_fbcr, 0);
+			ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
  
 		fsl_ifc_run_command(mtd);
 		return;
  
 	case NAND_CMD_STATUS:
-		out_be32(&ifc->ifc_nand.nand_fir0,
-				(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-				(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
-		out_be32(&ifc->ifc_nand.nand_fcr0,
-				NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
-		out_be32(&ifc->ifc_nand.nand_fbcr, 1);
+		ifc_out32(&ifc->ifc_nand.nand_fir0,
+			  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+			  (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fcr0,
+			  NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
+		ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
 		set_addr(mtd, 0, 0, 0);
 		ctrl->read_bytes = 1;
  
@@ -572,10 +573,10 @@
 		return;
  
 	case NAND_CMD_RESET:
-		out_be32(&ifc->ifc_nand.nand_fir0,
-				IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
-		out_be32(&ifc->ifc_nand.nand_fcr0,
-				NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
+		ifc_out32(&ifc->ifc_nand.nand_fir0,
+			  IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
+		ifc_out32(&ifc->ifc_nand.nand_fcr0,
+			  NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
 		fsl_ifc_run_command(mtd);
 		return;
  
@@ -647,8 +648,8 @@
 	 * next byte.
 	 */
 	if (ctrl->index < ctrl->read_bytes) {
-		data = in_be16((uint16_t *)&ctrl->
-					addr[ctrl->index]);
+		data = ifc_in16((uint16_t *)&ctrl->
+				 addr[ctrl->index]);
 		ctrl->index += 2;
 		return (uint8_t)data;
 	}
@@ -727,12 +728,12 @@
 		return NAND_STATUS_FAIL;
  
 	/* Use READ_STATUS command, but wait for the device to be ready */
-	out_be32(&ifc->ifc_nand.nand_fir0,
-		 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-		 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
-	out_be32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
-			IFC_NAND_FCR0_CMD0_SHIFT);
-	out_be32(&ifc->ifc_nand.nand_fbcr, 1);
+	ifc_out32(&ifc->ifc_nand.nand_fir0,
+		  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+		  (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
+	ifc_out32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
+		  IFC_NAND_FCR0_CMD0_SHIFT);
+	ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
 	set_addr(mtd, 0, 0, 0);
 	ctrl->read_bytes = 1;
  
@@ -741,7 +742,7 @@
 	if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
 		return NAND_STATUS_FAIL;
  
-	nand_fsr = in_be32(&ifc->ifc_nand.nand_fsr);
+	nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
  
 	/* Chip sometimes reporting write protect even when it's not */
 	nand_fsr = nand_fsr | NAND_STATUS_WP;
  
  
@@ -784,17 +785,17 @@
 	ifc_ctrl->regs = IFC_BASE_ADDR;
  
 	/* clear event registers */
-	out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U);
-	out_be32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
+	ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U);
+	ifc_out32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
  
 	/* Enable error and event for any detected errors */
-	out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_en,
-			IFC_NAND_EVTER_EN_OPC_EN |
-			IFC_NAND_EVTER_EN_PGRDCMPL_EN |
-			IFC_NAND_EVTER_EN_FTOER_EN |
-			IFC_NAND_EVTER_EN_WPER_EN);
+	ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_en,
+		  IFC_NAND_EVTER_EN_OPC_EN |
+		  IFC_NAND_EVTER_EN_PGRDCMPL_EN |
+		  IFC_NAND_EVTER_EN_FTOER_EN |
+		  IFC_NAND_EVTER_EN_WPER_EN);
  
-	out_be32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0);
+	ifc_out32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0);
 }
  
 static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
  
  
  
  
  
  
  
  
  
@@ -810,50 +811,50 @@
 	cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT;
  
 	/* Save CSOR and CSOR_ext */
-	csor = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor);
-	csor_ext = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext);
+	csor = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor);
+	csor_ext = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor_ext);
  
 	/* chage PageSize 8K and SpareSize 1K*/
 	csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
-	out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k);
-	out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400);
+	ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k);
+	ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400);
  
 	/* READID */
-	out_be32(&ifc->ifc_nand.nand_fir0,
-			(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-			(IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
-			(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
-	out_be32(&ifc->ifc_nand.nand_fcr0,
-			NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
-	out_be32(&ifc->ifc_nand.row3, 0x0);
+	ifc_out32(&ifc->ifc_nand.nand_fir0,
+		  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+		  (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
+		  (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
+	ifc_out32(&ifc->ifc_nand.nand_fcr0,
+		  NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
+	ifc_out32(&ifc->ifc_nand.row3, 0x0);
  
-	out_be32(&ifc->ifc_nand.nand_fbcr, 0x0);
+	ifc_out32(&ifc->ifc_nand.nand_fbcr, 0x0);
  
 	/* Program ROW0/COL0 */
-	out_be32(&ifc->ifc_nand.row0, 0x0);
-	out_be32(&ifc->ifc_nand.col0, 0x0);
+	ifc_out32(&ifc->ifc_nand.row0, 0x0);
+	ifc_out32(&ifc->ifc_nand.col0, 0x0);
  
 	/* set the chip select for NAND Transaction */
-	out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
+	ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
  
 	/* start read seq */
-	out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
+	ifc_out32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
  
 	/* wait for NAND Machine complete flag or timeout */
 	end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
  
 	while (end_tick > get_ticks()) {
-		ifc_ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat);
+		ifc_ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
  
 		if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC)
 			break;
 	}
  
-	out_be32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
+	ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
  
 	/* Restore CSOR and CSOR_ext */
-	out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor);
-	out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext);
+	ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor);
+	ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext);
 }
  
 static int fsl_ifc_chip_init(int devnum, u8 *addr)
@@ -883,8 +884,8 @@
 	for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
 		phys_addr_t phys_addr = virt_to_phys(addr);
  
-		cspr = in_be32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr);
-		csor = in_be32(&ifc_ctrl->regs->csor_cs[priv->bank].csor);
+		cspr = ifc_in32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr);
+		csor = ifc_in32(&ifc_ctrl->regs->csor_cs[priv->bank].csor);
  
 		if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
 		    (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr)) {
@@ -1004,7 +1005,7 @@
 		nand->ecc.mode = NAND_ECC_SOFT;
 	}
  
-	ver = in_be32(&ifc_ctrl->regs->ifc_rev);
+	ver = ifc_in32(&ifc_ctrl->regs->ifc_rev);
 	if (ver == FSL_IFC_V1_1_0)
 		fsl_ifc_sram_init();
  
@@ -60,7 +60,7 @@
 	bufnum_end = bufnum + bufperpage - 1;
  
 	do {
-		status = in_be32(&ifc->ifc_nand.nand_evter_stat);
+		status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
 	} while (!(status & IFC_NAND_EVTER_STAT_OPC));
  
 	if (status & IFC_NAND_EVTER_STAT_FTOER) {
  
@@ -70,14 +70,14 @@
 	}
  
 	for (i = bufnum / 4; i <= bufnum_end / 4; i++)
-		eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
+		eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
  
 	for (i = bufnum; i <= bufnum_end; i++) {
 		if (check_read_ecc(buf, eccstat, i, page_size))
 			break;
 	}
  
-	out_be32(&ifc->ifc_nand.nand_evter_stat, status);
+	ifc_out32(&ifc->ifc_nand.nand_evter_stat, status);
 }
  
 static inline int bad_block(uchar *marker, int port_size)
  
  
  
  
  
  
@@ -140,38 +140,38 @@
 	blk_size = pages_per_blk * page_size;
  
 	/* Open Full SRAM mapping for spare are access */
-	out_be32(&ifc->ifc_nand.ncfgr, 0x0);
+	ifc_out32(&ifc->ifc_nand.ncfgr, 0x0);
  
 	/* Clear Boot events */
-	out_be32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff);
+	ifc_out32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff);
  
 	/* Program FIR/FCR for Large/Small page */
 	if (page_size > 512) {
-		out_be32(&ifc->ifc_nand.nand_fir0,
-			 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-			 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
-			 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
-			 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
-			 (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT));
-		out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
+		ifc_out32(&ifc->ifc_nand.nand_fir0,
+			  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+			  (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
+			  (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
+			  (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
+			  (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
  
-		out_be32(&ifc->ifc_nand.nand_fcr0,
-			 (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
-			 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fcr0,
+			  (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
+			  (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
 	} else {
-		out_be32(&ifc->ifc_nand.nand_fir0,
-			 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-			 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
-			 (IFC_FIR_OP_RA0  << IFC_NAND_FIR0_OP2_SHIFT) |
-			 (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT));
-		out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
+		ifc_out32(&ifc->ifc_nand.nand_fir0,
+			  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+			  (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
+			  (IFC_FIR_OP_RA0  << IFC_NAND_FIR0_OP2_SHIFT) |
+			  (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
  
-		out_be32(&ifc->ifc_nand.nand_fcr0,
-			 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
+		ifc_out32(&ifc->ifc_nand.nand_fcr0,
+			  NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
 	}
  
 	/* Program FBCR = 0 for full page read */
-	out_be32(&ifc->ifc_nand.nand_fbcr, 0);
+	ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
  
 	/* Read and copy u-boot on SDRAM from NAND device, In parallel
 	 * check for Bad block if found skip it and read continue to
  
@@ -184,11 +184,11 @@
 			bufnum = pg_no & bufnum_mask;
 			sram_addr = bufnum * page_size * 2;
  
-			out_be32(&ifc->ifc_nand.row0, pg_no);
-			out_be32(&ifc->ifc_nand.col0, 0);
+			ifc_out32(&ifc->ifc_nand.row0, pg_no);
+			ifc_out32(&ifc->ifc_nand.col0, 0);
 			/* start read */
-			out_be32(&ifc->ifc_nand.nandseq_strt,
-				 IFC_NAND_SEQ_STRT_FIR_STRT);
+			ifc_out32(&ifc->ifc_nand.nandseq_strt,
+				  IFC_NAND_SEQ_STRT_FIR_STRT);
  
 			/* wait for read to complete */
 			nand_wait(&buf[sram_addr], bufnum, page_size);
@@ -12,6 +12,20 @@
 #include <config.h>
 #include <common.h>
  
+
+#ifdef CONFIG_SYS_FSL_IFC_LE
+#define ifc_in32(a)       in_le32(a)
+#define ifc_out32(a, v)   out_le32(a, v)
+#define ifc_in16(a)       in_le16(a)
+#elif defined(CONFIG_SYS_FSL_IFC_BE)
+#define ifc_in32(a)       in_be32(a)
+#define ifc_out32(a, v)   out_be32(a, v)
+#define ifc_in16(a)       in_be16(a)
+#else
+#error Neither CONFIG_SYS_FSL_IFC_LE nor CONFIG_SYS_FSL_IFC_BE is defined
+#endif
+
+
 /*
  * CSPR - Chip Select Property Register
  */
  
  
@@ -773,20 +787,22 @@
  
 #define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR)
  
-#define get_ifc_cspr_ext(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext))
-#define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr))
-#define get_ifc_csor_ext(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext))
-#define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor))
-#define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask))
-#define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j]))
+#define get_ifc_cspr_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext))
+#define get_ifc_cspr(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr))
+#define get_ifc_csor_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext))
+#define get_ifc_csor(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor))
+#define get_ifc_amask(i) (ifc_in32(&(IFC_BASE_ADDR)->amask_cs[i].amask))
+#define get_ifc_ftim(i, j) (ifc_in32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j]))
  
-#define set_ifc_cspr_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v))
-#define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v))
-#define set_ifc_csor_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v))
-#define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v))
-#define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v))
+#define set_ifc_cspr_ext(i, v) \
+			(ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v))
+#define set_ifc_cspr(i, v) (ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v))
+#define set_ifc_csor_ext(i, v) \
+			(ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v))
+#define set_ifc_csor(i, v) (ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v))
+#define set_ifc_amask(i, v) (ifc_out32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v))
 #define set_ifc_ftim(i, j, v) \
-			(out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v))
+			(ifc_out32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v))
  
 enum ifc_chip_sel {
 	IFC_CS0,
...	...	@@ -472,6 +472,12 @@
472	472	Board config to use DDR3. It can be enabled for SoCs with
473	473	Freescale DDR3 controllers.
474	474
	475	+ CONFIG_SYS_FSL_IFC_BE
	476	+ Defines the IFC controller register space as Big Endian
	477	+
	478	+ CONFIG_SYS_FSL_IFC_LE
	479	+ Defines the IFC controller register space as Little Endian
	480	+
475	481	CONFIG_SYS_FSL_PBL_PBI
476	482	It enables addition of RCW (Power on reset configuration) in built image.
477	483	Please refer doc/README.pblimage for more details
...	...	@@ -22,6 +22,9 @@
22	22	#define FSL_DDR_VER_4_7 47
23	23	#define FSL_DDR_VER_5_0 50
24	24
	25	+/* IP endianness */
	26	+#define CONFIG_SYS_FSL_IFC_BE
	27	+
25	28	/* Number of TLB CAM entries we have on FSL Book-E chips */
26	29	#if defined(CONFIG_E500MC)
27	30	#define CONFIG_SYS_NUM_TLBCAMS 64
...	...	@@ -230,8 +230,8 @@
230	230	ctrl->page = page_addr;
231	231
232	232	/* Program ROW0/COL0 */
233		- out_be32(&ifc->ifc_nand.row0, page_addr);
234		- out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) \| column);
	233	+ ifc_out32(&ifc->ifc_nand.row0, page_addr);
	234	+ ifc_out32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) \| column);
235	235
236	236	buf_num = page_addr & priv->bufnum_mask;
237	237
238	238
239	239
240	240
...	...	@@ -294,23 +294,23 @@
294	294	int i;
295	295
296	296	/* set the chip select for NAND Transaction */
297		- out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
	297	+ ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
298	298
299	299	/* start read/write seq */
300		- out_be32(&ifc->ifc_nand.nandseq_strt,
301		- IFC_NAND_SEQ_STRT_FIR_STRT);
	300	+ ifc_out32(&ifc->ifc_nand.nandseq_strt,
	301	+ IFC_NAND_SEQ_STRT_FIR_STRT);
302	302
303	303	/* wait for NAND Machine complete flag or timeout */
304	304	end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
305	305
306	306	while (end_tick > get_ticks()) {
307		- ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat);
	307	+ ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
308	308
309	309	if (ctrl->status & IFC_NAND_EVTER_STAT_OPC)
310	310	break;
311	311	}
312	312
313		- out_be32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
	313	+ ifc_out32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
314	314
315	315	if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER)
316	316	printf("%s: Flash Time Out Error\n", __func__);
...	...	@@ -324,7 +324,7 @@
324	324	int sector_end = sector + chip->ecc.steps - 1;
325	325
326	326	for (i = sector / 4; i <= sector_end / 4; i++)
327		- eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
	327	+ eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
328	328
329	329	for (i = sector; i <= sector_end; i++) {
330	330	errors = check_read_ecc(mtd, ctrl, eccstat, i);
331	331
332	332
333	333
334	334
...	...	@@ -364,30 +364,30 @@
364	364
365	365	/* Program FIR/IFC_NAND_FCR0 for Small/Large page */
366	366	if (mtd->writesize > 512) {
367		- out_be32(&ifc->ifc_nand.nand_fir0,
368		- (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
369		- (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) \|
370		- (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) \|
371		- (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) \|
372		- (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
373		- out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
	367	+ ifc_out32(&ifc->ifc_nand.nand_fir0,
	368	+ (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
	369	+ (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) \|
	370	+ (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) \|
	371	+ (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) \|
	372	+ (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
	373	+ ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
374	374
375		- out_be32(&ifc->ifc_nand.nand_fcr0,
376		- (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) \|
377		- (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
	375	+ ifc_out32(&ifc->ifc_nand.nand_fcr0,
	376	+ (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) \|
	377	+ (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
378	378	} else {
379		- out_be32(&ifc->ifc_nand.nand_fir0,
380		- (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
381		- (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) \|
382		- (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) \|
383		- (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
	379	+ ifc_out32(&ifc->ifc_nand.nand_fir0,
	380	+ (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
	381	+ (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) \|
	382	+ (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) \|
	383	+ (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
384	384
385	385	if (oob)
386		- out_be32(&ifc->ifc_nand.nand_fcr0,
387		- NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
	386	+ ifc_out32(&ifc->ifc_nand.nand_fcr0,
	387	+ NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
388	388	else
389		- out_be32(&ifc->ifc_nand.nand_fcr0,
390		- NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
	389	+ ifc_out32(&ifc->ifc_nand.nand_fcr0,
	390	+ NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
391	391	}
392	392	}
393	393
...	...	@@ -408,7 +408,7 @@
408	408	switch (command) {
409	409	/* READ0 read the entire buffer to use hardware ECC. */
410	410	case NAND_CMD_READ0: {
411		- out_be32(&ifc->ifc_nand.nand_fbcr, 0);
	411	+ ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
412	412	set_addr(mtd, 0, page_addr, 0);
413	413
414	414	ctrl->read_bytes = mtd->writesize + mtd->oobsize;
...	...	@@ -424,7 +424,7 @@
424	424
425	425	/* READOOB reads only the OOB because no ECC is performed. */
426	426	case NAND_CMD_READOOB:
427		- out_be32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
	427	+ ifc_out32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
428	428	set_addr(mtd, column, page_addr, 1);
429	429
430	430	ctrl->read_bytes = mtd->writesize + mtd->oobsize;
431	431
...	...	@@ -441,19 +441,19 @@
441	441	if (command == NAND_CMD_PARAM)
442	442	timing = IFC_FIR_OP_RBCD;
443	443
444		- out_be32(&ifc->ifc_nand.nand_fir0,
445		- (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
446		- (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) \|
447		- (timing << IFC_NAND_FIR0_OP2_SHIFT));
448		- out_be32(&ifc->ifc_nand.nand_fcr0,
449		- command << IFC_NAND_FCR0_CMD0_SHIFT);
450		- out_be32(&ifc->ifc_nand.row3, column);
	444	+ ifc_out32(&ifc->ifc_nand.nand_fir0,
	445	+ (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
	446	+ (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) \|
	447	+ (timing << IFC_NAND_FIR0_OP2_SHIFT));
	448	+ ifc_out32(&ifc->ifc_nand.nand_fcr0,
	449	+ command << IFC_NAND_FCR0_CMD0_SHIFT);
	450	+ ifc_out32(&ifc->ifc_nand.row3, column);
451	451
452	452	/*
453	453	* although currently it's 8 bytes for READID, we always read
454	454	* the maximum 256 bytes(for PARAM)
455	455	*/
456		- out_be32(&ifc->ifc_nand.nand_fbcr, 256);
	456	+ ifc_out32(&ifc->ifc_nand.nand_fbcr, 256);
457	457	ctrl->read_bytes = 256;
458	458
459	459	set_addr(mtd, 0, 0, 0);
460	460
461	461
...	...	@@ -468,16 +468,16 @@
468	468
469	469	/* ERASE2 uses the block and page address from ERASE1 */
470	470	case NAND_CMD_ERASE2:
471		- out_be32(&ifc->ifc_nand.nand_fir0,
472		- (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
473		- (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) \|
474		- (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
	471	+ ifc_out32(&ifc->ifc_nand.nand_fir0,
	472	+ (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
	473	+ (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) \|
	474	+ (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
475	475
476		- out_be32(&ifc->ifc_nand.nand_fcr0,
477		- (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) \|
478		- (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
	476	+ ifc_out32(&ifc->ifc_nand.nand_fcr0,
	477	+ (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) \|
	478	+ (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
479	479
480		- out_be32(&ifc->ifc_nand.nand_fbcr, 0);
	480	+ ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
481	481	ctrl->read_bytes = 0;
482	482	fsl_ifc_run_command(mtd);
483	483	return;
484	484
...	...	@@ -494,17 +494,18 @@
494	494	(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) \|
495	495	(NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
496	496
497		- out_be32(&ifc->ifc_nand.nand_fir0,
498		- (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
499		- (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) \|
500		- (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) \|
501		- (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) \|
502		- (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT));
503		- out_be32(&ifc->ifc_nand.nand_fir1,
504		- (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) \|
505		- (IFC_FIR_OP_RDSTAT <<
	497	+ ifc_out32(&ifc->ifc_nand.nand_fir0,
	498	+ (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
	499	+ (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) \|
	500	+ (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) \|
	501	+ (IFC_FIR_OP_WBCD <<
	502	+ IFC_NAND_FIR0_OP3_SHIFT) \|
	503	+ (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT));
	504	+ ifc_out32(&ifc->ifc_nand.nand_fir1,
	505	+ (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) \|
	506	+ (IFC_FIR_OP_RDSTAT <<
506	507	IFC_NAND_FIR1_OP6_SHIFT) \|
507		- (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT));
	508	+ (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT));
508	509	} else {
509	510	nand_fcr0 = ((NAND_CMD_PAGEPROG <<
510	511	IFC_NAND_FCR0_CMD1_SHIFT) \|
511	512
...	...	@@ -513,18 +514,18 @@
513	514	(NAND_CMD_STATUS <<
514	515	IFC_NAND_FCR0_CMD3_SHIFT));
515	516
516		- out_be32(&ifc->ifc_nand.nand_fir0,
517		- (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
518		- (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) \|
519		- (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) \|
520		- (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) \|
521		- (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
522		- out_be32(&ifc->ifc_nand.nand_fir1,
523		- (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) \|
524		- (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) \|
525		- (IFC_FIR_OP_RDSTAT <<
	517	+ ifc_out32(&ifc->ifc_nand.nand_fir0,
	518	+ (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
	519	+ (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) \|
	520	+ (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) \|
	521	+ (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) \|
	522	+ (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
	523	+ ifc_out32(&ifc->ifc_nand.nand_fir1,
	524	+ (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) \|
	525	+ (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) \|
	526	+ (IFC_FIR_OP_RDSTAT <<
526	527	IFC_NAND_FIR1_OP7_SHIFT) \|
527		- (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT));
	528	+ (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT));
528	529
529	530	if (column >= mtd->writesize)
530	531	nand_fcr0 \|=
...	...	@@ -539,7 +540,7 @@
539	540	column -= mtd->writesize;
540	541	ctrl->oob = 1;
541	542	}
542		- out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
	543	+ ifc_out32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
543	544	set_addr(mtd, column, page_addr, ctrl->oob);
544	545	return;
545	546	}
546	547
547	548
...	...	@@ -547,21 +548,21 @@
547	548	/* PAGEPROG reuses all of the setup from SEQIN and adds the length */
548	549	case NAND_CMD_PAGEPROG:
549	550	if (ctrl->oob)
550		- out_be32(&ifc->ifc_nand.nand_fbcr,
551		- ctrl->index - ctrl->column);
	551	+ ifc_out32(&ifc->ifc_nand.nand_fbcr,
	552	+ ctrl->index - ctrl->column);
552	553	else
553		- out_be32(&ifc->ifc_nand.nand_fbcr, 0);
	554	+ ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
554	555
555	556	fsl_ifc_run_command(mtd);
556	557	return;
557	558
558	559	case NAND_CMD_STATUS:
559		- out_be32(&ifc->ifc_nand.nand_fir0,
560		- (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
561		- (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
562		- out_be32(&ifc->ifc_nand.nand_fcr0,
563		- NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
564		- out_be32(&ifc->ifc_nand.nand_fbcr, 1);
	560	+ ifc_out32(&ifc->ifc_nand.nand_fir0,
	561	+ (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
	562	+ (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
	563	+ ifc_out32(&ifc->ifc_nand.nand_fcr0,
	564	+ NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
	565	+ ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
565	566	set_addr(mtd, 0, 0, 0);
566	567	ctrl->read_bytes = 1;
567	568
...	...	@@ -572,10 +573,10 @@
572	573	return;
573	574
574	575	case NAND_CMD_RESET:
575		- out_be32(&ifc->ifc_nand.nand_fir0,
576		- IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
577		- out_be32(&ifc->ifc_nand.nand_fcr0,
578		- NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
	576	+ ifc_out32(&ifc->ifc_nand.nand_fir0,
	577	+ IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
	578	+ ifc_out32(&ifc->ifc_nand.nand_fcr0,
	579	+ NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
579	580	fsl_ifc_run_command(mtd);
580	581	return;
581	582
...	...	@@ -647,8 +648,8 @@
647	648	* next byte.
648	649	*/
649	650	if (ctrl->index < ctrl->read_bytes) {
650		- data = in_be16((uint16_t *)&ctrl->
651		- addr[ctrl->index]);
	651	+ data = ifc_in16((uint16_t *)&ctrl->
	652	+ addr[ctrl->index]);
652	653	ctrl->index += 2;
653	654	return (uint8_t)data;
654	655	}
...	...	@@ -727,12 +728,12 @@
727	728	return NAND_STATUS_FAIL;
728	729
729	730	/* Use READ_STATUS command, but wait for the device to be ready */
730		- out_be32(&ifc->ifc_nand.nand_fir0,
731		- (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
732		- (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
733		- out_be32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
734		- IFC_NAND_FCR0_CMD0_SHIFT);
735		- out_be32(&ifc->ifc_nand.nand_fbcr, 1);
	731	+ ifc_out32(&ifc->ifc_nand.nand_fir0,
	732	+ (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
	733	+ (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
	734	+ ifc_out32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
	735	+ IFC_NAND_FCR0_CMD0_SHIFT);
	736	+ ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
736	737	set_addr(mtd, 0, 0, 0);
737	738	ctrl->read_bytes = 1;
738	739
...	...	@@ -741,7 +742,7 @@
741	742	if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
742	743	return NAND_STATUS_FAIL;
743	744
744		- nand_fsr = in_be32(&ifc->ifc_nand.nand_fsr);
	745	+ nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
745	746
746	747	/* Chip sometimes reporting write protect even when it's not */
747	748	nand_fsr = nand_fsr \| NAND_STATUS_WP;
748	749
749	750
...	...	@@ -784,17 +785,17 @@
784	785	ifc_ctrl->regs = IFC_BASE_ADDR;
785	786
786	787	/* clear event registers */
787		- out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U);
788		- out_be32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
	788	+ ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U);
	789	+ ifc_out32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
789	790
790	791	/* Enable error and event for any detected errors */
791		- out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_en,
792		- IFC_NAND_EVTER_EN_OPC_EN \|
793		- IFC_NAND_EVTER_EN_PGRDCMPL_EN \|
794		- IFC_NAND_EVTER_EN_FTOER_EN \|
795		- IFC_NAND_EVTER_EN_WPER_EN);
	792	+ ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_en,
	793	+ IFC_NAND_EVTER_EN_OPC_EN \|
	794	+ IFC_NAND_EVTER_EN_PGRDCMPL_EN \|
	795	+ IFC_NAND_EVTER_EN_FTOER_EN \|
	796	+ IFC_NAND_EVTER_EN_WPER_EN);
796	797
797		- out_be32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0);
	798	+ ifc_out32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0);
798	799	}
799	800
800	801	static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
801	802
802	803
803	804
804	805
805	806
806	807
807	808
808	809
809	810
...	...	@@ -810,50 +811,50 @@
810	811	cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT;
811	812
812	813	/* Save CSOR and CSOR_ext */
813		- csor = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor);
814		- csor_ext = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext);
	814	+ csor = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor);
	815	+ csor_ext = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor_ext);
815	816
816	817	/* chage PageSize 8K and SpareSize 1K*/
817	818	csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) \| 0x0018C000;
818		- out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k);
819		- out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400);
	819	+ ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k);
	820	+ ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400);
820	821
821	822	/* READID */
822		- out_be32(&ifc->ifc_nand.nand_fir0,
823		- (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
824		- (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) \|
825		- (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
826		- out_be32(&ifc->ifc_nand.nand_fcr0,
827		- NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
828		- out_be32(&ifc->ifc_nand.row3, 0x0);
	823	+ ifc_out32(&ifc->ifc_nand.nand_fir0,
	824	+ (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
	825	+ (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) \|
	826	+ (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
	827	+ ifc_out32(&ifc->ifc_nand.nand_fcr0,
	828	+ NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
	829	+ ifc_out32(&ifc->ifc_nand.row3, 0x0);
829	830
830		- out_be32(&ifc->ifc_nand.nand_fbcr, 0x0);
	831	+ ifc_out32(&ifc->ifc_nand.nand_fbcr, 0x0);
831	832
832	833	/* Program ROW0/COL0 */
833		- out_be32(&ifc->ifc_nand.row0, 0x0);
834		- out_be32(&ifc->ifc_nand.col0, 0x0);
	834	+ ifc_out32(&ifc->ifc_nand.row0, 0x0);
	835	+ ifc_out32(&ifc->ifc_nand.col0, 0x0);
835	836
836	837	/* set the chip select for NAND Transaction */
837		- out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
	838	+ ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
838	839
839	840	/* start read seq */
840		- out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
	841	+ ifc_out32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
841	842
842	843	/* wait for NAND Machine complete flag or timeout */
843	844	end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
844	845
845	846	while (end_tick > get_ticks()) {
846		- ifc_ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat);
	847	+ ifc_ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
847	848
848	849	if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC)
849	850	break;
850	851	}
851	852
852		- out_be32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
	853	+ ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
853	854
854	855	/* Restore CSOR and CSOR_ext */
855		- out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor);
856		- out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext);
	856	+ ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor);
	857	+ ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext);
857	858	}
858	859
859	860	static int fsl_ifc_chip_init(int devnum, u8 *addr)
...	...	@@ -883,8 +884,8 @@
883	884	for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
884	885	phys_addr_t phys_addr = virt_to_phys(addr);
885	886
886		- cspr = in_be32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr);
887		- csor = in_be32(&ifc_ctrl->regs->csor_cs[priv->bank].csor);
	887	+ cspr = ifc_in32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr);
	888	+ csor = ifc_in32(&ifc_ctrl->regs->csor_cs[priv->bank].csor);
888	889
889	890	if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
890	891	(cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr)) {
...	...	@@ -1004,7 +1005,7 @@
1004	1005	nand->ecc.mode = NAND_ECC_SOFT;
1005	1006	}
1006	1007
1007		- ver = in_be32(&ifc_ctrl->regs->ifc_rev);
	1008	+ ver = ifc_in32(&ifc_ctrl->regs->ifc_rev);
1008	1009	if (ver == FSL_IFC_V1_1_0)
1009	1010	fsl_ifc_sram_init();
1010	1011
...	...	@@ -60,7 +60,7 @@
60	60	bufnum_end = bufnum + bufperpage - 1;
61	61
62	62	do {
63		- status = in_be32(&ifc->ifc_nand.nand_evter_stat);
	63	+ status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
64	64	} while (!(status & IFC_NAND_EVTER_STAT_OPC));
65	65
66	66	if (status & IFC_NAND_EVTER_STAT_FTOER) {
67	67
...	...	@@ -70,14 +70,14 @@
70	70	}
71	71
72	72	for (i = bufnum / 4; i <= bufnum_end / 4; i++)
73		- eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
	73	+ eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
74	74
75	75	for (i = bufnum; i <= bufnum_end; i++) {
76	76	if (check_read_ecc(buf, eccstat, i, page_size))
77	77	break;
78	78	}
79	79
80		- out_be32(&ifc->ifc_nand.nand_evter_stat, status);
	80	+ ifc_out32(&ifc->ifc_nand.nand_evter_stat, status);
81	81	}
82	82
83	83	static inline int bad_block(uchar *marker, int port_size)
84	84
85	85
86	86
87	87
88	88
89	89
...	...	@@ -140,38 +140,38 @@
140	140	blk_size = pages_per_blk * page_size;
141	141
142	142	/* Open Full SRAM mapping for spare are access */
143		- out_be32(&ifc->ifc_nand.ncfgr, 0x0);
	143	+ ifc_out32(&ifc->ifc_nand.ncfgr, 0x0);
144	144
145	145	/* Clear Boot events */
146		- out_be32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff);
	146	+ ifc_out32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff);
147	147
148	148	/* Program FIR/FCR for Large/Small page */
149	149	if (page_size > 512) {
150		- out_be32(&ifc->ifc_nand.nand_fir0,
151		- (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
152		- (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) \|
153		- (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) \|
154		- (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) \|
155		- (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT));
156		- out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
	150	+ ifc_out32(&ifc->ifc_nand.nand_fir0,
	151	+ (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
	152	+ (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) \|
	153	+ (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) \|
	154	+ (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) \|
	155	+ (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT));
	156	+ ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
157	157
158		- out_be32(&ifc->ifc_nand.nand_fcr0,
159		- (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) \|
160		- (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
	158	+ ifc_out32(&ifc->ifc_nand.nand_fcr0,
	159	+ (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) \|
	160	+ (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
161	161	} else {
162		- out_be32(&ifc->ifc_nand.nand_fir0,
163		- (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
164		- (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) \|
165		- (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) \|
166		- (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT));
167		- out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
	162	+ ifc_out32(&ifc->ifc_nand.nand_fir0,
	163	+ (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) \|
	164	+ (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) \|
	165	+ (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) \|
	166	+ (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT));
	167	+ ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
168	168
169		- out_be32(&ifc->ifc_nand.nand_fcr0,
170		- NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
	169	+ ifc_out32(&ifc->ifc_nand.nand_fcr0,
	170	+ NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
171	171	}
172	172
173	173	/* Program FBCR = 0 for full page read */
174		- out_be32(&ifc->ifc_nand.nand_fbcr, 0);
	174	+ ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
175	175
176	176	/* Read and copy u-boot on SDRAM from NAND device, In parallel
177	177	* check for Bad block if found skip it and read continue to
178	178
...	...	@@ -184,11 +184,11 @@
184	184	bufnum = pg_no & bufnum_mask;
185	185	sram_addr = bufnum * page_size * 2;
186	186
187		- out_be32(&ifc->ifc_nand.row0, pg_no);
188		- out_be32(&ifc->ifc_nand.col0, 0);
	187	+ ifc_out32(&ifc->ifc_nand.row0, pg_no);
	188	+ ifc_out32(&ifc->ifc_nand.col0, 0);
189	189	/* start read */
190		- out_be32(&ifc->ifc_nand.nandseq_strt,
191		- IFC_NAND_SEQ_STRT_FIR_STRT);
	190	+ ifc_out32(&ifc->ifc_nand.nandseq_strt,
	191	+ IFC_NAND_SEQ_STRT_FIR_STRT);
192	192
193	193	/* wait for read to complete */
194	194	nand_wait(&buf[sram_addr], bufnum, page_size);
...	...	@@ -12,6 +12,20 @@
12	12	#include <config.h>
13	13	#include <common.h>
14	14
	15	+
	16	+#ifdef CONFIG_SYS_FSL_IFC_LE
	17	+#define ifc_in32(a) in_le32(a)
	18	+#define ifc_out32(a, v) out_le32(a, v)
	19	+#define ifc_in16(a) in_le16(a)
	20	+#elif defined(CONFIG_SYS_FSL_IFC_BE)
	21	+#define ifc_in32(a) in_be32(a)
	22	+#define ifc_out32(a, v) out_be32(a, v)
	23	+#define ifc_in16(a) in_be16(a)
	24	+#else
	25	+#error Neither CONFIG_SYS_FSL_IFC_LE nor CONFIG_SYS_FSL_IFC_BE is defined
	26	+#endif
	27	+
	28	+
15	29	/*
16	30	* CSPR - Chip Select Property Register
17	31	*/
18	32
19	33
...	...	@@ -773,20 +787,22 @@
773	787
774	788	#define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR)
775	789
776		-#define get_ifc_cspr_ext(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext))
777		-#define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr))
778		-#define get_ifc_csor_ext(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext))
779		-#define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor))
780		-#define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask))
781		-#define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j]))
	790	+#define get_ifc_cspr_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext))
	791	+#define get_ifc_cspr(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr))
	792	+#define get_ifc_csor_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext))
	793	+#define get_ifc_csor(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor))
	794	+#define get_ifc_amask(i) (ifc_in32(&(IFC_BASE_ADDR)->amask_cs[i].amask))
	795	+#define get_ifc_ftim(i, j) (ifc_in32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j]))
782	796
783		-#define set_ifc_cspr_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v))
784		-#define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v))
785		-#define set_ifc_csor_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v))
786		-#define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v))
787		-#define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v))
	797	+#define set_ifc_cspr_ext(i, v) \
	798	+ (ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v))
	799	+#define set_ifc_cspr(i, v) (ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v))
	800	+#define set_ifc_csor_ext(i, v) \
	801	+ (ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v))
	802	+#define set_ifc_csor(i, v) (ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v))
	803	+#define set_ifc_amask(i, v) (ifc_out32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v))
788	804	#define set_ifc_ftim(i, j, v) \
789		- (out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v))
	805	+ (ifc_out32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v))
790	806
791	807	enum ifc_chip_sel {
792	808	IFC_CS0,