ARM: DRA7/ OMAP5: implement Auxiliary Control Register configuration

Implement logic for ACR(Auxiliary Control Register) configuration using ROM Code smc service. Suggested-by: Richard Woodruff <r-woodruff2@ti.com> Suggested-by: Brad Griffis <bgriffis@ti.com> Reviewed-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>

ARM: DRA7/ OMAP5: implement Auxiliary Control Register configuration
Implement logic for ACR(Auxiliary Control Register) configuration using ROM Code smc service. Suggested-by: Richard Woodruff <r-woodruff2@ti.com> Suggested-by: Brad Griffis <bgriffis@ti.com> Reviewed-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
Nishanth Menon · Tom Rini · Eric Lee
1 parent a615d0be6a
Showing 2 changed files with 7 additions and 0 deletions Side-by-side Diff
arch/arm/cpu/armv7/omap5/hwinit.c
arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -418,4 +418,10 @@
 {
 	omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
 }
+
+void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
+			  u32 cpu_variant, u32 cpu_rev)
+{
+	omap_smc1(OMAP5_SERVICE_ACR_SET, acr);
+}
@@ -81,6 +81,7 @@
 }
  
 #define OMAP5_SERVICE_L2ACTLR_SET    0x104
+#define OMAP5_SERVICE_ACR_SET        0x107
  
 #endif
...	...	@@ -418,4 +418,10 @@
418	418	{
419	419	omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
420	420	}
	421	+
	422	+void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
	423	+ u32 cpu_variant, u32 cpu_rev)
	424	+{
	425	+ omap_smc1(OMAP5_SERVICE_ACR_SET, acr);
	426	+}
...	...	@@ -81,6 +81,7 @@
81	81	}
82	82
83	83	#define OMAP5_SERVICE_L2ACTLR_SET 0x104
	84	+#define OMAP5_SERVICE_ACR_SET 0x107
84	85
85	86	#endif