Eric Lee / smarc-uboot

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Commit 1c0e03df6d5e6b183fdfd6935c8ae5ea4cf233a7

Authored by Ye Li
1 parent 44ab0cb416
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 5 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

MLK-18460-5 mx7d_19x19_arm2: Add LPDDR3, LPDDR2 and DDR3 ARM2 support 

Porting the iMX7D 19x19 LPDDR2, LPDDR3 and DDR3 ARM2 board codes from v2017.03.

Signed-off-by: Ye Li <ye.li@nxp.com>

Showing 17 changed files with 2809 additions and 0 deletions Side-by-side Diff

arch/arm/mach-imx/mx7/Kconfig
Diff comments   View file @ 1c0e03d
... ... @@ -48,6 +48,27 @@
48 48 select DM
49 49 select DM_THERMAL
50 50  
  51 +config TARGET_MX7D_19X19_DDR3_ARM2
  52 + bool "Support mx7d_19x19_ddr3_arm2"
  53 + select BOARD_LATE_INIT
  54 + select MX7D
  55 + select DM
  56 + select DM_THERMAL
  57 +
  58 +config TARGET_MX7D_19X19_LPDDR3_ARM2
  59 + bool "Support mx7d_19x19_lpddr3_arm2"
  60 + select BOARD_LATE_INIT
  61 + select MX7D
  62 + select DM
  63 + select DM_THERMAL
  64 +
  65 +config TARGET_MX7D_19X19_LPDDR2_ARM2
  66 + bool "Support mx7d_19x19_lpddr2_arm2"
  67 + select BOARD_LATE_INIT
  68 + select MX7D
  69 + select DM
  70 + select DM_THERMAL
  71 +
51 72 config TARGET_PICO_IMX7D
52 73 bool "pico-imx7d"
53 74 select BOARD_LATE_INIT
... ... @@ -78,6 +99,8 @@
78 99 source "board/freescale/mx7dsabresd/Kconfig"
79 100 source "board/freescale/mx7d_12x12_lpddr3_arm2/Kconfig"
80 101 source "board/freescale/mx7d_12x12_ddr3_arm2/Kconfig"
  102 +source "board/freescale/mx7d_19x19_ddr3_arm2/Kconfig"
  103 +source "board/freescale/mx7d_19x19_lpddr3_arm2/Kconfig"
81 104 source "board/technexion/pico-imx7d/Kconfig"
82 105 source "board/toradex/colibri_imx7/Kconfig"
83 106 source "board/warp7/Kconfig"
board/freescale/mx7d_19x19_ddr3_arm2/Kconfig
Diff comments   View file @ 1c0e03d
  1 +if TARGET_MX7D_19X19_DDR3_ARM2
  2 +
  3 +config SYS_BOARD
  4 + default "mx7d_19x19_ddr3_arm2"
  5 +
  6 +config SYS_VENDOR
  7 + default "freescale"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "mx7d_19x19_ddr3_arm2"
  11 +
  12 +config SYS_TEXT_BASE
  13 + default 0x87800000
  14 +endif
board/freescale/mx7d_19x19_ddr3_arm2/Makefile
Diff comments   View file @ 1c0e03d
  1 +# (C) Copyright 2014 Freescale Semiconductor, Inc.
  2 +#
  3 +# SPDX-License-Identifier: GPL-2.0+
  4 +#
  5 +
  6 +obj-y := mx7d_19x19_ddr3_arm2.o
board/freescale/mx7d_19x19_ddr3_arm2/imximage.cfg
Diff comments   View file @ 1c0e03d
  1 +/*
  2 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Refer docs/README.imxmage for more details about how-to configure
  7 + * and create imximage boot image
  8 + *
  9 + * The syntax is taken as close as possible with the kwbimage
  10 + */
  11 +
  12 +#define __ASSEMBLY__
  13 +#include <config.h>
  14 +
  15 +/* image version */
  16 +
  17 +IMAGE_VERSION 2
  18 +
  19 +BOOT_FROM sd
  20 +
  21 +#ifdef CONFIG_USE_IMXIMG_PLUGIN
  22 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  23 +PLUGIN board/freescale/mx7d_19x19_ddr3_arm2/plugin.bin 0x00910000
  24 +#else
  25 +
  26 +#ifdef CONFIG_SECURE_BOOT
  27 +CSF CONFIG_CSF_SIZE
  28 +#endif
  29 +
  30 +/*
  31 + * Device Configuration Data (DCD)
  32 + *
  33 + * Each entry must have the format:
  34 + * Addr-type Address Value
  35 + *
  36 + * where:
  37 + * Addr-type register length (1,2 or 4 bytes)
  38 + * Address absolute address of the register
  39 + * value value to be stored in the register
  40 + */
  41 +
  42 +DATA 4 0x30340004 0x4F400005
  43 +/* Clear then set bit30 to ensure exit from DDR retention */
  44 +DATA 4 0x30360388 0x40000000
  45 +DATA 4 0x30360384 0x40000000
  46 +
  47 +DATA 4 0x30391000 0x00000002
  48 +DATA 4 0x307a0000 0x01040001
  49 +DATA 4 0x307a01a0 0x80400003
  50 +DATA 4 0x307a01a4 0x00100020
  51 +DATA 4 0x307a01a8 0x80100004
  52 +DATA 4 0x307a0064 0x00400046
  53 +DATA 4 0x307a0490 0x00000001
  54 +DATA 4 0x307a00d0 0x00020083
  55 +DATA 4 0x307a00d4 0x00690000
  56 +DATA 4 0x307a00dc 0x09300004
  57 +DATA 4 0x307a00e0 0x04080000
  58 +DATA 4 0x307a00e4 0x00100004
  59 +DATA 4 0x307a00f4 0x0000033f
  60 +DATA 4 0x307a0100 0x09081109
  61 +DATA 4 0x307a0104 0x0007020d
  62 +DATA 4 0x307a0108 0x03040407
  63 +DATA 4 0x307a010c 0x00002006
  64 +DATA 4 0x307a0110 0x04020205
  65 +DATA 4 0x307a0114 0x03030202
  66 +DATA 4 0x307a0120 0x00000803
  67 +DATA 4 0x307a0180 0x00800020
  68 +DATA 4 0x307a0184 0x02000100
  69 +DATA 4 0x307a0190 0x02098204
  70 +DATA 4 0x307a0194 0x00030303
  71 +DATA 4 0x307a0200 0x00000016
  72 +DATA 4 0x307a0204 0x00080808
  73 +DATA 4 0x307a0210 0x00000f0f
  74 +DATA 4 0x307a0214 0x07070707
  75 +DATA 4 0x307a0218 0x0f070707
  76 +DATA 4 0x307a0240 0x06000604
  77 +DATA 4 0x307a0244 0x00000001
  78 +DATA 4 0x30391000 0x00000000
  79 +DATA 4 0x30790000 0x17420f40
  80 +DATA 4 0x30790004 0x10210100
  81 +DATA 4 0x30790010 0x00060807
  82 +DATA 4 0x307900b0 0x1010007e
  83 +DATA 4 0x3079009c 0x00000b24
  84 +DATA 4 0x30790020 0x08080808
  85 +DATA 4 0x30790030 0x08080808
  86 +DATA 4 0x30790050 0x01000010
  87 +DATA 4 0x30790050 0x00000010
  88 +
  89 +DATA 4 0x307900c0 0x0e407304
  90 +DATA 4 0x307900c0 0x0e447304
  91 +DATA 4 0x307900c0 0x0e447306
  92 +
  93 +CHECK_BITS_SET 4 0x307900c4 0x1
  94 +
  95 +DATA 4 0x307900c0 0x0e407304
  96 +
  97 +
  98 +DATA 4 0x30384130 0x00000000
  99 +DATA 4 0x30340020 0x00000178
  100 +DATA 4 0x30384130 0x00000002
  101 +DATA 4 0x30790018 0x0000000f
  102 +
  103 +CHECK_BITS_SET 4 0x307a0004 0x1
  104 +
  105 +#endif
board/freescale/mx7d_19x19_ddr3_arm2/imximage_TO_1_1.cfg
Diff comments   View file @ 1c0e03d
  1 +/*
  2 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Refer docs/README.imxmage for more details about how-to configure
  7 + * and create imximage boot image
  8 + *
  9 + * The syntax is taken as close as possible with the kwbimage
  10 + */
  11 +
  12 +#define __ASSEMBLY__
  13 +#include <config.h>
  14 +
  15 +/* image version */
  16 +
  17 +IMAGE_VERSION 2
  18 +
  19 +/*
  20 + * Boot Device : one of
  21 + * spi/sd/nand/onenand, qspi/nor
  22 + */
  23 +
  24 +BOOT_FROM sd
  25 +
  26 +#ifdef CONFIG_USE_IMXIMG_PLUGIN
  27 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  28 +PLUGIN board/freescale/mx7d_19x19_ddr3_arm2/plugin.bin 0x00910000
  29 +#else
  30 +
  31 +#ifdef CONFIG_SECURE_BOOT
  32 +CSF CONFIG_CSF_SIZE
  33 +#endif
  34 +
  35 +/*
  36 + * Device Configuration Data (DCD)
  37 + *
  38 + * Each entry must have the format:
  39 + * Addr-type Address Value
  40 + *
  41 + * where:
  42 + * Addr-type register length (1,2 or 4 bytes)
  43 + * Address absolute address of the register
  44 + * value value to be stored in the register
  45 + */
  46 +
  47 +DATA 4 0x30360070 0x00703021
  48 +DATA 4 0x30360090 0x0
  49 +DATA 4 0x30360070 0x00603021
  50 +CHECK_BITS_SET 4 0x30360070 0x80000000
  51 +DATA 4 0x30389880 0x1
  52 +
  53 +DATA 4 0x30340004 0x4F400005
  54 +/* Clear then set bit30 to ensure exit from DDR retention */
  55 +DATA 4 0x30360388 0x40000000
  56 +DATA 4 0x30360384 0x40000000
  57 +
  58 +DATA 4 0x30391000 0x00000002
  59 +DATA 4 0x307a0000 0x01040001
  60 +DATA 4 0x307a01a0 0x80400003
  61 +DATA 4 0x307a01a4 0x00100020
  62 +DATA 4 0x307a01a8 0x80100004
  63 +DATA 4 0x307a0064 0x00400046
  64 +DATA 4 0x307a0490 0x00000001
  65 +DATA 4 0x307a00d0 0x00020083
  66 +DATA 4 0x307a00d4 0x00690000
  67 +DATA 4 0x307a00dc 0x09300004
  68 +DATA 4 0x307a00e0 0x04080000
  69 +DATA 4 0x307a00e4 0x00100004
  70 +DATA 4 0x307a00f4 0x0000033f
  71 +DATA 4 0x307a0100 0x09081109
  72 +DATA 4 0x307a0104 0x0007020d
  73 +DATA 4 0x307a0108 0x03040407
  74 +DATA 4 0x307a010c 0x00002006
  75 +DATA 4 0x307a0110 0x04020205
  76 +DATA 4 0x307a0114 0x03030202
  77 +DATA 4 0x307a0120 0x00000803
  78 +DATA 4 0x307a0180 0x00800020
  79 +DATA 4 0x307a0184 0x02000100
  80 +DATA 4 0x307a0190 0x02098204
  81 +DATA 4 0x307a0194 0x00030303
  82 +DATA 4 0x307a0200 0x00000016
  83 +DATA 4 0x307a0204 0x00080808
  84 +DATA 4 0x307a0210 0x00000f0f
  85 +DATA 4 0x307a0214 0x07070707
  86 +DATA 4 0x307a0218 0x0f070707
  87 +DATA 4 0x307a0240 0x06000604
  88 +DATA 4 0x307a0244 0x00000001
  89 +DATA 4 0x30391000 0x00000000
  90 +DATA 4 0x30790000 0x17420f40
  91 +DATA 4 0x30790004 0x10210100
  92 +DATA 4 0x30790010 0x00060807
  93 +DATA 4 0x307900b0 0x1010007e
  94 +DATA 4 0x3079009c 0x00000dee
  95 +DATA 4 0x3079007c 0x18181818
  96 +DATA 4 0x30790080 0x18181818
  97 +DATA 4 0x30790084 0x40401818
  98 +DATA 4 0x30790088 0x00000040
  99 +DATA 4 0x3079006c 0x40404040
  100 +DATA 4 0x30790020 0x08080808
  101 +DATA 4 0x30790030 0x08080808
  102 +DATA 4 0x30790050 0x01000010
  103 +DATA 4 0x30790050 0x00000010
  104 +
  105 +DATA 4 0x307900c0 0x0e407304
  106 +DATA 4 0x307900c0 0x0e447304
  107 +DATA 4 0x307900c0 0x0e447306
  108 +
  109 +CHECK_BITS_SET 4 0x307900c4 0x1
  110 +
  111 +DATA 4 0x307900c0 0x0e407304
  112 +
  113 +
  114 +DATA 4 0x30384130 0x00000000
  115 +DATA 4 0x30340020 0x00000178
  116 +DATA 4 0x30384130 0x00000002
  117 +DATA 4 0x30790018 0x0000000f
  118 +
  119 +CHECK_BITS_SET 4 0x307a0004 0x1
  120 +
  121 +#endif
board/freescale/mx7d_19x19_ddr3_arm2/mx7d_19x19_ddr3_arm2.c
Diff comments   View file @ 1c0e03d
  1 +/*
  2 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <asm/arch/clock.h>
  8 +#include <asm/arch/imx-regs.h>
  9 +#include <asm/arch/mx7-pins.h>
  10 +#include <asm/arch/sys_proto.h>
  11 +#include <asm/gpio.h>
  12 +#include <asm/mach-imx/iomux-v3.h>
  13 +#include <asm/mach-imx/boot_mode.h>
  14 +#include <asm/io.h>
  15 +#include <linux/sizes.h>
  16 +#include <common.h>
  17 +#include <fsl_esdhc.h>
  18 +#include <mmc.h>
  19 +#include <miiphy.h>
  20 +#include <netdev.h>
  21 +#include <power/pmic.h>
  22 +#include <power/pfuze3000_pmic.h>
  23 +#include "../common/pfuze.h"
  24 +#ifdef CONFIG_SYS_I2C_MXC
  25 +#include <i2c.h>
  26 +#include <asm/mach-imx/mxc_i2c.h>
  27 +#endif
  28 +#include <asm/arch/crm_regs.h>
  29 +#include <asm/mach-imx/video.h>
  30 +
  31 +DECLARE_GLOBAL_DATA_PTR;
  32 +
  33 +#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
  34 + PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
  35 +
  36 +#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
  37 + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
  38 +
  39 +#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
  40 +#define ENET_PAD_CTRL_MII (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
  41 +
  42 +#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
  43 +
  44 +#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
  45 + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
  46 +
  47 +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
  48 + PAD_CTL_DSE_3P3V_49OHM)
  49 +
  50 +#define QSPI_PAD_CTRL \
  51 + (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
  52 +
  53 +#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
  54 +
  55 +#ifdef CONFIG_SYS_I2C
  56 +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  57 +/* I2C1 for PMIC */
  58 +struct i2c_pads_info i2c_pad_info1 = {
  59 + .scl = {
  60 + .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
  61 + .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
  62 + .gp = IMX_GPIO_NR(4, 8),
  63 + },
  64 + .sda = {
  65 + .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,
  66 + .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,
  67 + .gp = IMX_GPIO_NR(4, 9),
  68 + },
  69 +};
  70 +
  71 +/* I2C2 */
  72 +struct i2c_pads_info i2c_pad_info2 = {
  73 + .scl = {
  74 + .i2c_mode = MX7D_PAD_I2C2_SCL__I2C2_SCL | PC,
  75 + .gpio_mode = MX7D_PAD_I2C2_SCL__GPIO4_IO10 | PC,
  76 + .gp = IMX_GPIO_NR(4, 10),
  77 + },
  78 + .sda = {
  79 + .i2c_mode = MX7D_PAD_I2C2_SDA__I2C2_SDA | PC,
  80 + .gpio_mode = MX7D_PAD_I2C2_SDA__GPIO4_IO11 | PC,
  81 + .gp = IMX_GPIO_NR(4, 11),
  82 + },
  83 +};
  84 +#endif
  85 +
  86 +int dram_init(void)
  87 +{
  88 + gd->ram_size = PHYS_SDRAM_SIZE;
  89 +
  90 + return 0;
  91 +}
  92 +
  93 +static iomux_v3_cfg_t const uart1_pads[] = {
  94 + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  95 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  96 +};
  97 +
  98 +static iomux_v3_cfg_t const usdhc1_emmc_pads[] = {
  99 + MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  100 + MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  101 + MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  102 + MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  103 + MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  104 + MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  105 + MX7D_PAD_ECSPI2_SCLK__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  106 + MX7D_PAD_ECSPI2_MOSI__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  107 + MX7D_PAD_ECSPI2_MISO__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  108 + MX7D_PAD_ECSPI2_SS0__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  109 +
  110 + MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  111 + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  112 +};
  113 +
  114 +static iomux_v3_cfg_t const usdhc2_pads[] = {
  115 + MX7D_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  116 + MX7D_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  117 + MX7D_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  118 + MX7D_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  119 + MX7D_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  120 + MX7D_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  121 +
  122 + MX7D_PAD_GPIO1_IO12__SD2_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  123 +
  124 + MX7D_PAD_SD2_CD_B__GPIO5_IO9 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  125 + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  126 +};
  127 +
  128 +static iomux_v3_cfg_t const usdhc3_pads[] = {
  129 + MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  130 + MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  131 + MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  132 + MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  133 + MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  134 + MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  135 + MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  136 + MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  137 + MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  138 + MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  139 +
  140 + MX7D_PAD_GPIO1_IO13__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  141 +
  142 + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  143 + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  144 +};
  145 +
  146 +
  147 +#ifdef CONFIG_VIDEO_MXS
  148 +static iomux_v3_cfg_t const lcd_pads[] = {
  149 + MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
  150 + MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
  151 + MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  152 + MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  153 + MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  154 + MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  155 + MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  156 + MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  157 + MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  158 + MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  159 + MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  160 + MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  161 + MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  162 + MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  163 + MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  164 + MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  165 + MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  166 + MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  167 + MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  168 + MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  169 + MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  170 + MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  171 + MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  172 + MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  173 + MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  174 + MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  175 + MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  176 + MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  177 +
  178 + MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  179 +};
  180 +
  181 +static iomux_v3_cfg_t const pwm_pads[] = {
  182 + /* Use GPIO for Brightness adjustment, duty cycle = period */
  183 + MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
  184 +};
  185 +
  186 +void do_enable_parallel_lcd(struct display_info_t const *dev)
  187 +{
  188 + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
  189 +
  190 + imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
  191 +
  192 + /* Power up the LCD */
  193 + gpio_request(IMX_GPIO_NR(3, 4), "lcd_pwr");
  194 + gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
  195 +
  196 + /* Set Brightness to high */
  197 + gpio_request(IMX_GPIO_NR(1, 1), "lcd_backlight");
  198 + gpio_direction_output(IMX_GPIO_NR(1, 1) , 1);
  199 +}
  200 +
  201 +struct display_info_t const displays[] = {{
  202 + .bus = ELCDIF1_IPS_BASE_ADDR,
  203 + .addr = 0,
  204 + .pixfmt = 24,
  205 + .detect = NULL,
  206 + .enable = do_enable_parallel_lcd,
  207 + .mode = {
  208 + .name = "MCIMX28LCD",
  209 + .xres = 800,
  210 + .yres = 480,
  211 + .pixclock = 29850,
  212 + .left_margin = 89,
  213 + .right_margin = 164,
  214 + .upper_margin = 23,
  215 + .lower_margin = 10,
  216 + .hsync_len = 10,
  217 + .vsync_len = 10,
  218 + .sync = 0,
  219 + .vmode = FB_VMODE_NONINTERLACED
  220 +} } };
  221 +size_t display_count = ARRAY_SIZE(displays);
  222 +#endif
  223 +
  224 +static iomux_v3_cfg_t const per_rst_pads[] = {
  225 + MX7D_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL),
  226 +};
  227 +
  228 +static iomux_v3_cfg_t const wdog_pads[] = {
  229 + MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  230 +};
  231 +
  232 +#ifdef CONFIG_FEC_MXC
  233 +static iomux_v3_cfg_t const fec2_pads[] = {
  234 + MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  235 + MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  236 + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  237 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  238 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  239 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  240 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  241 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  242 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  243 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  244 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  245 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  246 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  247 + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  248 +};
  249 +
  250 +static void setup_iomux_fec2(void)
  251 +{
  252 + imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
  253 +}
  254 +#endif
  255 +
  256 +static void setup_iomux_uart(void)
  257 +{
  258 + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  259 +}
  260 +
  261 +#ifdef CONFIG_FSL_QSPI
  262 +
  263 +static iomux_v3_cfg_t const quadspi_pads[] = {
  264 + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  265 + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  266 + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  267 + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  268 + MX7D_PAD_EPDC_DATA04__QSPI_A_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  269 + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  270 + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  271 + MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  272 +
  273 + MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  274 + MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  275 + MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  276 + MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  277 + MX7D_PAD_EPDC_DATA12__QSPI_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  278 + MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  279 + MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  280 + MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  281 +
  282 +};
  283 +
  284 +int board_qspi_init(void)
  285 +{
  286 + /* Set the iomux */
  287 + imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
  288 +
  289 + /* Set the clock */
  290 + set_clk_qspi();
  291 +
  292 + return 0;
  293 +}
  294 +#endif
  295 +
  296 +#ifdef CONFIG_FSL_ESDHC
  297 +
  298 +#define USDHC2_CD_GPIO IMX_GPIO_NR(5, 9)
  299 +#define USDHC3_CD_GPIO IMX_GPIO_NR(1, 14)
  300 +
  301 +#define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2)
  302 +#define USDHC2_PWR_GPIO IMX_GPIO_NR(5, 11)
  303 +#define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11)
  304 +
  305 +
  306 +static struct fsl_esdhc_cfg usdhc_cfg[3] = {
  307 + {USDHC1_BASE_ADDR},
  308 + {USDHC2_BASE_ADDR, 0, 4},
  309 + {USDHC3_BASE_ADDR},
  310 +};
  311 +
  312 +int board_mmc_getcd(struct mmc *mmc)
  313 +{
  314 + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  315 + int ret = 0;
  316 +
  317 + switch (cfg->esdhc_base) {
  318 + case USDHC1_BASE_ADDR:
  319 + ret = 1; /* Assume uSDHC1 emmc is always present */
  320 + break;
  321 + case USDHC2_BASE_ADDR:
  322 + ret = !gpio_get_value(USDHC2_CD_GPIO);
  323 + break;
  324 + case USDHC3_BASE_ADDR:
  325 + ret = !gpio_get_value(USDHC3_CD_GPIO);
  326 + break;
  327 + }
  328 +
  329 + return ret;
  330 +}
  331 +int board_mmc_init(bd_t *bis)
  332 +{
  333 + int i;
  334 + /*
  335 + * According to the board_mmc_init() the following map is done:
  336 + * (U-boot device node) (Physical Port)
  337 + * mmc0 USDHC1 (eMMC)
  338 + * mmc1 USDHC2
  339 + * mmc2 USDHC3
  340 + */
  341 + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  342 + switch (i) {
  343 + case 0:
  344 + imx_iomux_v3_setup_multiple_pads(
  345 + usdhc1_emmc_pads, ARRAY_SIZE(usdhc1_emmc_pads));
  346 + gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr");
  347 + gpio_direction_output(USDHC1_PWR_GPIO, 1);
  348 + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  349 + break;
  350 + case 1:
  351 + imx_iomux_v3_setup_multiple_pads(
  352 + usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  353 + gpio_request(USDHC2_PWR_GPIO, "usdhc2_pwr");
  354 + gpio_request(USDHC2_CD_GPIO, "usdhc2_cd");
  355 + gpio_direction_input(USDHC2_CD_GPIO);
  356 + gpio_direction_output(USDHC2_PWR_GPIO, 1);
  357 + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  358 + break;
  359 + case 2:
  360 + imx_iomux_v3_setup_multiple_pads(
  361 + usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  362 + gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr");
  363 + gpio_request(USDHC3_CD_GPIO, "usdhc3_cd");
  364 + gpio_direction_input(USDHC3_CD_GPIO);
  365 + gpio_direction_output(USDHC3_PWR_GPIO, 1);
  366 + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  367 + break;
  368 + default:
  369 + printf("Warning: you configured more USDHC controllers"
  370 + "(%d) than supported by the board\n", i + 1);
  371 + return 0;
  372 + }
  373 +
  374 + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
  375 + printf("Warning: failed to initialize mmc dev %d\n", i);
  376 + }
  377 +
  378 + return 0;
  379 +}
  380 +#endif
  381 +
  382 +#ifdef CONFIG_FEC_MXC
  383 +int board_eth_init(bd_t *bis)
  384 +{
  385 + int ret;
  386 +
  387 + setup_iomux_fec2();
  388 +
  389 + ret = fecmxc_initialize_multi(bis, 0,
  390 + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
  391 + if (ret)
  392 + printf("FEC1 MXC: %s:failed\n", __func__);
  393 +
  394 + return 0;
  395 +}
  396 +
  397 +static int setup_fec(void)
  398 +{
  399 + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
  400 + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
  401 + int ret;
  402 +
  403 + /* Use 125M anatop REF_CLK for ENET2, clear gpr1[14], gpr1[18]*/
  404 + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
  405 + (IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK |
  406 + IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK), 0);
  407 +
  408 + ret = set_clk_enet(ENET_125MHZ);
  409 + if (ret)
  410 + return ret;
  411 +
  412 + return 0;
  413 +}
  414 +
  415 +
  416 +int board_phy_config(struct phy_device *phydev)
  417 +{
  418 + /* Enable 1.8V(SEL_1P5_1P8_POS_REG) on
  419 + Phy control debug reg 0 */
  420 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
  421 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
  422 +
  423 + /* rgmii tx clock delay enable */
  424 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  425 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
  426 +
  427 + if (phydev->drv->config)
  428 + phydev->drv->config(phydev);
  429 +
  430 + return 0;
  431 +}
  432 +#endif
  433 +
  434 +#ifdef CONFIG_MXC_SPI
  435 +iomux_v3_cfg_t const ecspi1_pads[] = {
  436 + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  437 + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  438 + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  439 +
  440 + /* CS0 */
  441 + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
  442 +};
  443 +
  444 +void setup_spinor(void)
  445 +{
  446 + imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
  447 + ARRAY_SIZE(ecspi1_pads));
  448 + gpio_request(IMX_GPIO_NR(4, 19), "ecspi1_cs");
  449 + gpio_direction_output(IMX_GPIO_NR(4, 19), 0);
  450 +}
  451 +
  452 +int board_spi_cs_gpio(unsigned bus, unsigned cs)
  453 +{
  454 + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 19)) : -1;
  455 +}
  456 +#endif
  457 +
  458 +#ifdef CONFIG_USB_EHCI_MX7
  459 +#ifndef CONFIG_DM_USB
  460 +iomux_v3_cfg_t const usb_otg1_pads[] = {
  461 + MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  462 +};
  463 +
  464 +iomux_v3_cfg_t const usb_otg2_pads[] = {
  465 + MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  466 +};
  467 +
  468 +static void setup_usb(void)
  469 +{
  470 + imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, ARRAY_SIZE(usb_otg1_pads));
  471 + imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, ARRAY_SIZE(usb_otg2_pads));
  472 +}
  473 +#endif
  474 +#endif
  475 +
  476 +int board_early_init_f(void)
  477 +{
  478 + setup_iomux_uart();
  479 +
  480 +#ifdef CONFIG_SYS_I2C
  481 + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  482 + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  483 +#endif
  484 +
  485 +#ifdef CONFIG_USB_EHCI_MX7
  486 +#ifndef CONFIG_DM_USB
  487 + setup_usb();
  488 +#endif
  489 +#endif
  490 +
  491 + return 0;
  492 +}
  493 +
  494 +int board_init(void)
  495 +{
  496 + /* address of boot parameters */
  497 + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  498 +
  499 + /* Reset peripherals */
  500 + imx_iomux_v3_setup_multiple_pads(per_rst_pads, ARRAY_SIZE(per_rst_pads));
  501 +
  502 + gpio_request(IMX_GPIO_NR(1, 3), "per_rst");
  503 + gpio_direction_output(IMX_GPIO_NR(1, 3), 0);
  504 + udelay(500);
  505 + gpio_set_value(IMX_GPIO_NR(1, 3), 1);
  506 +
  507 +#ifdef CONFIG_MXC_SPI
  508 + setup_spinor();
  509 +#endif
  510 +
  511 +#ifdef CONFIG_FEC_MXC
  512 + setup_fec();
  513 +#endif
  514 +
  515 +#ifdef CONFIG_FSL_QSPI
  516 + board_qspi_init();
  517 +#endif
  518 +
  519 + return 0;
  520 +}
  521 +
  522 +#ifdef CONFIG_CMD_BMODE
  523 +static const struct boot_mode board_boot_modes[] = {
  524 + /* 4 bit bus width */
  525 + {"emmc", MAKE_CFGVAL(0x10, 0x22, 0x00, 0x00)},
  526 + {"sd2", MAKE_CFGVAL(0x10, 0x16, 0x00, 0x00)},
  527 + {"sd3", MAKE_CFGVAL(0x10, 0x1a, 0x00, 0x00)},
  528 + {"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)},
  529 + {NULL, 0},
  530 +};
  531 +#endif
  532 +
  533 +#ifdef CONFIG_POWER
  534 +#define I2C_PMIC 0
  535 +int power_init_board(void)
  536 +{
  537 + struct pmic *p;
  538 + int ret;
  539 + unsigned int reg, rev_id;
  540 +
  541 + ret = power_pfuze3000_init(I2C_PMIC);
  542 + if (ret)
  543 + return ret;
  544 +
  545 + p = pmic_get("PFUZE3000");
  546 + ret = pmic_probe(p);
  547 + if (ret)
  548 + return ret;
  549 +
  550 + pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
  551 + pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
  552 + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
  553 +
  554 + /* disable Low Power Mode during standby mode */
  555 + pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);
  556 + reg |= 0x1;
  557 + pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
  558 +
  559 + /* SW1A/1B mode set to APS/APS */
  560 + reg = 0x8;
  561 + pmic_reg_write(p, PFUZE3000_SW1AMODE, reg);
  562 + pmic_reg_write(p, PFUZE3000_SW1BMODE, reg);
  563 +
  564 + /* SW1A/1B standby voltage set to 0.975V */
  565 + reg = 0xb;
  566 + pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
  567 + pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
  568 +
  569 + /* set SW1B normal voltage to 0.975V */
  570 + pmic_reg_read(p, PFUZE3000_SW1BVOLT, &reg);
  571 + reg &= ~0x1f;
  572 + reg |= PFUZE3000_SW1AB_SETP(9750);
  573 + pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
  574 +
  575 + return 0;
  576 +}
  577 +#elif defined(CONFIG_DM_PMIC_PFUZE100)
  578 +int power_init_board(void)
  579 +{
  580 + struct udevice *dev;
  581 + int ret, dev_id, rev_id, reg;
  582 +
  583 + ret = pmic_get("pfuze3000", &dev);
  584 + if (ret == -ENODEV)
  585 + return 0;
  586 + if (ret != 0)
  587 + return ret;
  588 +
  589 + dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
  590 + rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
  591 + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
  592 +
  593 + /* disable Low Power Mode during standby mode */
  594 + reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
  595 + reg |= 0x1;
  596 + pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
  597 +
  598 + /* SW1A/1B mode set to APS/APS */
  599 + reg = 0x8;
  600 + pmic_reg_write(dev, PFUZE3000_SW1AMODE, reg);
  601 + pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg);
  602 +
  603 + /* SW1A/1B standby voltage set to 0.975V */
  604 + reg = 0xb;
  605 + pmic_reg_write(dev, PFUZE3000_SW1ASTBY, reg);
  606 + pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg);
  607 +
  608 + /* set SW1B normal voltage to 0.975V */
  609 + reg = pmic_reg_read(dev, PFUZE3000_SW1BVOLT);
  610 + reg &= ~0x1f;
  611 + reg |= PFUZE3000_SW1AB_SETP(9750);
  612 + pmic_reg_write(dev, PFUZE3000_SW1BVOLT, reg);
  613 +
  614 + return 0;
  615 +}
  616 +#endif
  617 +
  618 +int board_late_init(void)
  619 +{
  620 +#ifdef CONFIG_CMD_BMODE
  621 + add_board_boot_modes(board_boot_modes);
  622 +#endif
  623 +
  624 +#ifdef CONFIG_ENV_IS_IN_MMC
  625 + board_late_mmc_env_init();
  626 +#endif
  627 +
  628 + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  629 +
  630 + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
  631 +
  632 + return 0;
  633 +}
  634 +
  635 +u32 get_board_rev(void)
  636 +{
  637 + return get_cpu_rev();
  638 +}
  639 +
  640 +int checkboard(void)
  641 +{
  642 + puts("Board: MX7D 19x19 DDR3 ARM2\n");
  643 +
  644 + return 0;
  645 +}
board/freescale/mx7d_19x19_ddr3_arm2/plugin.S
Diff comments   View file @ 1c0e03d
  1 +/*
  2 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <config.h>
  8 +
  9 +/* DDR script */
  10 +.macro imx7d_ddrphy_latency_setting
  11 + ldr r2, =ANATOP_BASE_ADDR
  12 + ldr r3, [r2, #0x800]
  13 + and r3, r3, #0xFF
  14 + cmp r3, #0x11
  15 + bne NO_DELAY
  16 +
  17 + /*TO 1.1*/
  18 + ldr r1, =0x00000dee
  19 + str r1, [r0, #0x9c]
  20 + ldr r1, =0x18181818
  21 + str r1, [r0, #0x7c]
  22 + ldr r1, =0x18181818
  23 + str r1, [r0, #0x80]
  24 + ldr r1, =0x40401818
  25 + str r1, [r0, #0x84]
  26 + ldr r1, =0x00000040
  27 + str r1, [r0, #0x88]
  28 + ldr r1, =0x40404040
  29 + str r1, [r0, #0x6c]
  30 + b TUNE_END
  31 +
  32 +NO_DELAY:
  33 + /*TO 1.0*/
  34 + ldr r1, =0x00000b24
  35 + str r1, [r0, #0x9c]
  36 +
  37 +TUNE_END:
  38 +.endm
  39 +
  40 +.macro imx7d_ddr_freq_setting
  41 + ldr r2, =ANATOP_BASE_ADDR
  42 + ldr r3, [r2, #0x800]
  43 + and r3, r3, #0xFF
  44 + cmp r3, #0x11
  45 + bne FREQ_DEFAULT_533
  46 +
  47 + /* Change to 400Mhz for TO1.1 */
  48 + ldr r0, =ANATOP_BASE_ADDR
  49 + ldr r1, =0x70
  50 + ldr r2, =0x00703021
  51 + str r2, [r0, r1]
  52 + ldr r1, =0x90
  53 + ldr r2, =0x0
  54 + str r2, [r0, r1]
  55 + ldr r1, =0x70
  56 + ldr r2, =0x00603021
  57 + str r2, [r0, r1]
  58 +
  59 + ldr r3, =0x80000000
  60 +wait_lock:
  61 + ldr r2, [r0, r1]
  62 + and r2, r3
  63 + cmp r2, r3
  64 + bne wait_lock
  65 +
  66 + ldr r0, =CCM_BASE_ADDR
  67 + ldr r1, =0x9880
  68 + ldr r2, =0x1
  69 + str r2, [r0, r1]
  70 +
  71 +FREQ_DEFAULT_533:
  72 +.endm
  73 +
  74 +.macro imx7d_19x19_ddr3_arm2_ddr_setting
  75 + imx7d_ddr_freq_setting
  76 +
  77 + /* Configure ocram_epdc */
  78 + ldr r0, =IOMUXC_GPR_BASE_ADDR
  79 + ldr r1, =0x4f400005
  80 + str r1, [r0, #0x4]
  81 +
  82 + /* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */
  83 + ldr r0, =ANATOP_BASE_ADDR
  84 + ldr r1, =(0x1 << 30)
  85 + str r1, [r0, #0x388]
  86 + str r1, [r0, #0x384]
  87 +
  88 + ldr r0, =SRC_BASE_ADDR
  89 + ldr r1, =0x2
  90 + ldr r2, =0x1000
  91 + str r1, [r0, r2]
  92 +
  93 + ldr r0, =DDRC_IPS_BASE_ADDR
  94 + ldr r1, =0x01040001
  95 + str r1, [r0]
  96 + ldr r1, =0x80400003
  97 + str r1, [r0, #0x1a0]
  98 + ldr r1, =0x00100020
  99 + str r1, [r0, #0x1a4]
  100 + ldr r1, =0x80100004
  101 + str r1, [r0, #0x1a8]
  102 + ldr r1, =0x00400046
  103 + str r1, [r0, #0x64]
  104 + ldr r1, =0x1
  105 + str r1, [r0, #0x490]
  106 + ldr r1, =0x00020001
  107 + str r1, [r0, #0xd0]
  108 + ldr r1, =0x00690000
  109 + str r1, [r0, #0xd4]
  110 + ldr r1, =0x09300004
  111 + str r1, [r0, #0xdc]
  112 + ldr r1, =0x04080000
  113 + str r1, [r0, #0xe0]
  114 + ldr r1, =0x00100004
  115 + str r1, [r0, #0xe4]
  116 + ldr r1, =0x33f
  117 + str r1, [r0, #0xf4]
  118 + ldr r1, =0x09081109
  119 + str r1, [r0, #0x100]
  120 + ldr r1, =0x0007020d
  121 + str r1, [r0, #0x104]
  122 + ldr r1, =0x03040407
  123 + str r1, [r0, #0x108]
  124 + ldr r1, =0x00002006
  125 + str r1, [r0, #0x10c]
  126 + ldr r1, =0x04020205
  127 + str r1, [r0, #0x110]
  128 + ldr r1, =0x03030202
  129 + str r1, [r0, #0x114]
  130 + ldr r1, =0x00000803
  131 + str r1, [r0, #0x120]
  132 + ldr r1, =0x00800020
  133 + str r1, [r0, #0x180]
  134 + ldr r1, =0x02000100
  135 + str r1, [r0, #0x184]
  136 + ldr r1, =0x02098204
  137 + str r1, [r0, #0x190]
  138 + ldr r1, =0x00030303
  139 + str r1, [r0, #0x194]
  140 +
  141 + ldr r1, =0x00000016
  142 + str r1, [r0, #0x200]
  143 + ldr r1, =0x00080808
  144 + str r1, [r0, #0x204]
  145 + ldr r1, =0x00000f0f
  146 + str r1, [r0, #0x210]
  147 + ldr r1, =0x07070707
  148 + str r1, [r0, #0x214]
  149 + ldr r1, =0x0f070707
  150 + str r1, [r0, #0x218]
  151 +
  152 + ldr r1, =0x06000604
  153 + str r1, [r0, #0x240]
  154 + ldr r1, =0x00000001
  155 + str r1, [r0, #0x244]
  156 +
  157 + ldr r0, =SRC_BASE_ADDR
  158 + mov r1, #0x0
  159 + ldr r2, =0x1000
  160 + str r1, [r0, r2]
  161 +
  162 + ldr r0, =DDRPHY_IPS_BASE_ADDR
  163 + ldr r1, =0x17420f40
  164 + str r1, [r0]
  165 + ldr r1, =0x10210100
  166 + str r1, [r0, #0x4]
  167 + ldr r1, =0x00060807
  168 + str r1, [r0, #0x10]
  169 + ldr r1, =0x1010007e
  170 + str r1, [r0, #0xb0]
  171 + imx7d_ddrphy_latency_setting
  172 + ldr r1, =0x08080808
  173 + str r1, [r0, #0x20]
  174 + ldr r1, =0x08080808
  175 + str r1, [r0, #0x30]
  176 + ldr r1, =0x01000010
  177 + str r1, [r0, #0x50]
  178 +
  179 + ldr r1, =0x0e407304
  180 + str r1, [r0, #0xc0]
  181 + ldr r1, =0x0e447304
  182 + str r1, [r0, #0xc0]
  183 + ldr r1, =0x0e447306
  184 + str r1, [r0, #0xc0]
  185 +
  186 +wait_zq:
  187 + ldr r1, [r0, #0xc4]
  188 + tst r1, #0x1
  189 + beq wait_zq
  190 +
  191 + ldr r1, =0x0e407304
  192 + str r1, [r0, #0xc0]
  193 +
  194 + ldr r0, =CCM_BASE_ADDR
  195 + mov r1, #0x0
  196 + ldr r2, =0x4130
  197 + str r1, [r0, r2]
  198 + ldr r0, =IOMUXC_GPR_BASE_ADDR
  199 + mov r1, #0x178
  200 + str r1, [r0, #0x20]
  201 + ldr r0, =CCM_BASE_ADDR
  202 + mov r1, #0x2
  203 + ldr r2, =0x4130
  204 + str r1, [r0, r2]
  205 + ldr r0, =DDRPHY_IPS_BASE_ADDR
  206 + ldr r1, =0x0000000f
  207 + str r1, [r0, #0x18]
  208 +
  209 + ldr r0, =DDRC_IPS_BASE_ADDR
  210 +wait_stat:
  211 + ldr r1, [r0, #0x4]
  212 + tst r1, #0x1
  213 + beq wait_stat
  214 +.endm
  215 +
  216 +.macro imx7_clock_gating
  217 +.endm
  218 +
  219 +.macro imx7_qos_setting
  220 +.endm
  221 +
  222 +.macro imx7_ddr_setting
  223 + imx7d_19x19_ddr3_arm2_ddr_setting
  224 +.endm
  225 +
  226 +/* include the common plugin code here */
  227 +#include <asm/arch/mx7_plugin.S>
board/freescale/mx7d_19x19_lpddr3_arm2/Kconfig
Diff comments   View file @ 1c0e03d
  1 +if TARGET_MX7D_19X19_LPDDR3_ARM2 || TARGET_MX7D_19X19_LPDDR2_ARM2
  2 +
  3 +config SYS_BOARD
  4 + default "mx7d_19x19_lpddr3_arm2"
  5 +
  6 +config SYS_VENDOR
  7 + default "freescale"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "mx7d_19x19_lpddr3_arm2"
  11 +
  12 +config SYS_TEXT_BASE
  13 + default 0x87800000
  14 +
  15 +config NOR
  16 + bool "Support for NOR flash"
  17 + help
  18 + The i.MX SoC supports having a NOR flash connected to the WEIM.
  19 + Need to set this for NOR_BOOT.
  20 +endif
board/freescale/mx7d_19x19_lpddr3_arm2/Makefile
Diff comments   View file @ 1c0e03d
  1 +# (C) Copyright 2015 Freescale Semiconductor, Inc.
  2 +#
  3 +# SPDX-License-Identifier: GPL-2.0+
  4 +#
  5 +
  6 +obj-y := mx7d_19x19_lpddr3_arm2.o
board/freescale/mx7d_19x19_lpddr3_arm2/imximage.cfg
Diff comments   View file @ 1c0e03d
  1 +/*
  2 + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Refer docs/README.imxmage for more details about how-to configure
  7 + * and create imximage boot image
  8 + *
  9 + * The syntax is taken as close as possible with the kwbimage
  10 + */
  11 +
  12 +#define __ASSEMBLY__
  13 +#include <config.h>
  14 +
  15 +/* image version */
  16 +
  17 +IMAGE_VERSION 2
  18 +
  19 +BOOT_FROM sd
  20 +
  21 +#ifdef CONFIG_USE_IMXIMG_PLUGIN
  22 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  23 +PLUGIN board/freescale/mx7d_19x19_lpddr3_arm2/plugin.bin 0x00910000
  24 +#else
  25 +
  26 +#ifdef CONFIG_SECURE_BOOT
  27 +CSF CONFIG_CSF_SIZE
  28 +#endif
  29 +
  30 +/*
  31 + * Device Configuration Data (DCD)
  32 + *
  33 + * Each entry must have the format:
  34 + * Addr-type Address Value
  35 + *
  36 + * where:
  37 + * Addr-type register length (1,2 or 4 bytes)
  38 + * Address absolute address of the register
  39 + * value value to be stored in the register
  40 + */
  41 +
  42 +DATA 4 0x30340004 0x4F400005
  43 +
  44 +DATA 4 0x30391000 0x00000002
  45 +DATA 4 0x307a0000 0x03040008
  46 +DATA 4 0x307a0064 0x00200038
  47 +DATA 4 0x307a0490 0x00000001
  48 +DATA 4 0x307a00d0 0x00350001
  49 +DATA 4 0x307a00dc 0x00c3000a
  50 +DATA 4 0x307a00e0 0x00010000
  51 +DATA 4 0x307a00e4 0x00110006
  52 +DATA 4 0x307a00f4 0x0000033f
  53 +DATA 4 0x307a0100 0x0a0e110b
  54 +DATA 4 0x307a0104 0x00020211
  55 +DATA 4 0x307a0108 0x03060708
  56 +DATA 4 0x307a010c 0x00a0500c
  57 +DATA 4 0x307a0110 0x05020307
  58 +DATA 4 0x307a0114 0x02020404
  59 +DATA 4 0x307a0118 0x02020003
  60 +DATA 4 0x307a011c 0x00000202
  61 +DATA 4 0x307a0120 0x00000202
  62 +
  63 +DATA 4 0x307a0180 0x00600018
  64 +DATA 4 0x307a0184 0x00e00100
  65 +DATA 4 0x307a0190 0x02098205
  66 +DATA 4 0x307a0194 0x00060303
  67 +DATA 4 0x307a01a0 0x80400003
  68 +DATA 4 0x307a01a4 0x00100020
  69 +DATA 4 0x307a01a8 0x80100004
  70 +
  71 +DATA 4 0x307a0200 0x00000016
  72 +DATA 4 0x307a0204 0x00090909
  73 +DATA 4 0x307a0210 0x00000f00
  74 +DATA 4 0x307a0214 0x08080808
  75 +DATA 4 0x307a0218 0x0f0f0808
  76 +
  77 +DATA 4 0x307a0240 0x06000600
  78 +DATA 4 0x307a0244 0x00000000
  79 +DATA 4 0x30391000 0x00000000
  80 +DATA 4 0x30790000 0x17421e40
  81 +DATA 4 0x30790004 0x10210100
  82 +DATA 4 0x30790008 0x00010000
  83 +DATA 4 0x30790010 0x0007080c
  84 +DATA 4 0x307900b0 0x1010007e
  85 +
  86 +DATA 4 0x3079001C 0x01010000
  87 +DATA 4 0x3079009c 0x00000b24
  88 +
  89 +DATA 4 0x30790030 0x06060606
  90 +DATA 4 0x30790020 0x0a0a0a0a
  91 +DATA 4 0x30790050 0x01000008
  92 +DATA 4 0x30790050 0x00000008
  93 +DATA 4 0x30790018 0x0000000f
  94 +DATA 4 0x307900c0 0x0e487304
  95 +DATA 4 0x307900c0 0x0e4c7304
  96 +DATA 4 0x307900c0 0x0e4c7306
  97 +CHECK_BITS_SET 4 0x307900c4 0x1
  98 +
  99 +DATA 4 0x307900c0 0x0e487304
  100 +
  101 +DATA 4 0x30384130 0x00000000
  102 +DATA 4 0x30340020 0x00000178
  103 +DATA 4 0x30384130 0x00000002
  104 +
  105 +CHECK_BITS_SET 4 0x307a0004 0x1
  106 +#endif
board/freescale/mx7d_19x19_lpddr3_arm2/imximage_TO_1_1.cfg
Diff comments   View file @ 1c0e03d
  1 +/*
  2 + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Refer docs/README.imxmage for more details about how-to configure
  7 + * and create imximage boot image
  8 + *
  9 + * The syntax is taken as close as possible with the kwbimage
  10 + */
  11 +
  12 +#define __ASSEMBLY__
  13 +#include <config.h>
  14 +
  15 +/* image version */
  16 +
  17 +IMAGE_VERSION 2
  18 +
  19 +/*
  20 + * Boot Device : one of
  21 + * spi/sd/nand/onenand, qspi/nor
  22 + */
  23 +
  24 +BOOT_FROM sd
  25 +
  26 +#ifdef CONFIG_USE_IMXIMG_PLUGIN
  27 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  28 +PLUGIN board/freescale/mx7d_19x19_lpddr3_arm2/plugin.bin 0x00910000
  29 +#else
  30 +
  31 +#ifdef CONFIG_SECURE_BOOT
  32 +CSF CONFIG_CSF_SIZE
  33 +#endif
  34 +
  35 +/*
  36 + * Device Configuration Data (DCD)
  37 + *
  38 + * Each entry must have the format:
  39 + * Addr-type Address Value
  40 + *
  41 + * where:
  42 + * Addr-type register length (1,2 or 4 bytes)
  43 + * Address absolute address of the register
  44 + * value value to be stored in the register
  45 + */
  46 +
  47 +DATA 4 0x30340004 0x4F400005
  48 +
  49 +DATA 4 0x30391000 0x00000002
  50 +DATA 4 0x307a0000 0x03040008
  51 +DATA 4 0x307a0064 0x00200038
  52 +DATA 4 0x307a0490 0x00000001
  53 +DATA 4 0x307a00d0 0x00350001
  54 +DATA 4 0x307a00dc 0x00c3000a
  55 +DATA 4 0x307a00e0 0x00010000
  56 +DATA 4 0x307a00e4 0x00110006
  57 +DATA 4 0x307a00f4 0x0000033f
  58 +DATA 4 0x307a0100 0x0a0e110b
  59 +DATA 4 0x307a0104 0x00020211
  60 +DATA 4 0x307a0108 0x03060708
  61 +DATA 4 0x307a010c 0x00a0500c
  62 +DATA 4 0x307a0110 0x05020307
  63 +DATA 4 0x307a0114 0x02020404
  64 +DATA 4 0x307a0118 0x02020003
  65 +DATA 4 0x307a011c 0x00000202
  66 +DATA 4 0x307a0120 0x00000202
  67 +
  68 +DATA 4 0x307a0180 0x00600018
  69 +DATA 4 0x307a0184 0x00e00100
  70 +DATA 4 0x307a0190 0x02098205
  71 +DATA 4 0x307a0194 0x00060303
  72 +DATA 4 0x307a01a0 0x80400003
  73 +DATA 4 0x307a01a4 0x00100020
  74 +DATA 4 0x307a01a8 0x80100004
  75 +
  76 +DATA 4 0x307a0200 0x00000016
  77 +DATA 4 0x307a0204 0x00090909
  78 +DATA 4 0x307a0210 0x00000f00
  79 +DATA 4 0x307a0214 0x08080808
  80 +DATA 4 0x307a0218 0x0f0f0808
  81 +
  82 +DATA 4 0x307a0240 0x06000601
  83 +DATA 4 0x307a0244 0x00000000
  84 +DATA 4 0x30391000 0x00000000
  85 +DATA 4 0x30790000 0x17421e40
  86 +DATA 4 0x30790004 0x10210100
  87 +DATA 4 0x30790008 0x00010000
  88 +DATA 4 0x30790010 0x0007080c
  89 +DATA 4 0x3079007c 0x1c1c1c1c
  90 +DATA 4 0x30790080 0x1c1c1c1c
  91 +DATA 4 0x30790084 0x30301c1c
  92 +DATA 4 0x30790088 0x00000030
  93 +DATA 4 0x3079006c 0x30303030
  94 +DATA 4 0x307900b0 0x1010007e
  95 +
  96 +DATA 4 0x3079001C 0x01010000
  97 +DATA 4 0x3079009c 0x0db60d6e
  98 +
  99 +DATA 4 0x30790030 0x06060606
  100 +DATA 4 0x30790020 0x0a0a0a0a
  101 +DATA 4 0x30790050 0x01000008
  102 +DATA 4 0x30790050 0x00000008
  103 +DATA 4 0x30790018 0x0000000f
  104 +DATA 4 0x307900c0 0x1e487304
  105 +DATA 4 0x307900c0 0x1e487304
  106 +DATA 4 0x307900c0 0x1e487306
  107 +DATA 4 0x307900c0 0x1e4c7304
  108 +CHECK_BITS_SET 4 0x307900c4 0x1
  109 +
  110 +DATA 4 0x307900c0 0x1e487304
  111 +
  112 +DATA 4 0x30384130 0x00000000
  113 +DATA 4 0x30340020 0x00000178
  114 +DATA 4 0x30384130 0x00000002
  115 +
  116 +CHECK_BITS_SET 4 0x307a0004 0x1
  117 +#endif
board/freescale/mx7d_19x19_lpddr3_arm2/imximage_lpddr2.cfg
Diff comments   View file @ 1c0e03d
  1 +/*
  2 + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Refer docs/README.imxmage for more details about how-to configure
  7 + * and create imximage boot image
  8 + *
  9 + * The syntax is taken as close as possible with the kwbimage
  10 + */
  11 +
  12 +#define __ASSEMBLY__
  13 +#include <config.h>
  14 +
  15 +/* image version */
  16 +
  17 +IMAGE_VERSION 2
  18 +
  19 +/*
  20 + * Boot Device : one of
  21 + * spi/sd/nand/onenand, qspi/nor
  22 + */
  23 +
  24 +#ifdef CONFIG_SYS_BOOT_QSPI
  25 +BOOT_FROM qspi
  26 +#elif defined(CONFIG_SYS_BOOT_EIMNOR)
  27 +BOOT_FROM nor
  28 +#else
  29 +BOOT_FROM sd
  30 +#endif
  31 +
  32 +#ifdef CONFIG_USE_PLUGIN
  33 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  34 +PLUGIN board/freescale/mx7d_19x19_lpddr3_arm2/plugin.bin 0x00910000
  35 +#else
  36 +
  37 +#ifdef CONFIG_SECURE_BOOT
  38 +CSF CONFIG_CSF_SIZE
  39 +#endif
  40 +
  41 +/*
  42 + * Device Configuration Data (DCD)
  43 + *
  44 + * Each entry must have the format:
  45 + * Addr-type Address Value
  46 + *
  47 + * where:
  48 + * Addr-type register length (1,2 or 4 bytes)
  49 + * Address absolute address of the register
  50 + * value value to be stored in the register
  51 + */
  52 +
  53 +DATA 4 0x30340004 0x4F400005
  54 +
  55 +DATA 4 0x30391000 0x00000002
  56 +DATA 4 0x307a0000 0x03020004
  57 +DATA 4 0x307a01a0 0x80400003
  58 +DATA 4 0x307a01a4 0x00100020
  59 +DATA 4 0x307a01a8 0x80100004
  60 +DATA 4 0x307a0064 0x00200023
  61 +DATA 4 0x307a0490 0x00000001
  62 +DATA 4 0x307a00d0 0x00350001
  63 +DATA 4 0x307a00d8 0x00001105
  64 +DATA 4 0x307a00dc 0x00c20006
  65 +DATA 4 0x307a00e0 0x00020000
  66 +DATA 4 0x307a00e4 0x00110006
  67 +DATA 4 0x307a00f4 0x0000033f
  68 +DATA 4 0x307a0100 0x080e110b
  69 +DATA 4 0x307a0104 0x00020211
  70 +DATA 4 0x307a0108 0x02040706
  71 +DATA 4 0x307a010c 0x00504000
  72 +DATA 4 0x307a0110 0x05010307
  73 +DATA 4 0x307a0114 0x02020404
  74 +DATA 4 0x307a0118 0x02020003
  75 +DATA 4 0x307a011c 0x00000202
  76 +DATA 4 0x307a0120 0x00000202
  77 +
  78 +DATA 4 0x307a0180 0x00600018
  79 +DATA 4 0x307a0184 0x00e00100
  80 +DATA 4 0x307a0190 0x02098203
  81 +DATA 4 0x307a0194 0x00060303
  82 +
  83 +DATA 4 0x307a0200 0x00000015
  84 +DATA 4 0x307a0204 0x00161616
  85 +DATA 4 0x307a0210 0x00000f0f
  86 +DATA 4 0x307a0214 0x04040404
  87 +DATA 4 0x307a0218 0x0f0f0404
  88 +
  89 +DATA 4 0x307a0240 0x06000600
  90 +DATA 4 0x307a0244 0x00000000
  91 +DATA 4 0x30391000 0x00000000
  92 +DATA 4 0x30790000 0x17421640
  93 +DATA 4 0x30790004 0x10210100
  94 +DATA 4 0x30790008 0x00010000
  95 +DATA 4 0x30790010 0x00050408
  96 +DATA 4 0x307900b0 0x1010007e
  97 +
  98 +DATA 4 0x3079001C 0x01010000
  99 +DATA 4 0x3079009C 0x00000d6e
  100 +DATA 4 0x30790018 0x0000000f
  101 +
  102 +DATA 4 0x30790030 0x06060606
  103 +DATA 4 0x30790020 0x0a0a0a0a
  104 +DATA 4 0x30790050 0x01000008
  105 +DATA 4 0x30790050 0x00000008
  106 +DATA 4 0x307900c0 0x0e487304
  107 +DATA 4 0x307900c0 0x0e4c7304
  108 +DATA 4 0x307900c0 0x0e4c7306
  109 +CHECK_BITS_SET 4 0x307900c4 0x1
  110 +
  111 +DATA 4 0x307900c0 0x0e4c7304
  112 +DATA 4 0x307900c0 0x0e487304
  113 +
  114 +DATA 4 0x30384130 0x00000000
  115 +DATA 4 0x30340020 0x000001f8
  116 +DATA 4 0x30384130 0x00000002
  117 +
  118 +CHECK_BITS_SET 4 0x307a0004 0x1
  119 +#endif
board/freescale/mx7d_19x19_lpddr3_arm2/imximage_lpddr2_TO_1_1.cfg
Diff comments   View file @ 1c0e03d
  1 +/*
  2 + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Refer docs/README.imxmage for more details about how-to configure
  7 + * and create imximage boot image
  8 + *
  9 + * The syntax is taken as close as possible with the kwbimage
  10 + */
  11 +
  12 +#define __ASSEMBLY__
  13 +#include <config.h>
  14 +
  15 +/* image version */
  16 +
  17 +IMAGE_VERSION 2
  18 +
  19 +/*
  20 + * Boot Device : one of
  21 + * spi/sd/nand/onenand, qspi/nor
  22 + */
  23 +
  24 +#ifdef CONFIG_SYS_BOOT_QSPI
  25 +BOOT_FROM qspi
  26 +#elif defined(CONFIG_SYS_BOOT_EIMNOR)
  27 +BOOT_FROM nor
  28 +#else
  29 +BOOT_FROM sd
  30 +#endif
  31 +
  32 +#ifdef CONFIG_USE_PLUGIN
  33 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  34 +PLUGIN board/freescale/mx7d_19x19_lpddr3_arm2/plugin.bin 0x00910000
  35 +#else
  36 +
  37 +#ifdef CONFIG_SECURE_BOOT
  38 +CSF CONFIG_CSF_SIZE
  39 +#endif
  40 +
  41 +/*
  42 + * Device Configuration Data (DCD)
  43 + *
  44 + * Each entry must have the format:
  45 + * Addr-type Address Value
  46 + *
  47 + * where:
  48 + * Addr-type register length (1,2 or 4 bytes)
  49 + * Address absolute address of the register
  50 + * value value to be stored in the register
  51 + */
  52 +
  53 +DATA 4 0x30340004 0x4F400005
  54 +
  55 +DATA 4 0x30391000 0x00000002
  56 +DATA 4 0x307a0000 0x03020004
  57 +DATA 4 0x307a01a0 0x80400003
  58 +DATA 4 0x307a01a4 0x00100020
  59 +DATA 4 0x307a01a8 0x80100004
  60 +DATA 4 0x307a0064 0x00200023
  61 +DATA 4 0x307a0490 0x00000001
  62 +DATA 4 0x307a00d0 0x00350001
  63 +DATA 4 0x307a00d8 0x00001105
  64 +DATA 4 0x307a00dc 0x00c20006
  65 +DATA 4 0x307a00e0 0x00020000
  66 +DATA 4 0x307a00e4 0x00110006
  67 +DATA 4 0x307a00f4 0x0000033f
  68 +DATA 4 0x307a0100 0x080e110b
  69 +DATA 4 0x307a0104 0x00020211
  70 +DATA 4 0x307a0108 0x02040706
  71 +DATA 4 0x307a010c 0x00504000
  72 +DATA 4 0x307a0110 0x05010307
  73 +DATA 4 0x307a0114 0x02020404
  74 +DATA 4 0x307a0118 0x02020003
  75 +DATA 4 0x307a011c 0x00000202
  76 +DATA 4 0x307a0120 0x00000202
  77 +
  78 +DATA 4 0x307a0180 0x00600018
  79 +DATA 4 0x307a0184 0x00e00100
  80 +DATA 4 0x307a0190 0x02098203
  81 +DATA 4 0x307a0194 0x00060303
  82 +
  83 +DATA 4 0x307a0200 0x00000015
  84 +DATA 4 0x307a0204 0x00161616
  85 +DATA 4 0x307a0210 0x00000f0f
  86 +DATA 4 0x307a0214 0x04040404
  87 +DATA 4 0x307a0218 0x0f0f0404
  88 +
  89 +DATA 4 0x307a0240 0x06000600
  90 +DATA 4 0x307a0244 0x00000000
  91 +DATA 4 0x30391000 0x00000000
  92 +DATA 4 0x30790000 0x17421640
  93 +DATA 4 0x30790004 0x10210100
  94 +DATA 4 0x30790008 0x00010000
  95 +DATA 4 0x30790010 0x00050408
  96 +DATA 4 0x307900b0 0x1010007e
  97 +
  98 +DATA 4 0x3079001C 0x01010000
  99 +DATA 4 0x3079009C 0x00000dee
  100 +DATA 4 0x3079007c 0x08080808
  101 +DATA 4 0x30790080 0x08080808
  102 +DATA 4 0x30790084 0x0a0a0808
  103 +DATA 4 0x30790088 0x0000000a
  104 +DATA 4 0x3079006c 0x0a0a0a0a
  105 +DATA 4 0x30790018 0x0000000f
  106 +
  107 +DATA 4 0x30790030 0x06060606
  108 +DATA 4 0x30790020 0x0a0a0a0a
  109 +DATA 4 0x30790050 0x01000008
  110 +DATA 4 0x30790050 0x00000008
  111 +DATA 4 0x307900c0 0x0e487304
  112 +DATA 4 0x307900c0 0x0e4c7304
  113 +DATA 4 0x307900c0 0x0e4c7306
  114 +CHECK_BITS_SET 4 0x307900c4 0x1
  115 +
  116 +DATA 4 0x307900c0 0x0e4c7304
  117 +DATA 4 0x307900c0 0x0e487304
  118 +
  119 +DATA 4 0x30384130 0x00000000
  120 +DATA 4 0x30340020 0x000001f8
  121 +DATA 4 0x30384130 0x00000002
  122 +
  123 +CHECK_BITS_SET 4 0x307a0004 0x1
  124 +#endif
board/freescale/mx7d_19x19_lpddr3_arm2/mx7d_19x19_lpddr3_arm2.c
Diff comments   View file @ 1c0e03d
  1 +/*
  2 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <asm/arch/clock.h>
  8 +#include <asm/arch/imx-regs.h>
  9 +#include <asm/arch/mx7-pins.h>
  10 +#include <asm/arch/sys_proto.h>
  11 +#include <asm/gpio.h>
  12 +#include <asm/mach-imx/iomux-v3.h>
  13 +#include <asm/mach-imx/boot_mode.h>
  14 +#include <asm/io.h>
  15 +#include <linux/sizes.h>
  16 +#include <common.h>
  17 +#include <fsl_esdhc.h>
  18 +#include <mmc.h>
  19 +#include <miiphy.h>
  20 +#include <netdev.h>
  21 +#include <power/pmic.h>
  22 +#include <power/pfuze3000_pmic.h>
  23 +#include "../common/pfuze.h"
  24 +#ifdef CONFIG_SYS_I2C
  25 +#include <i2c.h>
  26 +#include <asm/mach-imx/mxc_i2c.h>
  27 +#endif
  28 +#include <asm/arch/crm_regs.h>
  29 +
  30 +DECLARE_GLOBAL_DATA_PTR;
  31 +
  32 +#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
  33 + PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
  34 +
  35 +#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
  36 + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
  37 +
  38 +#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
  39 +#define ENET_PAD_CTRL_MII (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
  40 +
  41 +#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
  42 +
  43 +#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
  44 + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
  45 +
  46 +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
  47 + PAD_CTL_DSE_3P3V_49OHM)
  48 +
  49 +#define QSPI_PAD_CTRL \
  50 + (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
  51 +
  52 +#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
  53 +
  54 +#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
  55 +
  56 +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
  57 +
  58 +#define WEIM_NOR_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | \
  59 + PAD_CTL_PUS_PU100KOHM)
  60 +
  61 +
  62 +#ifdef CONFIG_SYS_I2C
  63 +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  64 +/* I2C1 for PMIC */
  65 +struct i2c_pads_info i2c_pad_info1 = {
  66 + .scl = {
  67 + .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
  68 + .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
  69 + .gp = IMX_GPIO_NR(4, 8),
  70 + },
  71 + .sda = {
  72 + .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,
  73 + .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,
  74 + .gp = IMX_GPIO_NR(4, 9),
  75 + },
  76 +};
  77 +
  78 +/* I2C2 */
  79 +struct i2c_pads_info i2c_pad_info2 = {
  80 + .scl = {
  81 + .i2c_mode = MX7D_PAD_I2C2_SCL__I2C2_SCL | PC,
  82 + .gpio_mode = MX7D_PAD_I2C2_SCL__GPIO4_IO10 | PC,
  83 + .gp = IMX_GPIO_NR(4, 10),
  84 + },
  85 + .sda = {
  86 + .i2c_mode = MX7D_PAD_I2C2_SDA__I2C2_SDA | PC,
  87 + .gpio_mode = MX7D_PAD_I2C2_SDA__GPIO4_IO11 | PC,
  88 + .gp = IMX_GPIO_NR(4, 11),
  89 + },
  90 +};
  91 +#endif
  92 +
  93 +int dram_init(void)
  94 +{
  95 + gd->ram_size = PHYS_SDRAM_SIZE;
  96 +
  97 + return 0;
  98 +}
  99 +
  100 +static iomux_v3_cfg_t const uart1_pads[] = {
  101 + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  102 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  103 +};
  104 +
  105 +static iomux_v3_cfg_t const usdhc1_pads[] = {
  106 + MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  107 + MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  108 + MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  109 + MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  110 + MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  111 + MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  112 +
  113 + MX7D_PAD_GPIO1_IO08__SD1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  114 +
  115 + MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  116 + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  117 +};
  118 +
  119 +#ifdef CONFIG_MTD_NOR_FLASH
  120 +static iomux_v3_cfg_t const eimnor_pads[] = {
  121 + MX7D_PAD_LCD_DATA00__EIM_DATA0 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  122 + MX7D_PAD_LCD_DATA01__EIM_DATA1 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  123 + MX7D_PAD_LCD_DATA02__EIM_DATA2 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  124 + MX7D_PAD_LCD_DATA03__EIM_DATA3 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  125 + MX7D_PAD_LCD_DATA04__EIM_DATA4 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  126 + MX7D_PAD_LCD_DATA05__EIM_DATA5 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  127 + MX7D_PAD_LCD_DATA06__EIM_DATA6 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  128 + MX7D_PAD_LCD_DATA07__EIM_DATA7 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  129 + MX7D_PAD_LCD_DATA08__EIM_DATA8 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  130 + MX7D_PAD_LCD_DATA09__EIM_DATA9 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  131 + MX7D_PAD_LCD_DATA10__EIM_DATA10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  132 + MX7D_PAD_LCD_DATA11__EIM_DATA11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  133 + MX7D_PAD_LCD_DATA12__EIM_DATA12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  134 + MX7D_PAD_LCD_DATA13__EIM_DATA13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  135 + MX7D_PAD_LCD_DATA14__EIM_DATA14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  136 + MX7D_PAD_LCD_DATA15__EIM_DATA15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  137 +
  138 + MX7D_PAD_EPDC_DATA00__EIM_AD0 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  139 + MX7D_PAD_EPDC_DATA01__EIM_AD1 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  140 + MX7D_PAD_EPDC_DATA02__EIM_AD2 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  141 + MX7D_PAD_EPDC_DATA03__EIM_AD3 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  142 + MX7D_PAD_EPDC_DATA04__EIM_AD4 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  143 + MX7D_PAD_EPDC_DATA05__EIM_AD5 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  144 + MX7D_PAD_EPDC_DATA06__EIM_AD6 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  145 + MX7D_PAD_EPDC_DATA07__EIM_AD7 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  146 + MX7D_PAD_EPDC_BDR1__EIM_AD8 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  147 + MX7D_PAD_EPDC_PWR_COM__EIM_AD9 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  148 + MX7D_PAD_EPDC_SDCLK__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  149 + MX7D_PAD_EPDC_SDLE__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  150 + MX7D_PAD_EPDC_SDOE__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  151 + MX7D_PAD_EPDC_SDSHR__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  152 + MX7D_PAD_EPDC_SDCE0__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  153 + MX7D_PAD_EPDC_SDCE1__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  154 + MX7D_PAD_EPDC_SDCE2__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  155 + MX7D_PAD_EPDC_SDCE3__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  156 + MX7D_PAD_EPDC_GDCLK__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  157 + MX7D_PAD_EPDC_GDOE__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  158 + MX7D_PAD_EPDC_GDRL__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  159 + MX7D_PAD_EPDC_GDSP__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  160 + MX7D_PAD_EPDC_BDR0__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  161 + MX7D_PAD_LCD_DATA20__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  162 + MX7D_PAD_LCD_DATA21__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  163 + MX7D_PAD_LCD_DATA22__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  164 +
  165 + MX7D_PAD_EPDC_DATA08__EIM_OE | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  166 + MX7D_PAD_EPDC_DATA09__EIM_RW | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  167 + MX7D_PAD_EPDC_DATA10__EIM_CS0_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  168 + MX7D_PAD_EPDC_DATA12__EIM_LBA_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  169 + MX7D_PAD_EPDC_DATA13__EIM_WAIT | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  170 +};
  171 +
  172 +static void eimnor_cs_setup(void)
  173 +{
  174 + writel(0x00000120, WEIM_IPS_BASE_ADDR + 0x090);
  175 + writel(0x00210081, WEIM_IPS_BASE_ADDR + 0x000);
  176 + writel(0x00000001, WEIM_IPS_BASE_ADDR + 0x004);
  177 + writel(0x0e020000, WEIM_IPS_BASE_ADDR + 0x008);
  178 + writel(0x00000000, WEIM_IPS_BASE_ADDR + 0x00c);
  179 + writel(0x0704a040, WEIM_IPS_BASE_ADDR + 0x010);
  180 +}
  181 +
  182 +static void setup_eimnor(void)
  183 +{
  184 + imx_iomux_v3_setup_multiple_pads(eimnor_pads,
  185 + ARRAY_SIZE(eimnor_pads));
  186 +
  187 + eimnor_cs_setup();
  188 +}
  189 +#endif
  190 +
  191 +static iomux_v3_cfg_t const per_rst_pads[] = {
  192 + MX7D_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL),
  193 +};
  194 +
  195 +static iomux_v3_cfg_t const wdog_pads[] = {
  196 + MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY | MUX_PAD_CTRL(NO_PAD_CTRL),
  197 +};
  198 +
  199 +#ifdef CONFIG_FEC_MXC
  200 +static iomux_v3_cfg_t const fec2_pads[] = {
  201 + MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  202 + MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  203 + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  204 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  205 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  206 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  207 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  208 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  209 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  210 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  211 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  212 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  213 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  214 + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  215 +};
  216 +
  217 +static void setup_iomux_fec2(void)
  218 +{
  219 + imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
  220 +}
  221 +#endif
  222 +
  223 +static void setup_iomux_uart(void)
  224 +{
  225 + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  226 +}
  227 +
  228 +#ifdef CONFIG_FSL_QSPI
  229 +#ifndef CONFIG_DM_SPI
  230 +static iomux_v3_cfg_t const quadspi_pads[] = {
  231 + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  232 + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  233 + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  234 + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  235 + MX7D_PAD_EPDC_DATA04__QSPI_A_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  236 + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  237 + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  238 + MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  239 +
  240 + MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  241 + MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  242 + MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  243 + MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  244 + MX7D_PAD_EPDC_DATA12__QSPI_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  245 + MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  246 + MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  247 + MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  248 +
  249 +};
  250 +#endif
  251 +
  252 +int board_qspi_init(void)
  253 +{
  254 +#ifndef CONFIG_DM_SPI
  255 + /* Set the iomux */
  256 + imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
  257 +#endif
  258 +
  259 + /* Set the clock */
  260 + set_clk_qspi();
  261 +
  262 + return 0;
  263 +}
  264 +#endif
  265 +
  266 +#ifdef CONFIG_NAND_MXS
  267 +static iomux_v3_cfg_t const gpmi_pads[] = {
  268 + MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  269 + MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  270 + MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  271 + MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  272 + MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  273 + MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  274 + MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  275 + MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  276 + MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
  277 + MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
  278 + MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  279 + MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  280 + MX7D_PAD_SAI1_MCLK__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  281 + MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  282 + MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  283 + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  284 + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  285 + MX7D_PAD_SAI1_TX_SYNC__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL),
  286 + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
  287 +};
  288 +
  289 +static void setup_gpmi_nand(void)
  290 +{
  291 + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
  292 +
  293 + /*
  294 + * NAND_USDHC_BUS_CLK is set in rom
  295 + */
  296 +
  297 + set_clk_nand();
  298 +
  299 + /*
  300 + * APBH clock root is set in init_esdhc, USDHC3_CLK.
  301 + * There is no clk gate for APBHDMA.
  302 + * No touch here.
  303 + */
  304 +}
  305 +#endif
  306 +
  307 +
  308 +#ifdef CONFIG_FSL_ESDHC
  309 +
  310 +#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0)
  311 +#define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2)
  312 +
  313 +
  314 +static struct fsl_esdhc_cfg usdhc_cfg[1] = {
  315 + {USDHC1_BASE_ADDR, 0, 4},
  316 +};
  317 +
  318 +int board_mmc_getcd(struct mmc *mmc)
  319 +{
  320 + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  321 + int ret = 0;
  322 +
  323 + switch (cfg->esdhc_base) {
  324 + case USDHC1_BASE_ADDR:
  325 + ret = !gpio_get_value(USDHC1_CD_GPIO);
  326 + break;
  327 + }
  328 +
  329 + return ret;
  330 +}
  331 +int board_mmc_init(bd_t *bis)
  332 +{
  333 + int i, ret;
  334 + /*
  335 + * According to the board_mmc_init() the following map is done:
  336 + * (U-boot device node) (Physical Port)
  337 + * mmc0 USDHC1
  338 + */
  339 + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  340 + switch (i) {
  341 + case 0:
  342 + imx_iomux_v3_setup_multiple_pads(
  343 + usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
  344 + gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
  345 + gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr");
  346 + gpio_direction_input(USDHC1_CD_GPIO);
  347 + gpio_direction_output(USDHC1_PWR_GPIO, 0);
  348 + udelay(500);
  349 + gpio_direction_output(USDHC1_PWR_GPIO, 1);
  350 + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  351 + break;
  352 + default:
  353 + printf("Warning: you configured more USDHC controllers"
  354 + "(%d) than supported by the board\n", i + 1);
  355 + return -EINVAL;
  356 + }
  357 +
  358 + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  359 + if (ret) {
  360 + printf("Warning: failed to initialize mmc dev %d\n", i);
  361 + return ret;
  362 + }
  363 + }
  364 +
  365 + return 0;
  366 +}
  367 +#endif
  368 +
  369 +#ifdef CONFIG_FEC_MXC
  370 +int board_eth_init(bd_t *bis)
  371 +{
  372 + int ret;
  373 +
  374 + setup_iomux_fec2();
  375 +
  376 + ret = fecmxc_initialize_multi(bis, 0,
  377 + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
  378 + if (ret)
  379 + printf("FEC1 MXC: %s:failed\n", __func__);
  380 +
  381 + return 0;
  382 +}
  383 +
  384 +static int setup_fec(void)
  385 +{
  386 + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
  387 + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
  388 + int ret;
  389 +
  390 + /* Use 125M anatop REF_CLK for ENET2, clear gpr1[14], gpr1[18]*/
  391 + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
  392 + (IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK |
  393 + IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK), 0);
  394 +
  395 + ret = set_clk_enet(ENET_125MHZ);
  396 + if (ret)
  397 + return ret;
  398 +
  399 + return 0;
  400 +}
  401 +
  402 +
  403 +int board_phy_config(struct phy_device *phydev)
  404 +{
  405 + /* Enable 1.8V(SEL_1P5_1P8_POS_REG) on
  406 + Phy control debug reg 0 */
  407 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
  408 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
  409 +
  410 + /* rgmii tx clock delay enable */
  411 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  412 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
  413 +
  414 + if (phydev->drv->config)
  415 + phydev->drv->config(phydev);
  416 +
  417 + return 0;
  418 +}
  419 +#endif
  420 +
  421 +#ifdef CONFIG_MXC_SPI
  422 +iomux_v3_cfg_t const ecspi1_pads[] = {
  423 + MX7D_PAD_UART3_RX_DATA__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  424 + MX7D_PAD_UART3_TX_DATA__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  425 + MX7D_PAD_UART3_RTS_B__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  426 +
  427 + /* CS0 */
  428 + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL),
  429 +};
  430 +
  431 +void setup_spinor(void)
  432 +{
  433 + imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
  434 + ARRAY_SIZE(ecspi1_pads));
  435 + gpio_direction_output(IMX_GPIO_NR(4, 7), 0);
  436 +}
  437 +
  438 +int board_spi_cs_gpio(unsigned bus, unsigned cs)
  439 +{
  440 + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 7)) : -1;
  441 +}
  442 +#endif
  443 +
  444 +#ifdef CONFIG_USB_EHCI_MX7
  445 +#ifndef CONFIG_DM_USB
  446 +
  447 +iomux_v3_cfg_t const usb_otg1_pads[] = {
  448 + MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  449 +};
  450 +
  451 +iomux_v3_cfg_t const usb_otg2_pads[] = {
  452 + MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  453 +};
  454 +
  455 +static void setup_usb(void)
  456 +{
  457 + imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, ARRAY_SIZE(usb_otg1_pads));
  458 + imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, ARRAY_SIZE(usb_otg2_pads));
  459 +}
  460 +#endif
  461 +#endif
  462 +
  463 +int board_early_init_f(void)
  464 +{
  465 + setup_iomux_uart();
  466 +
  467 +#ifdef CONFIG_SYS_I2C
  468 + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  469 + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  470 +#endif
  471 +
  472 +#ifdef CONFIG_USB_EHCI_MX7
  473 +#ifndef CONFIG_DM_USB
  474 + setup_usb();
  475 +#endif
  476 +#endif
  477 + return 0;
  478 +}
  479 +
  480 +int board_init(void)
  481 +{
  482 + /* address of boot parameters */
  483 + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  484 +
  485 + /* Reset peripherals */
  486 + imx_iomux_v3_setup_multiple_pads(per_rst_pads, ARRAY_SIZE(per_rst_pads));
  487 +
  488 + gpio_request(IMX_GPIO_NR(1, 3), "per rst");
  489 + gpio_direction_output(IMX_GPIO_NR(1, 3) , 0);
  490 + udelay(500);
  491 + gpio_set_value(IMX_GPIO_NR(1, 3), 1);
  492 +
  493 +#ifdef CONFIG_MXC_SPI
  494 + setup_spinor();
  495 +#endif
  496 +
  497 +#ifdef CONFIG_MTD_NOR_FLASH
  498 + setup_eimnor();
  499 +#endif
  500 +
  501 +#ifdef CONFIG_NAND_MXS
  502 + setup_gpmi_nand();
  503 +#endif
  504 +
  505 +#ifdef CONFIG_FEC_MXC
  506 + setup_fec();
  507 +#endif
  508 +
  509 +#ifdef CONFIG_FSL_QSPI
  510 + board_qspi_init();
  511 +#endif
  512 +
  513 + return 0;
  514 +}
  515 +
  516 +#ifdef CONFIG_CMD_BMODE
  517 +static const struct boot_mode board_boot_modes[] = {
  518 + /* 4 bit bus width */
  519 + {"sd1", MAKE_CFGVAL(0x10, 0x12, 0x00, 0x00)},
  520 + {"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)},
  521 + {NULL, 0},
  522 +};
  523 +#endif
  524 +
  525 +#ifdef CONFIG_POWER
  526 +#define I2C_PMIC 0
  527 +int power_init_board(void)
  528 +{
  529 + struct pmic *p;
  530 + int ret;
  531 + unsigned int reg, rev_id;
  532 +
  533 + ret = power_pfuze3000_init(I2C_PMIC);
  534 + if (ret)
  535 + return ret;
  536 +
  537 + p = pmic_get("PFUZE3000");
  538 + ret = pmic_probe(p);
  539 + if (ret)
  540 + return ret;
  541 +
  542 + pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
  543 + pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
  544 + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
  545 +
  546 + /* disable Low Power Mode during standby mode */
  547 + pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);
  548 + reg |= 0x1;
  549 + pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
  550 +
  551 + /* SW1A/1B mode set to APS/APS */
  552 + reg = 0x8;
  553 + pmic_reg_write(p, PFUZE3000_SW1AMODE, reg);
  554 + pmic_reg_write(p, PFUZE3000_SW1BMODE, reg);
  555 +
  556 + /* SW1A/1B standby voltage set to 0.975V */
  557 + reg = 0xb;
  558 + pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
  559 + pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
  560 +
  561 + /* set SW1B normal voltage to 0.975V */
  562 + pmic_reg_read(p, PFUZE3000_SW1BVOLT, &reg);
  563 + reg &= ~0x1f;
  564 + reg |= PFUZE3000_SW1AB_SETP(9750);
  565 + pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
  566 +
  567 + return 0;
  568 +}
  569 +#elif defined(CONFIG_DM_PMIC_PFUZE100)
  570 +int power_init_board(void)
  571 +{
  572 + struct udevice *dev;
  573 + int ret, dev_id, rev_id, reg;
  574 +
  575 + ret = pmic_get("pfuze3000", &dev);
  576 + if (ret == -ENODEV)
  577 + return 0;
  578 + if (ret != 0)
  579 + return ret;
  580 +
  581 + dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
  582 + rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
  583 + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
  584 +
  585 + /* disable Low Power Mode during standby mode */
  586 + reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
  587 + reg |= 0x1;
  588 + pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
  589 +
  590 + /* SW1A/1B mode set to APS/APS */
  591 + reg = 0x8;
  592 + pmic_reg_write(dev, PFUZE3000_SW1AMODE, reg);
  593 + pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg);
  594 +
  595 + /* SW1A/1B standby voltage set to 0.975V */
  596 + reg = 0xb;
  597 + pmic_reg_write(dev, PFUZE3000_SW1ASTBY, reg);
  598 + pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg);
  599 +
  600 + /* set SW1B normal voltage to 0.975V */
  601 + reg = pmic_reg_read(dev, PFUZE3000_SW1BVOLT);
  602 + reg &= ~0x1f;
  603 + reg |= PFUZE3000_SW1AB_SETP(9750);
  604 + pmic_reg_write(dev, PFUZE3000_SW1BVOLT, reg);
  605 +
  606 + return 0;
  607 +}
  608 +#endif
  609 +
  610 +int board_late_init(void)
  611 +{
  612 +#ifdef CONFIG_CMD_BMODE
  613 + add_board_boot_modes(board_boot_modes);
  614 +#endif
  615 +
  616 +#ifdef CONFIG_ENV_IS_IN_MMC
  617 + board_late_mmc_env_init();
  618 +#endif
  619 +
  620 + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  621 +
  622 + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
  623 +
  624 + return 0;
  625 +}
  626 +
  627 +u32 get_board_rev(void)
  628 +{
  629 + return get_cpu_rev();
  630 +}
  631 +
  632 +int checkboard(void)
  633 +{
  634 +#ifdef CONFIG_TARGET_MX7D_19X19_LPDDR2_ARM2
  635 + puts("Board: MX7D 19x19 LPDDR2 ARM2\n");
  636 +#else
  637 + puts("Board: MX7D 19x19 LPDDR3 ARM2\n");
  638 +#endif
  639 + return 0;
  640 +}
board/freescale/mx7d_19x19_lpddr3_arm2/plugin.S
Diff comments   View file @ 1c0e03d
  1 +/*
  2 + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <config.h>
  8 +
  9 +/* DDR script */
  10 +.macro imx7d_ddrphy_lpddr3_latency_setting
  11 + ldr r2, =ANATOP_BASE_ADDR
  12 + ldr r3, [r2, #0x800]
  13 + and r3, r3, #0xFF
  14 + cmp r3, #0x11
  15 + bne TUNE_END
  16 +
  17 + /*TO 1.1*/
  18 + ldr r1, =0x1c1c1c1c
  19 + str r1, [r0, #0x7c]
  20 + ldr r1, =0x1c1c1c1c
  21 + str r1, [r0, #0x80]
  22 + ldr r1, =0x30301c1c
  23 + str r1, [r0, #0x84]
  24 + ldr r1, =0x00000030
  25 + str r1, [r0, #0x88]
  26 + ldr r1, =0x30303030
  27 + str r1, [r0, #0x6c]
  28 +
  29 +TUNE_END:
  30 +.endm
  31 +
  32 +.macro imx7d_ddrphy_lpddr2_latency_setting
  33 + ldr r2, =ANATOP_BASE_ADDR
  34 + ldr r3, [r2, #0x800]
  35 + and r3, r3, #0xFF
  36 + cmp r3, #0x11
  37 + bne NO_DELAY
  38 +
  39 + /*TO 1.1*/
  40 + ldr r1, =0x00000dee
  41 + str r1, [r0, #0x9c]
  42 + ldr r1, =0x08080808
  43 + str r1, [r0, #0x7c]
  44 + ldr r1, =0x08080808
  45 + str r1, [r0, #0x80]
  46 + ldr r1, =0x0a0a0808
  47 + str r1, [r0, #0x84]
  48 + ldr r1, =0x0000000a
  49 + str r1, [r0, #0x88]
  50 + ldr r1, =0x0a0a0a0a
  51 + str r1, [r0, #0x6c]
  52 + b TUNE_END
  53 +
  54 +NO_DELAY:
  55 + /*TO 1.0*/
  56 + ldr r1, =0x00000d6e
  57 + str r1, [r0, #0x9c]
  58 +
  59 +TUNE_END:
  60 +.endm
  61 +
  62 +.macro imx7d_19x19_lpddr3_arm2_setting
  63 + /* Configure ocram_epdc */
  64 + ldr r0, =IOMUXC_GPR_BASE_ADDR
  65 + ldr r1, =0x4f400005
  66 + str r1, [r0, #0x4]
  67 +
  68 + ldr r0, =SRC_BASE_ADDR
  69 + ldr r1, =0x2
  70 + ldr r2, =0x1000
  71 + str r1, [r0, r2]
  72 +
  73 + ldr r0, =DDRC_IPS_BASE_ADDR
  74 + ldr r1, =0x03040008
  75 + str r1, [r0]
  76 + ldr r1, =0x00200038
  77 + str r1, [r0, #0x64]
  78 + ldr r1, =0x1
  79 + str r1, [r0, #0x490]
  80 + ldr r1, =0x00350001
  81 + str r1, [r0, #0xd0]
  82 + ldr r1, =0x00c3000a
  83 + str r1, [r0, #0xdc]
  84 + ldr r1, =0x00010000
  85 + str r1, [r0, #0xe0]
  86 + ldr r1, =0x00110006
  87 + str r1, [r0, #0xe4]
  88 + ldr r1, =0x33f
  89 + str r1, [r0, #0xf4]
  90 + ldr r1, =0x0a0e110b
  91 + str r1, [r0, #0x100]
  92 + ldr r1, =0x00020211
  93 + str r1, [r0, #0x104]
  94 + ldr r1, =0x03060708
  95 + str r1, [r0, #0x108]
  96 + ldr r1, =0x00a0500c
  97 + str r1, [r0, #0x10c]
  98 + ldr r1, =0x05020307
  99 + str r1, [r0, #0x110]
  100 + ldr r1, =0x02020404
  101 + str r1, [r0, #0x114]
  102 + ldr r1, =0x02020003
  103 + str r1, [r0, #0x118]
  104 + ldr r1, =0x00000202
  105 + str r1, [r0, #0x11c]
  106 + ldr r1, =0x00000202
  107 + str r1, [r0, #0x120]
  108 + ldr r1, =0x00600018
  109 + str r1, [r0, #0x180]
  110 + ldr r1, =0x00e00100
  111 + str r1, [r0, #0x184]
  112 + ldr r1, =0x02098205
  113 + str r1, [r0, #0x190]
  114 + ldr r1, =0x00060303
  115 + str r1, [r0, #0x194]
  116 + ldr r1, =0x80400003
  117 + str r1, [r0, #0x1a0]
  118 + ldr r1, =0x00100020
  119 + str r1, [r0, #0x1a4]
  120 + ldr r1, =0x80100004
  121 + str r1, [r0, #0x1a8]
  122 +
  123 + ldr r1, =0x00000016
  124 + str r1, [r0, #0x200]
  125 + ldr r1, =0x00090909
  126 + str r1, [r0, #0x204]
  127 + ldr r1, =0x00000f00
  128 + str r1, [r0, #0x210]
  129 + ldr r1, =0x08080808
  130 + str r1, [r0, #0x214]
  131 + ldr r1, =0x0f0f0808
  132 + str r1, [r0, #0x218]
  133 +
  134 + ldr r1, =0x06000600
  135 + str r1, [r0, #0x240]
  136 + mov r1, #0x0
  137 + str r1, [r0, #0x244]
  138 +
  139 + ldr r0, =SRC_BASE_ADDR
  140 + mov r1, #0x0
  141 + ldr r2, =0x1000
  142 + str r1, [r0, r2]
  143 +
  144 + ldr r0, =DDRPHY_IPS_BASE_ADDR
  145 + ldr r1, =0x17421e40
  146 + str r1, [r0]
  147 + ldr r1, =0x10210100
  148 + str r1, [r0, #0x4]
  149 + ldr r1, =0x00010000
  150 + str r1, [r0, #0x8]
  151 + ldr r1, =0x0007080c
  152 + str r1, [r0, #0x10]
  153 + imx7d_ddrphy_lpddr3_latency_setting
  154 + ldr r1, =0x1010007e
  155 + str r1, [r0, #0xb0]
  156 + ldr r1, =0x01010000
  157 + str r1, [r0, #0x1c]
  158 +
  159 + ldr r2, =ANATOP_BASE_ADDR
  160 + ldr r3, [r2, #0x800]
  161 + and r3, r3, #0xFF
  162 + cmp r3, #0x11
  163 + bne 1f
  164 +
  165 + ldr r1, =0x0db60d6e
  166 + str r1, [r0, #0x9c]
  167 + b 2f
  168 +1:
  169 + ldr r1, =0x00000b24
  170 + str r1, [r0, #0x9c]
  171 +2:
  172 + ldr r1, =0x06060606
  173 + str r1, [r0, #0x30]
  174 + ldr r1, =0x0a0a0a0a
  175 + str r1, [r0, #0x20]
  176 + ldr r1, =0x01000008
  177 + str r1, [r0, #0x50]
  178 + ldr r1, =0x00000008
  179 + str r1, [r0, #0x50]
  180 +
  181 + ldr r1, =0x0000000f
  182 + str r1, [r0, #0x18]
  183 + ldr r1, =0x0e487304
  184 + str r1, [r0, #0xc0]
  185 + ldr r1, =0x0e4c7304
  186 + str r1, [r0, #0xc0]
  187 + ldr r1, =0x0e4c7306
  188 + str r1, [r0, #0xc0]
  189 +
  190 +wait_zq:
  191 + ldr r1, [r0, #0xc4]
  192 + tst r1, #0x1
  193 + beq wait_zq
  194 +
  195 + ldr r1, =0x0e487304
  196 + str r1, [r0, #0xc0]
  197 +
  198 + ldr r0, =CCM_BASE_ADDR
  199 + mov r1, #0x0
  200 + ldr r2, =0x4130
  201 + str r1, [r0, r2]
  202 + ldr r0, =IOMUXC_GPR_BASE_ADDR
  203 + mov r1, #0x178
  204 + str r1, [r0, #0x20]
  205 + ldr r0, =CCM_BASE_ADDR
  206 + mov r1, #0x2
  207 + ldr r2, =0x4130
  208 + str r1, [r0, r2]
  209 +
  210 + ldr r0, =DDRC_IPS_BASE_ADDR
  211 +wait_stat:
  212 + ldr r1, [r0, #0x4]
  213 + tst r1, #0x1
  214 + beq wait_stat
  215 +.endm
  216 +
  217 +.macro imx7d_19x19_lpddr2_arm2_setting
  218 + /* Configure ocram_epdc */
  219 + ldr r0, =IOMUXC_GPR_BASE_ADDR
  220 + ldr r1, =0x4f400005
  221 + str r1, [r0, #0x4]
  222 +
  223 + ldr r0, =SRC_BASE_ADDR
  224 + ldr r1, =0x2
  225 + ldr r2, =0x1000
  226 + str r1, [r0, r2]
  227 +
  228 + ldr r0, =DDRC_IPS_BASE_ADDR
  229 + ldr r1, =0x03020004
  230 + str r1, [r0]
  231 + ldr r1, =0x80400003
  232 + str r1, [r0, #0x1a0]
  233 + ldr r1, =0x00100020
  234 + str r1, [r0, #0x1a4]
  235 + ldr r1, =0x80100004
  236 + str r1, [r0, #0x1a8]
  237 + ldr r1, =0x00200023
  238 + str r1, [r0, #0x64]
  239 + ldr r1, =0x1
  240 + str r1, [r0, #0x490]
  241 + ldr r1, =0x00350001
  242 + str r1, [r0, #0xd0]
  243 + ldr r1, =0x00001105
  244 + str r1, [r0, #0xd8]
  245 + ldr r1, =0x00c20006
  246 + str r1, [r0, #0xdc]
  247 + ldr r1, =0x00020000
  248 + str r1, [r0, #0xe0]
  249 + ldr r1, =0x00110006
  250 + str r1, [r0, #0xe4]
  251 + ldr r1, =0x33f
  252 + str r1, [r0, #0xf4]
  253 + ldr r1, =0x080e110b
  254 + str r1, [r0, #0x100]
  255 + ldr r1, =0x00020211
  256 + str r1, [r0, #0x104]
  257 + ldr r1, =0x02040706
  258 + str r1, [r0, #0x108]
  259 + ldr r1, =0x00504000
  260 + str r1, [r0, #0x10c]
  261 + ldr r1, =0x05010307
  262 + str r1, [r0, #0x110]
  263 + ldr r1, =0x02020404
  264 + str r1, [r0, #0x114]
  265 + ldr r1, =0x02020003
  266 + str r1, [r0, #0x118]
  267 + ldr r1, =0x00000202
  268 + str r1, [r0, #0x11c]
  269 + ldr r1, =0x00000202
  270 + str r1, [r0, #0x120]
  271 + ldr r1, =0x00600018
  272 + str r1, [r0, #0x180]
  273 + ldr r1, =0x00e00100
  274 + str r1, [r0, #0x184]
  275 + ldr r1, =0x02098203
  276 + str r1, [r0, #0x190]
  277 + ldr r1, =0x00060303
  278 + str r1, [r0, #0x194]
  279 +
  280 + ldr r1, =0x00000015
  281 + str r1, [r0, #0x200]
  282 + ldr r1, =0x00161616
  283 + str r1, [r0, #0x204]
  284 + ldr r1, =0x00000f0f
  285 + str r1, [r0, #0x210]
  286 + ldr r1, =0x04040404
  287 + str r1, [r0, #0x214]
  288 + ldr r1, =0x0f0f0404
  289 + str r1, [r0, #0x218]
  290 +
  291 + ldr r1, =0x06000600
  292 + str r1, [r0, #0x240]
  293 + mov r1, #0x0
  294 + str r1, [r0, #0x244]
  295 +
  296 + ldr r0, =SRC_BASE_ADDR
  297 + mov r1, #0x0
  298 + ldr r2, =0x1000
  299 + str r1, [r0, r2]
  300 +
  301 + ldr r0, =DDRPHY_IPS_BASE_ADDR
  302 + ldr r1, =0x17421640
  303 + str r1, [r0]
  304 + ldr r1, =0x10210100
  305 + str r1, [r0, #0x4]
  306 + ldr r1, =0x00010000
  307 + str r1, [r0, #0x8]
  308 + ldr r1, =0x00050408
  309 + str r1, [r0, #0x10]
  310 + ldr r1, =0x1010007e
  311 + str r1, [r0, #0xb0]
  312 + ldr r1, =0x01010000
  313 + str r1, [r0, #0x1c]
  314 + imx7d_ddrphy_lpddr2_latency_setting
  315 + ldr r1, =0x0000000f
  316 + str r1, [r0, #0x18]
  317 +
  318 + ldr r1, =0x06060606
  319 + str r1, [r0, #0x30]
  320 + ldr r1, =0x0a0a0a0a
  321 + str r1, [r0, #0x20]
  322 + ldr r1, =0x01000008
  323 + str r1, [r0, #0x50]
  324 + ldr r1, =0x00000008
  325 + str r1, [r0, #0x50]
  326 +
  327 + ldr r1, =0x0e487304
  328 + str r1, [r0, #0xc0]
  329 + ldr r1, =0x0e4c7304
  330 + str r1, [r0, #0xc0]
  331 + ldr r1, =0x0e4c7306
  332 + str r1, [r0, #0xc0]
  333 +
  334 +wait_zq:
  335 + ldr r1, [r0, #0xc4]
  336 + tst r1, #0x1
  337 + beq wait_zq
  338 +
  339 + ldr r1, =0x0e4c7304
  340 + str r1, [r0, #0xc0]
  341 + ldr r1, =0x0e487304
  342 + str r1, [r0, #0xc0]
  343 +
  344 + ldr r0, =CCM_BASE_ADDR
  345 + mov r1, #0x0
  346 + ldr r2, =0x4130
  347 + str r1, [r0, r2]
  348 + ldr r0, =IOMUXC_GPR_BASE_ADDR
  349 + mov r1, #0x1f8
  350 + str r1, [r0, #0x20]
  351 + ldr r0, =CCM_BASE_ADDR
  352 + mov r1, #0x2
  353 + ldr r2, =0x4130
  354 + str r1, [r0, r2]
  355 +
  356 + ldr r0, =DDRC_IPS_BASE_ADDR
  357 +wait_stat:
  358 + ldr r1, [r0, #0x4]
  359 + tst r1, #0x1
  360 + beq wait_stat
  361 +.endm
  362 +
  363 +.macro imx7_clock_gating
  364 +.endm
  365 +
  366 +.macro imx7_qos_setting
  367 +.endm
  368 +
  369 +.macro imx7_ddr_setting
  370 +#if defined (TARGET_MX7D_19X19_LPDDR2_ARM2)
  371 + imx7d_19x19_lpddr2_arm2_setting
  372 +#else
  373 + imx7d_19x19_lpddr3_arm2_setting
  374 +#endif
  375 +.endm
  376 +
  377 +/* include the common plugin code here */
  378 +#include <asm/arch/mx7_plugin.S>
include/configs/mx7d_19x19_ddr3_arm2.h
Diff comments   View file @ 1c0e03d
  1 +/*
  2 + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
  3 + *
  4 + * Configuration settings for the Freescale i.MX7D 19x19 DDR3 ARM2 board.
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __MX7D_19X19_DDR3_ARM2_CONFIG_H
  10 +#define __MX7D_19X19_DDR3_ARM2_CONFIG_H
  11 +
  12 +#define CONFIG_SYS_FSL_USDHC_NUM 3
  13 +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
  14 +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
  15 +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
  16 +
  17 +#define PHYS_SDRAM_SIZE SZ_1G
  18 +
  19 +#define CONFIG_FEC_MXC
  20 +#define CONFIG_MII
  21 +#define CONFIG_FEC_XCV_TYPE RGMII
  22 +#ifdef CONFIG_DM_ETH
  23 +#define CONFIG_ETHPRIME "eth0"
  24 +#else
  25 +#define CONFIG_ETHPRIME "FEC"
  26 +#endif
  27 +#define CONFIG_FEC_MXC_PHYADDR 0
  28 +
  29 +#define CONFIG_PHYLIB
  30 +#define CONFIG_PHY_ATHEROS
  31 +
  32 +/* ENET2 */
  33 +#define IMX_FEC_BASE ENET2_IPS_BASE_ADDR
  34 +
  35 +#define CONFIG_FEC_MXC_MDIO_BASE ENET_IPS_BASE_ADDR
  36 +
  37 +/* For QSPI, not use DM driver, because DTS does not have it supported */
  38 +#ifdef CONFIG_SPI_BOOT
  39 +#define CONFIG_MXC_SPI
  40 +#endif
  41 +
  42 +#define CONFIG_FSL_QSPI /* Enable the QSPI flash at default */
  43 +
  44 +#ifndef CONFIG_DM_I2C
  45 +#define CONFIG_SYS_I2C
  46 +#endif
  47 +#ifdef CONFIG_CMD_I2C
  48 +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
  49 +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
  50 +#endif
  51 +
  52 +/* PMIC */
  53 +#ifndef CONFIG_DM_PMIC
  54 +#define CONFIG_POWER
  55 +#define CONFIG_POWER_I2C
  56 +#define CONFIG_POWER_PFUZE3000
  57 +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
  58 +#endif
  59 +
  60 +#ifdef CONFIG_MXC_SPI
  61 +#define CONFIG_CMD_SF
  62 +#define CONFIG_SPI_FLASH
  63 +#define CONFIG_SPI_FLASH_ATMEL
  64 +#define CONFIG_SF_DEFAULT_BUS 0
  65 +#define CONFIG_SF_DEFAULT_SPEED 20000000
  66 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
  67 +#define CONFIG_SF_DEFAULT_CS 0
  68 +#endif
  69 +
  70 +#include "mx7d_arm2.h"
  71 +
  72 +#endif
include/configs/mx7d_19x19_lpddr3_arm2.h
Diff comments   View file @ 1c0e03d
  1 +/*
  2 + * Copyright (C) 2015 Freescale Semiconductor, Inc.
  3 + *
  4 + * Configuration settings for the Freescale i.MX7D 19x19 LPDDR3 ARM2 board.
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __MX7D_19X19_LPDDR3_ARM2_CONFIG_H
  10 +#define __MX7D_19X19_LPDDR3_ARM2_CONFIG_H
  11 +
  12 +#define CONFIG_SYS_FSL_USDHC_NUM 1
  13 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
  14 +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
  15 +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
  16 +
  17 +#ifdef CONFIG_TARGET_MX7D_19X19_LPDDR2_ARM2
  18 +#define PHYS_SDRAM_SIZE SZ_512M
  19 +#else
  20 +#define PHYS_SDRAM_SIZE SZ_2G
  21 +#endif
  22 +
  23 +#define CONFIG_FEC_MXC
  24 +#define CONFIG_MII
  25 +#define CONFIG_FEC_XCV_TYPE RGMII
  26 +#ifdef CONFIG_DM_ETH
  27 +#define CONFIG_ETHPRIME "eth0"
  28 +#else
  29 +#define CONFIG_ETHPRIME "FEC"
  30 +#endif
  31 +#define CONFIG_FEC_MXC_PHYADDR 0
  32 +
  33 +#define CONFIG_PHYLIB
  34 +#define CONFIG_PHY_ATHEROS
  35 +
  36 +/* ENET2 */
  37 +#define IMX_FEC_BASE ENET2_IPS_BASE_ADDR
  38 +
  39 +#define CONFIG_FEC_MXC_MDIO_BASE ENET_IPS_BASE_ADDR
  40 +
  41 +/* QSPI conflict with EIMNOR */
  42 +/* FEC0 conflict with EIMNOR */
  43 +/* ECSPI conflict with UART */
  44 +#ifdef CONFIG_QSPI_BOOT
  45 +#define CONFIG_FSL_QSPI
  46 +#elif defined CONFIG_SPI_BOOT
  47 +#define CONFIG_MXC_SPI
  48 +#elif defined CONFIG_NOR_BOOT
  49 +#define CONFIG_MTD_NOR_FLASH
  50 +#undef CONFIG_FEC_MXC
  51 +#elif defined CONFIG_NAND_BOOT
  52 +#define CONFIG_NAND_MXS
  53 +#else
  54 +#define CONFIG_MTD_NOR_FLASH
  55 +#undef CONFIG_FEC_MXC
  56 +#endif
  57 +
  58 +#ifndef CONFIG_DM_I2C
  59 +#define CONFIG_SYS_I2C
  60 +#endif
  61 +#ifdef CONFIG_CMD_I2C
  62 +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
  63 +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
  64 +#endif
  65 +
  66 +/* PMIC */
  67 +#ifndef CONFIG_DM_PMIC
  68 +#define CONFIG_POWER
  69 +#define CONFIG_POWER_I2C
  70 +#define CONFIG_POWER_PFUZE3000
  71 +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
  72 +#endif
  73 +
  74 +#ifdef CONFIG_MXC_SPI
  75 +#define CONFIG_CMD_SF
  76 +#define CONFIG_SPI_FLASH
  77 +#define CONFIG_SPI_FLASH_ATMEL
  78 +#define CONFIG_SF_DEFAULT_BUS 0
  79 +#define CONFIG_SF_DEFAULT_SPEED 20000000
  80 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
  81 +#define CONFIG_SF_DEFAULT_CS 0
  82 +#endif
  83 +
  84 +#include "mx7d_arm2.h"
  85 +
  86 +#endif