arch: powerpc: update the IFC IP input clock

IFC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register (CCR) used in current implementation governs IFC IP output clock. Update sys_info->freq_localbus to represent IFC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>

arch: powerpc: update the IFC IP input clock
IFC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register (CCR) used in current implementation governs IFC IP output clock. Update sys_info->freq_localbus to represent IFC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Prabhakar Kushwaha · York Sun
1 parent d98b98d62e
Showing 3 changed files with 21 additions and 8 deletions Side-by-side Diff
README
arch/powerpc/cpu/mpc85xx/Kconfig
arch/powerpc/cpu/mpc85xx/speed.c
@@ -504,6 +504,9 @@
 		CONFIG_SYS_FSL_IFC_LE
 		Defines the IFC controller register space as Little Endian
  
+		CONFIG_SYS_FSL_IFC_CLK_DIV
+		Defines divider of platform clock(clock input to IFC controller).
+
 		CONFIG_SYS_FSL_PBL_PBI
 		It enables addition of RCW (Power on reset configuration) in built image.
 		Please refer doc/README.pblimage for more details
@@ -1301,6 +1301,22 @@
                 symbol should be set to the TLB1 entry to be used for this
                 purpose. If unsure, do not change.
  
+config SYS_FSL_IFC_CLK_DIV
+	int "Divider of platform clock"
+	depends on FSL_IFC
+	default 2 if	ARCH_B4420	|| \
+			ARCH_B4860	|| \
+			ARCH_T1024	|| \
+			ARCH_T1023	|| \
+			ARCH_T1040	|| \
+			ARCH_T1042	|| \
+			ARCH_T4160	|| \
+			ARCH_T4240
+	default 1
+	help
+		Defines divider of platform clock(clock input to
+		IFC controller).
+
 source "board/freescale/b4860qds/Kconfig"
 source "board/freescale/bsc9131rdb/Kconfig"
 source "board/freescale/bsc9132qds/Kconfig"
@@ -27,10 +27,6 @@
 void get_sys_info(sys_info_t *sys_info)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#ifdef CONFIG_FSL_IFC
-	struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
-	u32 ccr;
-#endif
 #ifdef CONFIG_FSL_CORENET
 	volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
 	unsigned int cpu;
@@ -640,10 +636,8 @@
 #endif
  
 #if defined(CONFIG_FSL_IFC)
-	ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
-	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
-
-	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
+	sys_info->freq_localbus = sys_info->freq_systembus /
+						CONFIG_SYS_FSL_IFC_CLK_DIV;
 #endif
 }
...	...	@@ -504,6 +504,9 @@
504	504	CONFIG_SYS_FSL_IFC_LE
505	505	Defines the IFC controller register space as Little Endian
506	506
	507	+ CONFIG_SYS_FSL_IFC_CLK_DIV
	508	+ Defines divider of platform clock(clock input to IFC controller).
	509	+
507	510	CONFIG_SYS_FSL_PBL_PBI
508	511	It enables addition of RCW (Power on reset configuration) in built image.
509	512	Please refer doc/README.pblimage for more details
...	...	@@ -1301,6 +1301,22 @@
1301	1301	symbol should be set to the TLB1 entry to be used for this
1302	1302	purpose. If unsure, do not change.
1303	1303
	1304	+config SYS_FSL_IFC_CLK_DIV
	1305	+ int "Divider of platform clock"
	1306	+ depends on FSL_IFC
	1307	+ default 2 if ARCH_B4420 \|\| \
	1308	+ ARCH_B4860 \|\| \
	1309	+ ARCH_T1024 \|\| \
	1310	+ ARCH_T1023 \|\| \
	1311	+ ARCH_T1040 \|\| \
	1312	+ ARCH_T1042 \|\| \
	1313	+ ARCH_T4160 \|\| \
	1314	+ ARCH_T4240
	1315	+ default 1
	1316	+ help
	1317	+ Defines divider of platform clock(clock input to
	1318	+ IFC controller).
	1319	+
1304	1320	source "board/freescale/b4860qds/Kconfig"
1305	1321	source "board/freescale/bsc9131rdb/Kconfig"
1306	1322	source "board/freescale/bsc9132qds/Kconfig"
...	...	@@ -27,10 +27,6 @@
27	27	void get_sys_info(sys_info_t *sys_info)
28	28	{
29	29	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
30		-#ifdef CONFIG_FSL_IFC
31		- struct fsl_ifc ifc_regs = {(void )CONFIG_SYS_IFC_ADDR, (void )NULL};
32		- u32 ccr;
33		-#endif
34	30	#ifdef CONFIG_FSL_CORENET
35	31	volatile ccsr_clk_t clk = (void )(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
36	32	unsigned int cpu;
...	...	@@ -640,10 +636,8 @@
640	636	#endif
641	637
642	638	#if defined(CONFIG_FSL_IFC)
643		- ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
644		- ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
645		-
646		- sys_info->freq_localbus = sys_info->freq_systembus / ccr;
	639	+ sys_info->freq_localbus = sys_info->freq_systembus /
	640	+ CONFIG_SYS_FSL_IFC_CLK_DIV;
647	641	#endif
648	642	}
649	643