mmc: at91: add multi block read/write support.

Since the at91sam9263, the mmc hardware support multi blocks read/write. So this driver enable it. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

mmc: at91: add multi block read/write support.
Since the at91sam9263, the mmc hardware support multi blocks read/write. So this driver enable it. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wu, Josh · Andreas Bießmann
1 parent b9f4bc34ac
Showing 2 changed files with 17 additions and 1 deletions Side-by-side Diff
drivers/mmc/gen_atmel_mci.c
include/atmel_mci.h
@@ -87,6 +87,11 @@
 		 | MMCI_BF(BLKLEN, blklen)
 		 | MMCI_BIT(RDPROOF)
 		 | MMCI_BIT(WRPROOF)), &mci->mr);
+	/*
+	 * On some new platforms BLKLEN in mci->mr is ignored.
+	 * Should use the BLKLEN in the block register.
+	 */
+	writel(MMCI_BF(BLKLEN, blklen), &mci->blkr);
 	initialized = 1;
 }
  
@@ -182,6 +187,12 @@
  
 	/* Figure out the transfer arguments */
 	cmdr = mci_encode_cmd(cmd, data, &error_flags);
+
+	/* For multi blocks read/write, set the block register */
+	if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK)
+			|| (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK))
+		writel(data->blocks | MMCI_BF(BLKLEN, mmc->read_bl_len),
+			&mci->blkr);
  
 	/* Send the command */
 	writel(cmd->cmdarg, &mci->argr);
@@ -38,7 +38,7 @@
 	u32	sdcr;	/* 0x0c */
 	u32	argr;	/* 0x10 */
 	u32	cmdr;	/* 0x14 */
-	u32	_18;	/* 0x18 */
+	u32	blkr;	/* 0x18 */
 	u32	_1c;	/* 0x1c */
 	u32	rspr;	/* 0x20 */
 	u32	rspr1;	/* 0x24 */
@@ -117,6 +117,11 @@
 #define MMCI_TRDIR_SIZE				1
 #define MMCI_TRTYP_OFFSET			19
 #define MMCI_TRTYP_SIZE				2
+
+/* Bitfields in BLKR */
+/* MMCI_BLKLEN_OFFSET/SIZE already defined in MR */
+#define MMCI_BCNT_OFFSET			0
+#define MMCI_BCNT_SIZE			16
  
 /* Bitfields in RSPRx */
 #define MMCI_RSP_OFFSET				0
...	...	@@ -87,6 +87,11 @@
87	87	\| MMCI_BF(BLKLEN, blklen)
88	88	\| MMCI_BIT(RDPROOF)
89	89	\| MMCI_BIT(WRPROOF)), &mci->mr);
	90	+ /*
	91	+ * On some new platforms BLKLEN in mci->mr is ignored.
	92	+ * Should use the BLKLEN in the block register.
	93	+ */
	94	+ writel(MMCI_BF(BLKLEN, blklen), &mci->blkr);
90	95	initialized = 1;
91	96	}
92	97
...	...	@@ -182,6 +187,12 @@
182	187
183	188	/* Figure out the transfer arguments */
184	189	cmdr = mci_encode_cmd(cmd, data, &error_flags);
	190	+
	191	+ /* For multi blocks read/write, set the block register */
	192	+ if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK)
	193	+ \|\| (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK))
	194	+ writel(data->blocks \| MMCI_BF(BLKLEN, mmc->read_bl_len),
	195	+ &mci->blkr);
185	196
186	197	/* Send the command */
187	198	writel(cmd->cmdarg, &mci->argr);
...	...	@@ -38,7 +38,7 @@
38	38	u32 sdcr; /* 0x0c */
39	39	u32 argr; /* 0x10 */
40	40	u32 cmdr; /* 0x14 */
41		- u32 _18; /* 0x18 */
	41	+ u32 blkr; /* 0x18 */
42	42	u32 _1c; /* 0x1c */
43	43	u32 rspr; /* 0x20 */
44	44	u32 rspr1; /* 0x24 */
...	...	@@ -117,6 +117,11 @@
117	117	#define MMCI_TRDIR_SIZE 1
118	118	#define MMCI_TRTYP_OFFSET 19
119	119	#define MMCI_TRTYP_SIZE 2
	120	+
	121	+/* Bitfields in BLKR */
	122	+/* MMCI_BLKLEN_OFFSET/SIZE already defined in MR */
	123	+#define MMCI_BCNT_OFFSET 0
	124	+#define MMCI_BCNT_SIZE 16
120	125
121	126	/* Bitfields in RSPRx */
122	127	#define MMCI_RSP_OFFSET 0