Commit 1e468dfbe7c5ae117482d1dccaff94b8652f32aa
1 parent
1c6f3b6ec7
Exists in
smarc-imx-l5.0.0_1.0.0-ga
ENGR00331706-4 imx: mx6sl: Set the preclk clock source to OSC 24Mhz
For MX6SL, uses the OSC 24Mhz as the preclk source in CCM. Align the preclk setting with kernel. Signed-off-by: Ye.Li <B37916@freescale.com>
Showing 1 changed file with 16 additions and 0 deletions Side-by-side Diff
arch/arm/cpu/armv7/mx6/soc.c
| ... | ... | @@ -393,7 +393,18 @@ |
| 393 | 393 | writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &mxc_ccm->ana_misc0_set); |
| 394 | 394 | } |
| 395 | 395 | |
| 396 | +#ifdef CONFIG_MX6SL | |
| 397 | +static void set_preclk_from_osc(void) | |
| 398 | +{ | |
| 399 | + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
| 400 | + u32 reg; | |
| 396 | 401 | |
| 402 | + reg = readl(&mxc_ccm->cscmr1); | |
| 403 | + reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK; | |
| 404 | + writel(reg, &mxc_ccm->cscmr1); | |
| 405 | +} | |
| 406 | +#endif | |
| 407 | + | |
| 397 | 408 | #ifdef CONFIG_MX6SX |
| 398 | 409 | void vadc_power_up(void) |
| 399 | 410 | { |
| ... | ... | @@ -536,6 +547,11 @@ |
| 536 | 547 | */ |
| 537 | 548 | if (mxc_get_clock(MXC_ARM_CLK) == 396000000) |
| 538 | 549 | set_ahb_rate(132000000); |
| 550 | + | |
| 551 | + /* Set perclk to source from OSC 24MHz */ | |
| 552 | +#if defined(CONFIG_MX6SL) | |
| 553 | + set_preclk_from_osc(); | |
| 554 | +#endif | |
| 539 | 555 | |
| 540 | 556 | imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ |
| 541 | 557 |