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Commit 1e4ad74b875f4da91193afffb0bb0db90ec7b886

Authored by Felipe Balbi
Committed by Tom Rini
1 parent d11ac4b56d
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

beagle_x15: add board support for Beagle x15 

BeagleBoard-X15 is the next generation Open Source
Hardware BeagleBoard based on TI's AM5728 SoC
featuring dual core 1.5GHZ A15 processor. The
platform features 2GB DDR3L (w/dual 32bit busses),
eSATA, 3 USB3.0 ports, integrated HDMI (1920x108@60),
separate LCD port, video In port, 4GB eMMC, uSD,
Analog audio in/out, dual 1G Ethernet.

For more information, refer to:
http://www.elinux.org/Beagleboard:BeagleBoard-X15

Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>

Showing 8 changed files with 569 additions and 0 deletions Side-by-side Diff

arch/arm/cpu/armv7/omap5/Kconfig
Diff comments   View file @ 1e4ad74
... ... @@ -12,6 +12,9 @@
12 12 config TARGET_DRA7XX_EVM
13 13 bool "TI DRA7XX"
14 14  
  15 +config TARGET_BEAGLE_X15
  16 + bool "BeagleBoard X15"
  17 +
15 18 endchoice
16 19  
17 20 config SYS_SOC
... ... @@ -20,6 +23,7 @@
20 23 source "board/compulab/cm_t54/Kconfig"
21 24 source "board/ti/omap5_uevm/Kconfig"
22 25 source "board/ti/dra7xx/Kconfig"
  26 +source "board/ti/beagle_x15/Kconfig"
23 27  
24 28 endif
board/ti/beagle_x15/Kconfig
Diff comments   View file @ 1e4ad74
  1 +if TARGET_BEAGLE_X15
  2 +
  3 +config SYS_BOARD
  4 + default "beagle_x15"
  5 +
  6 +config SYS_VENDOR
  7 + default "ti"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "beagle_x15"
  11 +
  12 +endif
board/ti/beagle_x15/Makefile
Diff comments   View file @ 1e4ad74
  1 +#
  2 +# (C) Copyright 2014
  3 +# Texas Instruments, <www.ti.com>
  4 +#
  5 +# SPDX-License-Identifier: GPL-2.0+
  6 +#
  7 +
  8 +obj-y := board.o
board/ti/beagle_x15/board.c
Diff comments   View file @ 1e4ad74
  1 +/*
  2 + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
  3 + *
  4 + * Author: Felipe Balbi <balbi@ti.com>
  5 + *
  6 + * Based on board/ti/dra7xx/evm.c
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#include <common.h>
  12 +#include <palmas.h>
  13 +#include <sata.h>
  14 +#include <usb.h>
  15 +#include <asm/omap_common.h>
  16 +#include <asm/emif.h>
  17 +#include <asm/arch/clock.h>
  18 +#include <asm/arch/sys_proto.h>
  19 +#include <asm/arch/mmc_host_def.h>
  20 +#include <asm/arch/sata.h>
  21 +#include <asm/arch/gpio.h>
  22 +#include <environment.h>
  23 +
  24 +#include "mux_data.h"
  25 +
  26 +#ifdef CONFIG_DRIVER_TI_CPSW
  27 +#include <cpsw.h>
  28 +#endif
  29 +
  30 +DECLARE_GLOBAL_DATA_PTR;
  31 +
  32 +const struct omap_sysinfo sysinfo = {
  33 + "Board: BeagleBoard x15\n"
  34 +};
  35 +
  36 +static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  37 + .dmm_lisa_map_3 = 0x80740300,
  38 + .is_ma_present = 0x1
  39 +};
  40 +
  41 +void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  42 +{
  43 + *dmm_lisa_regs = &beagle_x15_lisa_regs;
  44 +}
  45 +
  46 +static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
  47 + .sdram_config_init = 0x61851b32,
  48 + .sdram_config = 0x61851b32,
  49 + .sdram_config2 = 0x00000000,
  50 + .ref_ctrl = 0x00001035,
  51 + .sdram_tim1 = 0xceef266b,
  52 + .sdram_tim2 = 0x328f7fda,
  53 + .sdram_tim3 = 0x027f88a8,
  54 + .read_idle_ctrl = 0x00050001,
  55 + .zq_config = 0x0007190b,
  56 + .temp_alert_config = 0x00000000,
  57 + .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
  58 + .emif_ddr_phy_ctlr_1 = 0x0e24400a,
  59 + .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  60 + .emif_ddr_ext_phy_ctrl_2 = 0x00740074,
  61 + .emif_ddr_ext_phy_ctrl_3 = 0x00780078,
  62 + .emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
  63 + .emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
  64 + .emif_rd_wr_lvl_rmp_win = 0x00000000,
  65 + .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
  66 + .emif_rd_wr_lvl_ctl = 0x00000000,
  67 + .emif_rd_wr_exec_thresh = 0x00000305
  68 +};
  69 +
  70 +static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
  71 + 0x00800080,
  72 + 0x00360036,
  73 + 0x00340034,
  74 + 0x00360036,
  75 + 0x00350035,
  76 + 0x00350035,
  77 +
  78 + 0x01ff01ff,
  79 + 0x01ff01ff,
  80 + 0x01ff01ff,
  81 + 0x01ff01ff,
  82 + 0x01ff01ff,
  83 +
  84 + 0x00430043,
  85 + 0x003e003e,
  86 + 0x004a004a,
  87 + 0x00470047,
  88 + 0x00400040,
  89 +
  90 + 0x00000000,
  91 + 0x00600020,
  92 + 0x40010080,
  93 + 0x08102040,
  94 +
  95 + 0x00400040,
  96 + 0x00400040,
  97 + 0x00400040,
  98 + 0x00400040,
  99 + 0x00400040
  100 +};
  101 +
  102 +static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
  103 + .sdram_config_init = 0x61851b32,
  104 + .sdram_config = 0x61851b32,
  105 + .sdram_config2 = 0x00000000,
  106 + .ref_ctrl = 0x00001035,
  107 + .sdram_tim1 = 0xceef266b,
  108 + .sdram_tim2 = 0x328f7fda,
  109 + .sdram_tim3 = 0x027f88a8,
  110 + .read_idle_ctrl = 0x00050001,
  111 + .zq_config = 0x0007190b,
  112 + .temp_alert_config = 0x00000000,
  113 + .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
  114 + .emif_ddr_phy_ctlr_1 = 0x0e24400a,
  115 + .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  116 + .emif_ddr_ext_phy_ctrl_2 = 0x00820082,
  117 + .emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
  118 + .emif_ddr_ext_phy_ctrl_4 = 0x00800080,
  119 + .emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
  120 + .emif_rd_wr_lvl_rmp_win = 0x00000000,
  121 + .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
  122 + .emif_rd_wr_lvl_ctl = 0x00000000,
  123 + .emif_rd_wr_exec_thresh = 0x00000305
  124 +};
  125 +
  126 +static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
  127 + 0x00800080,
  128 + 0x00370037,
  129 + 0x00390039,
  130 + 0x00360036,
  131 + 0x00370037,
  132 + 0x00350035,
  133 + 0x01ff01ff,
  134 + 0x01ff01ff,
  135 + 0x01ff01ff,
  136 + 0x01ff01ff,
  137 + 0x01ff01ff,
  138 + 0x00540054,
  139 + 0x00540054,
  140 + 0x004e004e,
  141 + 0x004c004c,
  142 + 0x00400040,
  143 +
  144 + 0x00000000,
  145 + 0x00600020,
  146 + 0x40010080,
  147 + 0x08102040,
  148 +
  149 + 0x00400040,
  150 + 0x00400040,
  151 + 0x00400040,
  152 + 0x00400040,
  153 + 0x00400040
  154 +};
  155 +
  156 +void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
  157 +{
  158 + switch (emif_nr) {
  159 + case 1:
  160 + *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
  161 + break;
  162 + case 2:
  163 + *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
  164 + break;
  165 + }
  166 +}
  167 +
  168 +void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
  169 +{
  170 + switch (emif_nr) {
  171 + case 1:
  172 + *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
  173 + *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
  174 + break;
  175 + case 2:
  176 + *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
  177 + *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
  178 + break;
  179 + }
  180 +}
  181 +
  182 +struct vcores_data beagle_x15_volts = {
  183 + .mpu.value = VDD_MPU_DRA752,
  184 + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
  185 + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  186 + .mpu.addr = TPS659038_REG_ADDR_SMPS12,
  187 + .mpu.pmic = &tps659038,
  188 +
  189 + .eve.value = VDD_EVE_DRA752,
  190 + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  191 + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  192 + .eve.addr = TPS659038_REG_ADDR_SMPS45,
  193 + .eve.pmic = &tps659038,
  194 +
  195 + .gpu.value = VDD_GPU_DRA752,
  196 + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
  197 + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  198 + .gpu.addr = TPS659038_REG_ADDR_SMPS45,
  199 + .gpu.pmic = &tps659038,
  200 +
  201 + .core.value = VDD_CORE_DRA752,
  202 + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
  203 + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  204 + .core.addr = TPS659038_REG_ADDR_SMPS6,
  205 + .core.pmic = &tps659038,
  206 +
  207 + .iva.value = VDD_IVA_DRA752,
  208 + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
  209 + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  210 + .iva.addr = TPS659038_REG_ADDR_SMPS45,
  211 + .iva.pmic = &tps659038,
  212 +};
  213 +
  214 +void hw_data_init(void)
  215 +{
  216 + *prcm = &dra7xx_prcm;
  217 + *dplls_data = &dra7xx_dplls;
  218 + *omap_vcores = &beagle_x15_volts;
  219 + *ctrl = &dra7xx_ctrl;
  220 +}
  221 +
  222 +int board_init(void)
  223 +{
  224 + gpmc_init();
  225 + gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
  226 +
  227 + return 0;
  228 +}
  229 +
  230 +int board_late_init(void)
  231 +{
  232 + init_sata(0);
  233 + /*
  234 + * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
  235 + * This is the POWERHOLD-in-Low behavior.
  236 + */
  237 + palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
  238 + return 0;
  239 +}
  240 +
  241 +static void do_set_mux32(u32 base,
  242 + struct pad_conf_entry const *array, int size)
  243 +{
  244 + int i;
  245 + struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
  246 +
  247 + for (i = 0; i < size; i++, pad++)
  248 + writel(pad->val, base + pad->offset);
  249 +}
  250 +
  251 +void set_muxconf_regs_essential(void)
  252 +{
  253 + do_set_mux32((*ctrl)->control_padconf_core_base,
  254 + core_padconf_array_essential,
  255 + sizeof(core_padconf_array_essential) /
  256 + sizeof(struct pad_conf_entry));
  257 +}
  258 +
  259 +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
  260 +int board_mmc_init(bd_t *bis)
  261 +{
  262 + omap_mmc_init(0, 0, 0, -1, -1);
  263 + omap_mmc_init(1, 0, 0, -1, -1);
  264 + return 0;
  265 +}
  266 +#endif
  267 +
  268 +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
  269 +int spl_start_uboot(void)
  270 +{
  271 + /* break into full u-boot on 'c' */
  272 + if (serial_tstc() && serial_getc() == 'c')
  273 + return 1;
  274 +
  275 +#ifdef CONFIG_SPL_ENV_SUPPORT
  276 + env_init();
  277 + env_relocate_spec();
  278 + if (getenv_yesno("boot_os") != 1)
  279 + return 1;
  280 +#endif
  281 +
  282 + return 0;
  283 +}
  284 +#endif
  285 +
  286 +#ifdef CONFIG_DRIVER_TI_CPSW
  287 +
  288 +/* Delay value to add to calibrated value */
  289 +#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
  290 +#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
  291 +#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
  292 +#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
  293 +#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
  294 +#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
  295 +#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
  296 +#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
  297 +#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
  298 +#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
  299 +
  300 +static void cpsw_control(int enabled)
  301 +{
  302 + /* VTP can be added here */
  303 +}
  304 +
  305 +static struct cpsw_slave_data cpsw_slaves[] = {
  306 + {
  307 + .slave_reg_ofs = 0x208,
  308 + .sliver_reg_ofs = 0xd80,
  309 + .phy_addr = 1,
  310 + },
  311 + {
  312 + .slave_reg_ofs = 0x308,
  313 + .sliver_reg_ofs = 0xdc0,
  314 + .phy_addr = 2,
  315 + },
  316 +};
  317 +
  318 +static struct cpsw_platform_data cpsw_data = {
  319 + .mdio_base = CPSW_MDIO_BASE,
  320 + .cpsw_base = CPSW_BASE,
  321 + .mdio_div = 0xff,
  322 + .channels = 8,
  323 + .cpdma_reg_ofs = 0x800,
  324 + .slaves = 1,
  325 + .slave_data = cpsw_slaves,
  326 + .ale_reg_ofs = 0xd00,
  327 + .ale_entries = 1024,
  328 + .host_port_reg_ofs = 0x108,
  329 + .hw_stats_reg_ofs = 0x900,
  330 + .bd_ram_ofs = 0x2000,
  331 + .mac_control = (1 << 5),
  332 + .control = cpsw_control,
  333 + .host_port_num = 0,
  334 + .version = CPSW_CTRL_VERSION_2,
  335 +};
  336 +
  337 +int board_eth_init(bd_t *bis)
  338 +{
  339 + int ret;
  340 + uint8_t mac_addr[6];
  341 + uint32_t mac_hi, mac_lo;
  342 + uint32_t ctrl_val;
  343 +
  344 + /* try reading mac address from efuse */
  345 + mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
  346 + mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
  347 + mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
  348 + mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  349 + mac_addr[2] = mac_hi & 0xFF;
  350 + mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
  351 + mac_addr[4] = (mac_lo & 0xFF00) >> 8;
  352 + mac_addr[5] = mac_lo & 0xFF;
  353 +
  354 + if (!getenv("ethaddr")) {
  355 + printf("<ethaddr> not set. Validating first E-fuse MAC\n");
  356 +
  357 + if (is_valid_ether_addr(mac_addr))
  358 + eth_setenv_enetaddr("ethaddr", mac_addr);
  359 + }
  360 +
  361 + mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
  362 + mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
  363 + mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
  364 + mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  365 + mac_addr[2] = mac_hi & 0xFF;
  366 + mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
  367 + mac_addr[4] = (mac_lo & 0xFF00) >> 8;
  368 + mac_addr[5] = mac_lo & 0xFF;
  369 +
  370 + if (!getenv("eth1addr")) {
  371 + if (is_valid_ether_addr(mac_addr))
  372 + eth_setenv_enetaddr("eth1addr", mac_addr);
  373 + }
  374 +
  375 + ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
  376 + ctrl_val |= 0x22;
  377 + writel(ctrl_val, (*ctrl)->control_core_control_io1);
  378 +
  379 + ret = cpsw_register(&cpsw_data);
  380 + if (ret < 0)
  381 + printf("Error %d registering CPSW switch\n", ret);
  382 +
  383 + return ret;
  384 +}
  385 +#endif
  386 +
  387 +#ifdef CONFIG_USB_XHCI_OMAP
  388 +int board_usb_init(int index, enum usb_init_type init)
  389 +{
  390 + setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
  391 + OTG_SS_CLKCTRL_MODULEMODE_HW | OPTFCLKEN_REFCLK960M);
  392 +
  393 + return 0;
  394 +}
  395 +#endif
board/ti/beagle_x15/mux_data.h
Diff comments   View file @ 1e4ad74
  1 +/*
  2 + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
  3 + *
  4 + * Author: Felipe Balbi <balbi@ti.com>
  5 + *
  6 + * Based on board/ti/dra7xx/evm.c
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +#ifndef _MUX_DATA_BEAGLE_X15_H_
  11 +#define _MUX_DATA_BEAGLE_X15_H_
  12 +
  13 +#include <asm/arch/mux_dra7xx.h>
  14 +
  15 +const struct pad_conf_entry core_padconf_array_essential[] = {
  16 + {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */
  17 + {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */
  18 + {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */
  19 + {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */
  20 + {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */
  21 + {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */
  22 + {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */
  23 + {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */
  24 + {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */
  25 + {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */
  26 + {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */
  27 + {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */
  28 + {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */
  29 + {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */
  30 + {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */
  31 + {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */
  32 + {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */
  33 + {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */
  34 + {UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */
  35 + {UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */
  36 + {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */
  37 + {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */
  38 + {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */
  39 + {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */
  40 + {RGMII0_TXC, (M0) },
  41 + {RGMII0_TXCTL, (M0) },
  42 + {RGMII0_TXD3, (M0) },
  43 + {RGMII0_TXD2, (M0) },
  44 + {RGMII0_TXD1, (M0) },
  45 + {RGMII0_TXD0, (M0) },
  46 + {RGMII0_RXC, (IEN | M0) },
  47 + {RGMII0_RXCTL, (IEN | M0) },
  48 + {RGMII0_RXD3, (IEN | M0) },
  49 + {RGMII0_RXD2, (IEN | M0) },
  50 + {RGMII0_RXD1, (IEN | M0) },
  51 + {RGMII0_RXD0, (IEN | M0) },
  52 + {USB1_DRVVBUS, (M0 | FSC) },
  53 + {SPI1_CS1, (PEN | IDIS | M14) }, /* GPIO7_11 */
  54 +};
  55 +#endif /* _MUX_DATA_BEAGLE_X15_H_ */
configs/beagle_x15_defconfig
Diff comments   View file @ 1e4ad74
  1 +CONFIG_SPL=y
  2 +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3"
  3 ++S:CONFIG_ARM=y
  4 ++S:CONFIG_OMAP54XX=y
  5 ++S:CONFIG_TARGET_BEAGLE_X15=y
include/configs/beagle_x15.h
Diff comments   View file @ 1e4ad74
  1 +/*
  2 + * (C) Copyright 2014
  3 + * Texas Instruments Incorporated.
  4 + * Felipe Balbi <balbi@ti.com>
  5 + *
  6 + * Configuration settings for the TI Beagle x15 board.
  7 + * See ti_omap5_common.h for omap5 common settings.
  8 + *
  9 + * SPDX-License-Identifier: GPL-2.0+
  10 + */
  11 +
  12 +#ifndef __CONFIG_BEAGLE_X15_H
  13 +#define __CONFIG_BEAGLE_X15_H
  14 +
  15 +#define CONFIG_AM57XX
  16 +
  17 +#define CONFIG_NR_DRAM_BANKS 2
  18 +
  19 +#define CONFIG_ENV_SIZE (64 << 10)
  20 +#define CONFIG_ENV_IS_IN_FAT
  21 +#define FAT_ENV_INTERFACE "mmc"
  22 +#define FAT_ENV_DEVICE_AND_PART "0:1"
  23 +#define FAT_ENV_FILE "uboot.env"
  24 +
  25 +#define CONFIG_CMD_SAVEENV
  26 +
  27 +#define CONSOLEDEV "ttyO2"
  28 +#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
  29 +#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
  30 +#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
  31 +#define CONFIG_BAUDRATE 115200
  32 +
  33 +#define CONFIG_SYS_OMAP_ABE_SYSCK
  34 +
  35 +/* Define the default GPT table for eMMC */
  36 +#define PARTS_DEFAULT \
  37 + "uuid_disk=${uuid_gpt_disk};" \
  38 + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
  39 +
  40 +#include <configs/ti_omap5_common.h>
  41 +
  42 +/* Enhance our eMMC support / experience. */
  43 +#define CONFIG_CMD_GPT
  44 +#define CONFIG_EFI_PARTITION
  45 +#define CONFIG_PARTITION_UUIDS
  46 +#define CONFIG_CMD_PART
  47 +
  48 +/* CPSW Ethernet */
  49 +#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */
  50 +#define CONFIG_CMD_DHCP
  51 +#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */
  52 +#define CONFIG_BOOTP_DNS2
  53 +#define CONFIG_BOOTP_SEND_HOSTNAME
  54 +#define CONFIG_BOOTP_GATEWAY
  55 +#define CONFIG_BOOTP_SUBNETMASK
  56 +#define CONFIG_NET_RETRY_COUNT 10
  57 +#define CONFIG_CMD_PING
  58 +#define CONFIG_CMD_MII
  59 +#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
  60 +#define CONFIG_MII /* Required in net/eth.c */
  61 +#define CONFIG_PHY_GIGE /* per-board part of CPSW */
  62 +#define CONFIG_PHYLIB
  63 +
  64 +#define CONFIG_SUPPORT_EMMC_BOOT
  65 +
  66 +/* USB xHCI HOST */
  67 +#define CONFIG_CMD_USB
  68 +#define CONFIG_USB_HOST
  69 +#define CONFIG_USB_XHCI
  70 +#define CONFIG_USB_XHCI_OMAP
  71 +#define CONFIG_USB_STORAGE
  72 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
  73 +
  74 +#define CONFIG_OMAP_USB_PHY
  75 +#define CONFIG_OMAP_USB3PHY1_HOST
  76 +
  77 +/* SATA */
  78 +#define CONFIG_BOARD_LATE_INIT
  79 +#define CONFIG_CMD_SCSI
  80 +#define CONFIG_LIBATA
  81 +#define CONFIG_SCSI_AHCI
  82 +#define CONFIG_SCSI_AHCI_PLAT
  83 +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
  84 +#define CONFIG_SYS_SCSI_MAX_LUN 1
  85 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  86 + CONFIG_SYS_SCSI_MAX_LUN)
  87 +
  88 +#endif /* __CONFIG_BEAGLE_X5_H */
include/configs/ti_omap5_common.h
Diff comments   View file @ 1e4ad74
... ... @@ -117,6 +117,8 @@
117 117 "setenv fdtfile dra7-evm.dtb; fi;" \
118 118 "if test $board_name = dra72x; then " \
119 119 "setenv fdtfile dra72-evm.dtb; fi;" \
  120 + "if test $board_name = beagle_x15; then " \
  121 + "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
120 122 "if test $fdtfile = undefined; then " \
121 123 "echo WARNING: Could not determine device tree to use; fi; \0" \
122 124 "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \