Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 1e669b4808c4457fc53f78655748ec625dd3440c

Authored by Thierry Reding
Committed by Tom Warren
1 parent c79aa81dbc
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

ARM: tegra: Rename pcie-controller to pcie 

Recent versions of DTC have checks for PCI host bridge device tree nodes
that are named something other than "pci" or "pcie". Fix all occurrences
of such nodes for Tegra boards to avoid potential warnings from DTC.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

Showing 16 changed files with 16 additions and 16 deletions Side-by-side Diff

arch/arm/dts/tegra124-apalis.dts
Diff comments   View file @ 1e669b4
... ... @@ -77,7 +77,7 @@
77 77 reg = <0x0 0x80000000 0x0 0x80000000>;
78 78 };
79 79  
80   - pcie-controller@01003000 {
  80 + pcie@1003000 {
81 81 status = "okay";
82 82 avddio-pex-supply = <&vdd_1v05>;
83 83 avdd-pex-pll-supply = <&vdd_1v05>;
arch/arm/dts/tegra124-cei-tk1-som.dts
Diff comments   View file @ 1e669b4
... ... @@ -29,7 +29,7 @@
29 29 reg = <0x80000000 0x80000000>;
30 30 };
31 31  
32   - pcie-controller@01003000 {
  32 + pcie@1003000 {
33 33 status = "okay";
34 34  
35 35 avddio-pex-supply = <&vdd_1v05_run>;
arch/arm/dts/tegra124-jetson-tk1.dts
Diff comments   View file @ 1e669b4
... ... @@ -29,7 +29,7 @@
29 29 reg = <0x80000000 0x80000000>;
30 30 };
31 31  
32   - pcie-controller@01003000 {
  32 + pcie@1003000 {
33 33 status = "okay";
34 34  
35 35 avddio-pex-supply = <&vdd_1v05_run>;
arch/arm/dts/tegra124.dtsi
Diff comments   View file @ 1e669b4
... ... @@ -14,7 +14,7 @@
14 14 interrupt-parent = <&lic>;
15 15  
16 16  
17   - pcie-controller@01003000 {
  17 + pcie@1003000 {
18 18 compatible = "nvidia,tegra124-pcie";
19 19 device_type = "pci";
20 20 reg = <0x01003000 0x00000800 /* PADS registers */
arch/arm/dts/tegra186-p2771-0000-000.dts
Diff comments   View file @ 1e669b4
... ... @@ -11,7 +11,7 @@
11 11 power-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 5) GPIO_ACTIVE_HIGH>;
12 12 };
13 13  
14   - pcie-controller@10003000 {
  14 + pcie@10003000 {
15 15 status = "okay";
16 16  
17 17 pci@1,0 {
arch/arm/dts/tegra186-p2771-0000-500.dts
Diff comments   View file @ 1e669b4
... ... @@ -11,7 +11,7 @@
11 11 power-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>;
12 12 };
13 13  
14   - pcie-controller@10003000 {
  14 + pcie@10003000 {
15 15 status = "okay";
16 16  
17 17 pci@1,0 {
arch/arm/dts/tegra186.dtsi
Diff comments   View file @ 1e669b4
... ... @@ -217,7 +217,7 @@
217 217 #interrupt-cells = <2>;
218 218 };
219 219  
220   - pcie-controller@10003000 {
  220 + pcie@10003000 {
221 221 compatible = "nvidia,tegra186-pcie";
222 222 device_type = "pci";
223 223 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */
arch/arm/dts/tegra20-harmony.dts
Diff comments   View file @ 1e669b4
... ... @@ -599,7 +599,7 @@
599 599 nvidia,sys-clock-req-active-high;
600 600 };
601 601  
602   - pcie-controller@80003000 {
  602 + pcie@80003000 {
603 603 status = "okay";
604 604  
605 605 avdd-pex-supply = <&pci_vdd_reg>;
arch/arm/dts/tegra20-trimslice.dts
Diff comments   View file @ 1e669b4
... ... @@ -30,7 +30,7 @@
30 30 spi-max-frequency = <25000000>;
31 31 };
32 32  
33   - pcie-controller@80003000 {
  33 + pcie@80003000 {
34 34 status = "okay";
35 35  
36 36 avdd-pex-supply = <&pci_vdd_reg>;
arch/arm/dts/tegra20.dtsi
Diff comments   View file @ 1e669b4
... ... @@ -580,7 +580,7 @@
580 580 reset-names = "fuse";
581 581 };
582 582  
583   - pcie-controller@80003000 {
  583 + pcie@80003000 {
584 584 compatible = "nvidia,tegra20-pcie";
585 585 device_type = "pci";
586 586 reg = <0x80003000 0x00000800 /* PADS registers */
arch/arm/dts/tegra210-p2371-2180.dts
Diff comments   View file @ 1e669b4
... ... @@ -21,7 +21,7 @@
21 21 reg = <0x0 0x80000000 0x0 0xc0000000>;
22 22 };
23 23  
24   - pcie-controller@01003000 {
  24 + pcie@1003000 {
25 25 status = "okay";
26 26  
27 27 pci@1,0 {
arch/arm/dts/tegra210.dtsi
Diff comments   View file @ 1e669b4
... ... @@ -11,7 +11,7 @@
11 11 #address-cells = <2>;
12 12 #size-cells = <2>;
13 13  
14   - pcie-controller@01003000 {
  14 + pcie@1003000 {
15 15 compatible = "nvidia,tegra210-pcie";
16 16 device_type = "pci";
17 17 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
arch/arm/dts/tegra30-apalis.dts
Diff comments   View file @ 1e669b4
... ... @@ -32,7 +32,7 @@
32 32 reg = <0x80000000 0x40000000>;
33 33 };
34 34  
35   - pcie-controller@00003000 {
  35 + pcie@3000 {
36 36 status = "okay";
37 37 avdd-pexa-supply = <&vdd2_reg>;
38 38 vdd-pexa-supply = <&vdd2_reg>;
arch/arm/dts/tegra30-beaver.dts
Diff comments   View file @ 1e669b4
... ... @@ -28,7 +28,7 @@
28 28 reg = <0x80000000 0x7ff00000>;
29 29 };
30 30  
31   - pcie-controller@00003000 {
  31 + pcie@3000 {
32 32 status = "okay";
33 33  
34 34 avdd-pexa-supply = <&ldo1_reg>;
arch/arm/dts/tegra30-cardhu.dts
Diff comments   View file @ 1e669b4
... ... @@ -27,7 +27,7 @@
27 27 reg = <0x80000000 0x40000000>;
28 28 };
29 29  
30   - pcie-controller@00003000 {
  30 + pcie@3000 {
31 31 status = "okay";
32 32  
33 33 /* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */
arch/arm/dts/tegra30.dtsi
Diff comments   View file @ 1e669b4
... ... @@ -10,7 +10,7 @@
10 10 compatible = "nvidia,tegra30";
11 11 interrupt-parent = <&lic>;
12 12  
13   - pcie-controller@00003000 {
  13 + pcie@3000 {
14 14 compatible = "nvidia,tegra30-pcie";
15 15 device_type = "pci";
16 16 reg = <0x00003000 0x00000800 /* PADS registers */