Commit 1ea4fac5a34604e67504ee6537bb01e809528cd4
Committed by
Tom Rini
Tom Rini
1 parent
4baca92001
Exists in
v2017.01-smarct4x
and in
29 other branches
arm/arm64: Move barrier instructions into separate header
Commit bfb33f0bc45b ("sunxi: mctl_mem_matches: Add missing memory barrier") broke compilation for the Pine64, as dram_helper.c now includes <asm/armv7.h>, which does not compile on arm64. Fix this by moving all barrier instructions into a separate header file, which can easily be shared between arm and arm64. Also extend the inline assembly to take the "sy" argument, which is optional for ARMv7, but mandatory for v8. This fixes compilation for 64-bit sunxi boards (Pine64). Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Showing 3 changed files with 46 additions and 21 deletions Side-by-side Diff
arch/arm/include/asm/armv7.h
| ... | ... | @@ -59,26 +59,7 @@ |
| 59 | 59 | #ifndef __ASSEMBLY__ |
| 60 | 60 | #include <linux/types.h> |
| 61 | 61 | #include <asm/io.h> |
| 62 | - | |
| 63 | -/* | |
| 64 | - * CP15 Barrier instructions | |
| 65 | - * Please note that we have separate barrier instructions in ARMv7 | |
| 66 | - * However, we use the CP15 based instructtions because we use | |
| 67 | - * -march=armv5 in U-Boot | |
| 68 | - */ | |
| 69 | -#define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0)) | |
| 70 | -#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) | |
| 71 | -#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) | |
| 72 | - | |
| 73 | -#ifdef __ARM_ARCH_7A__ | |
| 74 | -#define ISB asm volatile ("isb" : : : "memory") | |
| 75 | -#define DSB asm volatile ("dsb" : : : "memory") | |
| 76 | -#define DMB asm volatile ("dmb" : : : "memory") | |
| 77 | -#else | |
| 78 | -#define ISB CP15ISB | |
| 79 | -#define DSB CP15DSB | |
| 80 | -#define DMB CP15DMB | |
| 81 | -#endif | |
| 62 | +#include <asm/barriers.h> | |
| 82 | 63 | |
| 83 | 64 | /* |
| 84 | 65 | * Workaround for ARM errata # 798870 |
arch/arm/include/asm/barriers.h
| 1 | +/* | |
| 2 | + * Copyright (C) 2016 ARM Ltd. | |
| 3 | + * | |
| 4 | + * ARM and ARM64 barrier instructions | |
| 5 | + * split from armv7.h to allow sharing between ARM and ARM64 | |
| 6 | + * | |
| 7 | + * Original copyright in armv7.h was: | |
| 8 | + * (C) Copyright 2010 Texas Instruments, <www.ti.com> Aneesh V <aneesh@ti.com> | |
| 9 | + * | |
| 10 | + * Much of the original barrier code was contributed by: | |
| 11 | + * Valentine Barshak <valentine.barshak@cogentembedded.com> | |
| 12 | + * | |
| 13 | + * SPDX-License-Identifier: GPL-2.0+ | |
| 14 | + */ | |
| 15 | +#ifndef __BARRIERS_H__ | |
| 16 | +#define __BARRIERS_H__ | |
| 17 | + | |
| 18 | +#ifndef __ASSEMBLY__ | |
| 19 | + | |
| 20 | +#ifndef CONFIG_ARM64 | |
| 21 | +/* | |
| 22 | + * CP15 Barrier instructions | |
| 23 | + * Please note that we have separate barrier instructions in ARMv7 | |
| 24 | + * However, we use the CP15 based instructtions because we use | |
| 25 | + * -march=armv5 in U-Boot | |
| 26 | + */ | |
| 27 | +#define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0)) | |
| 28 | +#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) | |
| 29 | +#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) | |
| 30 | + | |
| 31 | +#endif /* !CONFIG_ARM64 */ | |
| 32 | + | |
| 33 | +#if defined(__ARM_ARCH_7A__) || defined(CONFIG_ARM64) | |
| 34 | +#define ISB asm volatile ("isb sy" : : : "memory") | |
| 35 | +#define DSB asm volatile ("dsb sy" : : : "memory") | |
| 36 | +#define DMB asm volatile ("dmb sy" : : : "memory") | |
| 37 | +#else | |
| 38 | +#define ISB CP15ISB | |
| 39 | +#define DSB CP15DSB | |
| 40 | +#define DMB CP15DMB | |
| 41 | +#endif | |
| 42 | + | |
| 43 | +#endif /* __ASSEMBLY__ */ | |
| 44 | +#endif /* __BARRIERS_H__ */ |