XPedite5200 board support cleanup

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

XPedite5200 board support cleanup
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Peter Tyser · Andrew Fleming-AFLEMING
1 parent ada591d2a0
Showing 10 changed files with 1200 additions and 3 deletions Side-by-side Diff
board/xes/common/actl_nand.c
board/xes/common/fsl_85xx_pci.c
board/xes/xpedite5200/Makefile
board/xes/xpedite5200/config.mk
board/xes/xpedite5200/ddr.c
board/xes/xpedite5200/law.c
board/xes/xpedite5200/tlb.c
board/xes/xpedite5200/u-boot.lds
board/xes/xpedite5200/xpedite5200.c
include/configs/XPEDITE5200.h
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * This driver support NAND devices which have address lines
+ * connected as ALE and CLE inputs.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+
+/*
+ * Hardware specific access to control-lines
+ */
+static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
+{
+	struct nand_chip *this = mtd->priv;
+	ulong IO_ADDR_W;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		IO_ADDR_W = (ulong)this->IO_ADDR_W;
+
+		IO_ADDR_W &= ~(CONFIG_SYS_NAND_ACTL_CLE |
+				CONFIG_SYS_NAND_ACTL_ALE |
+				CONFIG_SYS_NAND_ACTL_NCE);
+		if (ctrl & NAND_CLE)
+			IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_CLE;
+		if (ctrl & NAND_ALE)
+			IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_ALE;
+		if (ctrl & NAND_NCE)
+			IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_NCE;
+
+		this->IO_ADDR_W = (void *)IO_ADDR_W;
+	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->cmd_ctrl = nand_addr_hwcontrol;
+	nand->chip_delay = CONFIG_SYS_NAND_ACTL_DELAY;
+
+	return 0;
+}
@@ -179,7 +179,7 @@
  
 		fsl_pci_init(hose);
  
-		first_free_busno = hose->last_busno+1;
+		first_free_busno = hose->last_busno + 1;
 		printf("    PCI1 on bus %02x - %02x\n",
 			hose->first_busno, hose->last_busno);
 	} else {
@@ -289,7 +289,7 @@
 		if (!host)
 			fsl_pci_config_unlock(hose);
  
-		first_free_busno = hose->last_busno+1;
+		first_free_busno = hose->last_busno + 1;
 		printf("    PCIE2 on bus %02x - %02x\n",
 				hose->first_busno, hose->last_busno);
 	}
@@ -343,7 +343,7 @@
 		if (!host)
 			fsl_pci_config_unlock(hose);
  
-		first_free_busno = hose->last_busno+1;
+		first_free_busno = hose->last_busno + 1;
 		printf("    PCIE3 on bus %02x - %02x\n",
 				hose->first_busno, hose->last_busno);
 	}
+#
+# Copyright 2008 Extreme Engineering Solutions, Inc.
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+#
+# Copyright 2008 Extreme Engineering Solutions, Inc.
+# Copyright 2004, 2007 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# xpedite5200 board
+#
+ifndef TEXT_BASE
+TEXT_BASE = 0xfff80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1
+PLATFORM_CPPFLAGS += -mrelocatable
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void
+get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
+
+	/* We use soldered memory, but use an SPD EEPROM to describe it.
+	 * The SPD has an unspecified dimm type, but the DDR2 initialization
+	 * code requires a specific type to be specified. This sets the type
+	 * as a standard unregistered SO-DIMM. */
+	if (spd->dimm_type == 0) {
+		spd->dimm_type = 0x4;
+		((uchar *)spd)[63] += 0x4;
+	}
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
+			unsigned int ctrl_num)
+{
+	unsigned int i;
+
+	if (ctrl_num) {
+		printf("%s: invalid ctrl_num = %d\n", __func__, ctrl_num);
+		return;
+	}
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++)
+		get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS);
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for clock adjust:
+	 *	- number of chips on bus
+	 *	- position of slot
+	 *	- DDR1 vs. DDR2?
+	 *	- ???
+	 *
+	 * This needs to be determined on a board-by-board basis.
+	 *	0110	3/4 cycle late
+	 *	0111	7/8 cycle late
+	 */
+	popts->clk_adjust = 7;
+
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 9;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#if CONFIG_SYS_PCI1_MEM_PHYS
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCI_1),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAWAR_SIZE_8M, LAW_TRGT_IF_PCI_1),
+#endif
+#if CONFIG_SYS_PCI2_MEM_PHYS
+	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_2),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* W**G* - NOR flashes */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+		0, 0, BOOKE_PAGESZ_256M, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 1, BOOKE_PAGESZ_1M, 1),
+
+	/* *I*G* - NAND flash */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 2, BOOKE_PAGESZ_1M, 1),
+
+#if CONFIG_PCI1
+	/* *I*G* - PCI MEM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 3, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#if CONFIG_PCI2
+	/* *I*G* - PCI MEM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 4, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2)
+	/* *I*G* - PCI IO */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 5, BOOKE_PAGESZ_16M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2004, 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+PHDRS
+{
+  text PT_LOAD;
+  bss PT_LOAD;
+}
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    *(.text)
+    *(.got1)
+   } :text
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  } :text
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  .bootpg ADDR(.text) + 0x7f000 :
+  {
+    cpu/mpc85xx/start.o	(.bootpg)
+  } :text = 0xffff
+
+  .resetvec ADDR(.text) + 0x7fffc :
+  {
+    *(.resetvec)
+  } :text = 0xffff
+
+  . = ADDR(.text) + 0x80000;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  } :bss
+
+  . = ALIGN(4);
+  _end = . ;
+  PROVIDE (end = .);
+}
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2004, 2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/immap_fsl_pci.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pca953x.h>
+
+extern void ft_board_pci_setup(void *blob, bd_t *bd);
+
+int checkboard(void)
+{
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+
+	char *s;
+
+	printf("Board: X-ES %s PMC\n", CONFIG_SYS_BOARD_NAME);
+	printf("       ");
+	s = getenv("board_rev");
+	if (s)
+		printf("Rev %s, ", s);
+	s = getenv("serial#");
+	if (s)
+		printf("Serial# %s, ", s);
+	s = getenv("board_cfg");
+	if (s)
+		printf("Cfg %s", s);
+	printf("\n");
+
+	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
+	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
+	ecm->eedr = 0xffffffff;		/* Clear ecm errors */
+	ecm->eeer = 0xffffffff;		/* Enable ecm errors */
+
+	return 0;
+}
+
+static void flash_cs_fixup(void)
+{
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	int flash_sel;
+
+	/*
+	 * Print boot dev and swap flash flash chip selects if booted from 2nd
+	 * flash.  Swapping chip selects presents user with a common memory
+	 * map regardless of which flash was booted from.
+	 */
+	flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+			CONFIG_SYS_PCA953X_FLASH_PASS_CS));
+	printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
+
+	if (flash_sel) {
+		lbc->br0 = CONFIG_SYS_BR1_PRELIM;
+		lbc->or0 = CONFIG_SYS_OR1_PRELIM;
+
+		lbc->br1 = CONFIG_SYS_BR0_PRELIM;
+		lbc->or1 = CONFIG_SYS_OR0_PRELIM;
+	}
+}
+
+int board_early_init_r(void)
+{
+	/* Initialize PCA9557 devices */
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
+
+	/*
+	 * Remap NOR flash region to caching-inhibited
+	 * so that flash can be erased/programmed properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* Invalidate existing TLB entry for NOR flash */
+	disable_tlb(0);
+	set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+		(CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 0, BOOKE_PAGESZ_256M, 1);
+
+	flash_cs_fixup();
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_PCI
+	ft_board_pci_setup(blob, bd);
+#endif
+	ft_cpu_setup(blob, bd);
+}
+#endif
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2004-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * xpedite5200 board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8548		1
+#define CONFIG_XPEDITE5200	1
+#define CONFIG_SYS_BOARD_NAME	"XPedite5200"
+#define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */
+#define CONFIG_RELOC_FIXUP_WORKS	/* Fully relocate to SDRAM */
+
+#define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#define CONFIG_PCI_PNP		1	/* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
+#define CONFIG_PCI1		1	/* PCI controller 1 */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
+/*
+ * DDR config
+ */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#define SPD_EEPROM_ADDRESS		0x54
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_SYS_CLK_FREQ	66666666
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xef000000	/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
+#define CONFIG_SYS_PCI1_ADDR	(CONFIG_SYS_CCSRBAR + 0x8000)
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x20000000
+
+/*
+ * Memory map
+ * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
+ * 0x8000_0000	0xbfff_ffff	PCI1 Mem		1G non-cacheable
+ * 0xe000_0000	0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
+ * 0xe800_0000	0xe87f_ffff	PCI1 IO			8M non-cacheable
+ * 0xef00_0000	0xef0f_ffff	CCSR/IMMR		1M non-cacheable
+ * 0xef80_0000	0xef8f_ffff	NAND Flash		1M non-cacheable
+ * 0xf800_0000	0xfbff_ffff	NOR Flash 2		64M non-cacheable
+ * 0xfc00_0000	0xffff_ffff	NOR Flash 1		64M non-cacheable
+ */
+
+#define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_4 | LCRR_EADC_3)
+
+/*
+ * NAND flash configuration
+ */
+#define CONFIG_SYS_NAND_BASE		0xef800000
+#define CONFIG_SYS_NAND_BASE2		0xef840000 /* Unused at this time */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_NAND_ACTL
+#define CONFIG_SYS_NAND_ACTL_CLE	(1 << 3)	/* ADDR3 is CLE */
+#define CONFIG_SYS_NAND_ACTL_ALE	(1 << 4)	/* ADDR4 is ALE */
+#define CONFIG_SYS_NAND_ACTL_NCE	(0)		/* NCE not controlled by ADDR */
+#define CONFIG_SYS_NAND_ACTL_DELAY	25
+
+/*
+ * NOR flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		0xfc000000
+#define CONFIG_SYS_FLASH_BASE2		0xf8000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
+						  {0xfbf40000, 0xc0000} }
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+
+/*
+ * Chip select configuration
+ */
+/* NOR Flash 0 on CS0 */
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	| \
+				 BR_PS_16		| \
+				 BR_V)
+#define CONFIG_SYS_OR0_PRELIM	(OR_AM_64MB		| \
+				 OR_GPCM_ACS_DIV4	| \
+				 OR_GPCM_SCY_8)
+
+/* NOR Flash 1 on CS1 */
+#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	| \
+				 BR_PS_16		| \
+				 BR_V)
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	| \
+				 BR_PS_8		| \
+				 BR_V)
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB		| \
+				 OR_GPCM_BCTLD		| \
+				 OR_GPCM_CSNT		| \
+				 OR_GPCM_ACS_DIV4	| \
+				 OR_GPCM_SCY_4		| \
+				 OR_GPCM_TRLX		| \
+				 OR_GPCM_EHTR)
+
+/* NAND flash on CS3 */
+#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	| \
+				 BR_PS_8		| \
+				 BR_V)
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+
+/*
+ * Use L1 as initial stack
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
+#define CONFIG_SYS_INIT_RAM_END		0x4000
+
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * Use the HUSH parser
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+#define CONFIG_SYS_64BIT_VSPRINTF	1
+#define CONFIG_SYS_64BIT_STRTOUL	1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C				/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C				/* I2C with hardware support */
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C2_OFFSET		0x3100
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+
+/* I2C EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T11			1
+#define CONFIG_SYS_I2C_RTC_ADDR			0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR		2000
+
+/* GPIO */
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR0		0x18
+#define CONFIG_SYS_I2C_PCA953X_ADDR1		0x19
+#define CONFIG_SYS_I2C_PCA953X_ADDR		CONFIG_SYS_I2C_PCA953X_ADDR0
+
+/* PCA957 @ 0x18 */
+#define CONFIG_SYS_PCA953X_BRD_CFG0		0x01
+#define CONFIG_SYS_PCA953X_BRD_CFG1		0x02
+#define CONFIG_SYS_PCA953X_BRD_CFG2		0x04
+#define CONFIG_SYS_PCA953X_XMC_ROOT0		0x08
+#define CONFIG_SYS_PCA953X_FLASH_PASS_CS	0x10
+#define CONFIG_SYS_PCA953X_FLASH_WP		0x20
+#define CONFIG_SYS_PCA953X_MONARCH		0x40
+#define CONFIG_SYS_PCA953X_EREADY		0x80
+
+/* PCA957 @ 0x19 */
+#define CONFIG_SYS_PCA953X_P14_IO0		0x01
+#define CONFIG_SYS_PCA953X_P14_IO1		0x02
+#define CONFIG_SYS_PCA953X_P14_IO2		0x04
+#define CONFIG_SYS_PCA953X_P14_IO3		0x08
+#define CONFIG_SYS_PCA953X_P14_IO4		0x10
+#define CONFIG_SYS_PCA953X_P14_IO5		0x20
+#define CONFIG_SYS_PCA953X_P14_IO6		0x40
+#define CONFIG_SYS_PCA953X_P14_IO7		0x80
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x40000000	/* 1G */
+#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS		0xe8000000
+#define CONFIG_SYS_PCI1_IO_SIZE		0x00800000	/* 1M */
+
+/*
+ * Networking options
+ */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#define CONFIG_NET_MULTI	1
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC1_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define CONFIG_HAS_ETH0
+
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define TSEC2_FLAGS		TSEC_GIGABIT
+#define TSEC2_PHY_ADDR		2
+#define TSEC2_PHYIDX		0
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_TSEC3	1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+#define TSEC3_FLAGS		TSEC_GIGABIT
+#define TSEC3_PHY_ADDR		3
+#define TSEC3_PHYIDX		0
+#define CONFIG_HAS_ETH2
+
+#define CONFIG_TSEC4	1
+#define CONFIG_TSEC4_NAME	"eTSEC4"
+#define TSEC4_FLAGS		TSEC_GIGABIT
+#define TSEC4_PHY_ADDR		4
+#define TSEC4_PHYIDX		0
+#define CONFIG_HAS_ETH3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+
+/*
+ * Command configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
+#define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
+#define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
+#define CONFIG_PANIC_HANG			/* do not reset board on panic */
+#define CONFIG_PREBOOT				/* enable preboot variable */
+#define CONFIG_FIT		1
+#define CONFIG_FIT_VERBOSE	1
+#define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
+#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
+
+/*
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02		/* Software reboot */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
+#define CONFIG_ENV_SIZE		0x8000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))
+
+/*
+ * Flash memory map:
+ * fff80000 - ffffffff     Pri U-Boot (512 KB)
+ * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
+ * fff00000 - fff3ffff     Pri FDT (256KB)
+ * fef00000 - ffefffff     Pri OS image (16MB)
+ * fc000000 - feefffff     Pri OS Use/Filesystem (47MB)
+ *
+ * fbf80000 - fbffffff     Sec U-Boot (512 KB)
+ * fbf40000 - fbf7ffff     Sec U-Boot Environment (256 KB)
+ * fbf00000 - fbf3ffff     Sec FDT (256KB)
+ * faf00000 - fbefffff     Sec OS image (16MB)
+ * f8000000 - faefffff     Sec OS Use/Filesystem (47MB)
+ */
+#define CONFIG_UBOOT1_ENV_ADDR	MK_STR(0xfff80000)
+#define CONFIG_UBOOT2_ENV_ADDR	MK_STR(0xfbf80000)
+#define CONFIG_FDT1_ENV_ADDR	MK_STR(0xfff00000)
+#define CONFIG_FDT2_ENV_ADDR	MK_STR(0xfbf00000)
+#define CONFIG_OS1_ENV_ADDR	MK_STR(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR	MK_STR(0xfaf00000)
+
+#define CONFIG_PROG_UBOOT1						\
+	"$download_cmd $loadaddr $ubootfile; "				\
+	"if test $? -eq 0; then "					\
+		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
+		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
+		"if test $? -ne 0; then "				\
+			"echo PROGRAM FAILED; "				\
+		"else; "						\
+			"echo PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_UBOOT2						\
+	"$download_cmd $loadaddr $ubootfile; "				\
+	"if test $? -eq 0; then "					\
+		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
+		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
+		"if test $? -ne 0; then "				\
+			"echo PROGRAM FAILED; "				\
+		"else; "						\
+			"echo PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_BOOT_OS_NET						\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"if test -n $fdtaddr; then "				\
+			"$download_cmd $fdtaddr $fdtfile; "		\
+			"if test $? -eq 0; then "			\
+				"bootm $osaddr - $fdtaddr; "		\
+			"else; "					\
+				"echo FDT DOWNLOAD FAILED; "		\
+			"fi; "						\
+		"else; "						\
+			"bootm $osaddr; "				\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_OS1							\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
+		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
+		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo OS PROGRAM FAILED; "			\
+		"else; "						\
+			"echo OS PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_OS2							\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
+		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
+		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo OS PROGRAM FAILED; "			\
+		"else; "						\
+			"echo OS PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_FDT1						\
+	"$download_cmd $fdtaddr $fdtfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
+		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
+		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo FDT PROGRAM FAILED; "			\
+		"else; "						\
+			"echo FDT PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo FDT DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_FDT2						\
+	"$download_cmd $fdtaddr $fdtfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
+		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
+		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo FDT PROGRAM FAILED; "			\
+		"else; "						\
+			"echo FDT PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo FDT DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"autoload=yes\0"						\
+	"download_cmd=tftp\0"						\
+	"console_args=console=ttyS0,115200\0"				\
+	"root_args=root=/dev/nfs rw\0"					\
+	"misc_args=ip=on\0"						\
+	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
+	"bootfile=/home/user/file\0"					\
+	"osfile=/home/user/uImage-XPedite5200\0"			\
+	"fdtfile=/home/user/xpedite5200.dtb\0"				\
+	"ubootfile=/home/user/u-boot.bin\0"				\
+	"fdtaddr=c00000\0"						\
+	"osaddr=0x1000000\0"						\
+	"loadaddr=0x1000000\0"						\
+	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
+	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
+	"prog_os1="CONFIG_PROG_OS1"\0"					\
+	"prog_os2="CONFIG_PROG_OS2"\0"					\
+	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
+	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
+	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
+	"bootcmd_flash1=run set_bootargs; "				\
+		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
+	"bootcmd_flash2=run set_bootargs; "				\
+		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
+	"bootcmd=run bootcmd_flash1\0"
+#endif	/* __CONFIG_H */
	1	+/*
	2	+ * Copyright 2008 Extreme Engineering Solutions, Inc.
	3	+ *
	4	+ * This driver support NAND devices which have address lines
	5	+ * connected as ALE and CLE inputs.
	6	+ *
	7	+ * See file CREDITS for list of people who contributed to this
	8	+ * project.
	9	+ *
	10	+ * This program is free software; you can redistribute it and/or
	11	+ * modify it under the terms of the GNU General Public License as
	12	+ * published by the Free Software Foundation; either version 2 of
	13	+ * the License, or (at your option) any later version.
	14	+ *
	15	+ * This program is distributed in the hope that it will be useful,
	16	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	+ * GNU General Public License for more details.
	19	+ *
	20	+ * You should have received a copy of the GNU General Public License
	21	+ * along with this program; if not, write to the Free Software
	22	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	+ * MA 02111-1307 USA
	24	+ */
	25	+
	26	+#include <common.h>
	27	+#include <nand.h>
	28	+#include <asm/io.h>
	29	+
	30	+/*
	31	+ * Hardware specific access to control-lines
	32	+ */
	33	+static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
	34	+{
	35	+ struct nand_chip *this = mtd->priv;
	36	+ ulong IO_ADDR_W;
	37	+
	38	+ if (ctrl & NAND_CTRL_CHANGE) {
	39	+ IO_ADDR_W = (ulong)this->IO_ADDR_W;
	40	+
	41	+ IO_ADDR_W &= ~(CONFIG_SYS_NAND_ACTL_CLE \|
	42	+ CONFIG_SYS_NAND_ACTL_ALE \|
	43	+ CONFIG_SYS_NAND_ACTL_NCE);
	44	+ if (ctrl & NAND_CLE)
	45	+ IO_ADDR_W \|= CONFIG_SYS_NAND_ACTL_CLE;
	46	+ if (ctrl & NAND_ALE)
	47	+ IO_ADDR_W \|= CONFIG_SYS_NAND_ACTL_ALE;
	48	+ if (ctrl & NAND_NCE)
	49	+ IO_ADDR_W \|= CONFIG_SYS_NAND_ACTL_NCE;
	50	+
	51	+ this->IO_ADDR_W = (void *)IO_ADDR_W;
	52	+ }
	53	+
	54	+ if (cmd != NAND_CMD_NONE)
	55	+ writeb(cmd, this->IO_ADDR_W);
	56	+}
	57	+
	58	+int board_nand_init(struct nand_chip *nand)
	59	+{
	60	+ nand->ecc.mode = NAND_ECC_SOFT;
	61	+ nand->cmd_ctrl = nand_addr_hwcontrol;
	62	+ nand->chip_delay = CONFIG_SYS_NAND_ACTL_DELAY;
	63	+
	64	+ return 0;
	65	+}
...	...	@@ -179,7 +179,7 @@
179	179
180	180	fsl_pci_init(hose);
181	181
182		- first_free_busno = hose->last_busno+1;
	182	+ first_free_busno = hose->last_busno + 1;
183	183	printf(" PCI1 on bus %02x - %02x\n",
184	184	hose->first_busno, hose->last_busno);
185	185	} else {
...	...	@@ -289,7 +289,7 @@
289	289	if (!host)
290	290	fsl_pci_config_unlock(hose);
291	291
292		- first_free_busno = hose->last_busno+1;
	292	+ first_free_busno = hose->last_busno + 1;
293	293	printf(" PCIE2 on bus %02x - %02x\n",
294	294	hose->first_busno, hose->last_busno);
295	295	}
...	...	@@ -343,7 +343,7 @@
343	343	if (!host)
344	344	fsl_pci_config_unlock(hose);
345	345
346		- first_free_busno = hose->last_busno+1;
	346	+ first_free_busno = hose->last_busno + 1;
347	347	printf(" PCIE3 on bus %02x - %02x\n",
348	348	hose->first_busno, hose->last_busno);
349	349	}
	1	+#
	2	+# Copyright 2008 Extreme Engineering Solutions, Inc.
	3	+# Copyright 2004 Freescale Semiconductor.
	4	+# (C) Copyright 2001-2006
	5	+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	6	+#
	7	+# See file CREDITS for list of people who contributed to this
	8	+# project.
	9	+#
	10	+# This program is free software; you can redistribute it and/or
	11	+# modify it under the terms of the GNU General Public License as
	12	+# published by the Free Software Foundation; either version 2 of
	13	+# the License, or (at your option) any later version.
	14	+#
	15	+# This program is distributed in the hope that it will be useful,
	16	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	+# GNU General Public License for more details.
	19	+#
	20	+# You should have received a copy of the GNU General Public License
	21	+# along with this program; if not, write to the Free Software
	22	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	+# MA 02111-1307 USA
	24	+#
	25	+
	26	+include $(TOPDIR)/config.mk
	27	+
	28	+LIB = $(obj)lib$(BOARD).a
	29	+
	30	+COBJS-y += $(BOARD).o
	31	+COBJS-y += ddr.o
	32	+COBJS-y += law.o
	33	+COBJS-y += tlb.o
	34	+
	35	+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
	36	+OBJS := $(addprefix $(obj),$(COBJS-y))
	37	+SOBJS := $(addprefix $(obj),$(SOBJS-y))
	38	+
	39	+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
	40	+ $(AR) $(ARFLAGS) $@ $(OBJS)
	41	+
	42	+clean:
	43	+ rm -f $(OBJS) $(SOBJS)
	44	+
	45	+distclean: clean
	46	+ rm -f $(LIB) core *.bak .depend
	47	+
	48	+#########################################################################
	49	+
	50	+# defines $(obj).depend target
	51	+include $(SRCTREE)/rules.mk
	52	+
	53	+sinclude $(obj).depend
	54	+
	55	+#########################################################################
	1	+#
	2	+# Copyright 2008 Extreme Engineering Solutions, Inc.
	3	+# Copyright 2004, 2007 Freescale Semiconductor.
	4	+#
	5	+# See file CREDITS for list of people who contributed to this
	6	+# project.
	7	+#
	8	+# This program is free software; you can redistribute it and/or
	9	+# modify it under the terms of the GNU General Public License as
	10	+# published by the Free Software Foundation; either version 2 of
	11	+# the License, or (at your option) any later version.
	12	+#
	13	+# This program is distributed in the hope that it will be useful,
	14	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+# GNU General Public License for more details.
	17	+#
	18	+# You should have received a copy of the GNU General Public License
	19	+# along with this program; if not, write to the Free Software
	20	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+# MA 02111-1307 USA
	22	+#
	23	+
	24	+#
	25	+# xpedite5200 board
	26	+#
	27	+ifndef TEXT_BASE
	28	+TEXT_BASE = 0xfff80000
	29	+endif
	30	+
	31	+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
	32	+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
	33	+PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1
	34	+PLATFORM_CPPFLAGS += -mrelocatable
	1	+/*
	2	+ * Copyright 2008 Freescale Semiconductor, Inc.
	3	+ *
	4	+ * This program is free software; you can redistribute it and/or
	5	+ * modify it under the terms of the GNU General Public License
	6	+ * Version 2 as published by the Free Software Foundation.
	7	+ */
	8	+
	9	+#include <common.h>
	10	+#include <i2c.h>
	11	+
	12	+#include <asm/fsl_ddr_sdram.h>
	13	+#include <asm/fsl_ddr_dimm_params.h>
	14	+
	15	+static void
	16	+get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
	17	+{
	18	+ i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
	19	+
	20	+ /* We use soldered memory, but use an SPD EEPROM to describe it.
	21	+ * The SPD has an unspecified dimm type, but the DDR2 initialization
	22	+ * code requires a specific type to be specified. This sets the type
	23	+ * as a standard unregistered SO-DIMM. */
	24	+ if (spd->dimm_type == 0) {
	25	+ spd->dimm_type = 0x4;
	26	+ ((uchar *)spd)[63] += 0x4;
	27	+ }
	28	+}
	29	+
	30	+unsigned int fsl_ddr_get_mem_data_rate(void)
	31	+{
	32	+ return get_ddr_freq(0);
	33	+}
	34	+
	35	+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
	36	+ unsigned int ctrl_num)
	37	+{
	38	+ unsigned int i;
	39	+
	40	+ if (ctrl_num) {
	41	+ printf("%s: invalid ctrl_num = %d\n", __func__, ctrl_num);
	42	+ return;
	43	+ }
	44	+
	45	+ for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++)
	46	+ get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS);
	47	+}
	48	+
	49	+void fsl_ddr_board_options(memctl_options_t *popts,
	50	+ dimm_params_t *pdimm,
	51	+ unsigned int ctrl_num)
	52	+{
	53	+ /*
	54	+ * Factors to consider for clock adjust:
	55	+ * - number of chips on bus
	56	+ * - position of slot
	57	+ * - DDR1 vs. DDR2?
	58	+ * - ???
	59	+ *
	60	+ * This needs to be determined on a board-by-board basis.
	61	+ * 0110 3/4 cycle late
	62	+ * 0111 7/8 cycle late
	63	+ */
	64	+ popts->clk_adjust = 7;
	65	+
	66	+ /*
	67	+ * Factors to consider for CPO:
	68	+ * - frequency
	69	+ * - ddr1 vs. ddr2
	70	+ */
	71	+ popts->cpo_override = 9;
	72	+
	73	+ /*
	74	+ * Factors to consider for write data delay:
	75	+ * - number of DIMMs
	76	+ *
	77	+ * 1 = 1/4 clock delay
	78	+ * 2 = 1/2 clock delay
	79	+ * 3 = 3/4 clock delay
	80	+ * 4 = 1 clock delay
	81	+ * 5 = 5/4 clock delay
	82	+ * 6 = 3/2 clock delay
	83	+ */
	84	+ popts->write_data_delay = 3;
	85	+
	86	+ /*
	87	+ * Factors to consider for half-strength driver enable:
	88	+ * - number of DIMMs installed
	89	+ */
	90	+ popts->half_strength_driver_enable = 0;
	91	+}
	1	+/*
	2	+ * Copyright 2008 Extreme Engineering Solutions, Inc.
	3	+ * Copyright 2008 Freescale Semiconductor, Inc.
	4	+ *
	5	+ * (C) Copyright 2000
	6	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	7	+ *
	8	+ * See file CREDITS for list of people who contributed to this
	9	+ * project.
	10	+ *
	11	+ * This program is free software; you can redistribute it and/or
	12	+ * modify it under the terms of the GNU General Public License as
	13	+ * published by the Free Software Foundation; either version 2 of
	14	+ * the License, or (at your option) any later version.
	15	+ *
	16	+ * This program is distributed in the hope that it will be useful,
	17	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	+ * GNU General Public License for more details.
	20	+ *
	21	+ * You should have received a copy of the GNU General Public License
	22	+ * along with this program; if not, write to the Free Software
	23	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	+ * MA 02111-1307 USA
	25	+ */
	26	+
	27	+#include <common.h>
	28	+#include <asm/fsl_law.h>
	29	+#include <asm/mmu.h>
	30	+
	31	+/*
	32	+ * Notes:
	33	+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
	34	+ * If flash is 8M at default position (last 8M), no LAW needed.
	35	+ */
	36	+
	37	+struct law_entry law_table[] = {
	38	+ /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
	39	+ SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
	40	+ SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
	41	+#if CONFIG_SYS_PCI1_MEM_PHYS
	42	+ SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCI_1),
	43	+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAWAR_SIZE_8M, LAW_TRGT_IF_PCI_1),
	44	+#endif
	45	+#if CONFIG_SYS_PCI2_MEM_PHYS
	46	+ SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2),
	47	+ SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_2),
	48	+#endif
	49	+};
	50	+
	51	+int num_law_entries = ARRAY_SIZE(law_table);
	1	+/*
	2	+ * Copyright 2008 Extreme Engineering Solutions, Inc.
	3	+ * Copyright 2004, 2007-2008 Freescale Semiconductor, Inc.
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+OUTPUT_ARCH(powerpc)
	25	+/* Do we need any of these for elf?
	26	+ __DYNAMIC = 0; */
	27	+PHDRS
	28	+{
	29	+ text PT_LOAD;
	30	+ bss PT_LOAD;
	31	+}
	32	+
	33	+SECTIONS
	34	+{
	35	+ /* Read-only sections, merged into text segment: */
	36	+ . = + SIZEOF_HEADERS;
	37	+ .interp : { *(.interp) }
	38	+ .hash : { *(.hash) }
	39	+ .dynsym : { *(.dynsym) }
	40	+ .dynstr : { *(.dynstr) }
	41	+ .rel.text : { *(.rel.text) }
	42	+ .rela.text : { *(.rela.text) }
	43	+ .rel.data : { *(.rel.data) }
	44	+ .rela.data : { *(.rela.data) }
	45	+ .rel.rodata : { *(.rel.rodata) }
	46	+ .rela.rodata : { *(.rela.rodata) }
	47	+ .rel.got : { *(.rel.got) }
	48	+ .rela.got : { *(.rela.got) }
	49	+ .rel.ctors : { *(.rel.ctors) }
	50	+ .rela.ctors : { *(.rela.ctors) }
	51	+ .rel.dtors : { *(.rel.dtors) }
	52	+ .rela.dtors : { *(.rela.dtors) }
	53	+ .rel.bss : { *(.rel.bss) }
	54	+ .rela.bss : { *(.rela.bss) }
	55	+ .rel.plt : { *(.rel.plt) }
	56	+ .rela.plt : { *(.rela.plt) }
	57	+ .init : { *(.init) }
	58	+ .plt : { *(.plt) }
	59	+ .text :
	60	+ {
	61	+ *(.text)
	62	+ *(.got1)
	63	+ } :text
	64	+ _etext = .;
	65	+ PROVIDE (etext = .);
	66	+ .rodata :
	67	+ {
	68	+ *(.rodata)
	69	+ *(.rodata1)
	70	+ *(.rodata.str1.4)
	71	+ *(.eh_frame)
	72	+ } :text
	73	+ .fini : { *(.fini) } =0
	74	+ .ctors : { *(.ctors) }
	75	+ .dtors : { *(.dtors) }
	76	+
	77	+ /* Read-write section, merged into data segment: */
	78	+ . = (. + 0x00FF) & 0xFFFFFF00;
	79	+ _erotext = .;
	80	+ PROVIDE (erotext = .);
	81	+ .reloc :
	82	+ {
	83	+ *(.got)
	84	+ _GOT2_TABLE_ = .;
	85	+ *(.got2)
	86	+ _FIXUP_TABLE_ = .;
	87	+ *(.fixup)
	88	+ }
	89	+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
	90	+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
	91	+
	92	+ .data :
	93	+ {
	94	+ *(.data)
	95	+ *(.data1)
	96	+ *(.sdata)
	97	+ *(.sdata2)
	98	+ *(.dynamic)
	99	+ CONSTRUCTORS
	100	+ }
	101	+ _edata = .;
	102	+ PROVIDE (edata = .);
	103	+
	104	+ . = .;
	105	+ __u_boot_cmd_start = .;
	106	+ .u_boot_cmd : { *(.u_boot_cmd) }
	107	+ __u_boot_cmd_end = .;
	108	+
	109	+ . = .;
	110	+ __start___ex_table = .;
	111	+ __ex_table : { *(__ex_table) }
	112	+ __stop___ex_table = .;
	113	+
	114	+ . = ALIGN(256);
	115	+ __init_begin = .;
	116	+ .text.init : { *(.text.init) }
	117	+ .data.init : { *(.data.init) }
	118	+ . = ALIGN(256);
	119	+ __init_end = .;
	120	+
	121	+ .bootpg ADDR(.text) + 0x7f000 :
	122	+ {
	123	+ cpu/mpc85xx/start.o (.bootpg)
	124	+ } :text = 0xffff
	125	+
	126	+ .resetvec ADDR(.text) + 0x7fffc :
	127	+ {
	128	+ *(.resetvec)
	129	+ } :text = 0xffff
	130	+
	131	+ . = ADDR(.text) + 0x80000;
	132	+
	133	+ __bss_start = .;
	134	+ .bss (NOLOAD) :
	135	+ {
	136	+ (.sbss) (.scommon)
	137	+ *(.dynbss)
	138	+ *(.bss)
	139	+ *(COMMON)
	140	+ } :bss
	141	+
	142	+ . = ALIGN(4);
	143	+ _end = . ;
	144	+ PROVIDE (end = .);
	145	+}
	1	+/*
	2	+ * Copyright 2008 Extreme Engineering Solutions, Inc.
	3	+ * Copyright 2004, 2007 Freescale Semiconductor, Inc.
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+#include <common.h>
	25	+#include <command.h>
	26	+#include <pci.h>
	27	+#include <asm/processor.h>
	28	+#include <asm/immap_85xx.h>
	29	+#include <asm/immap_fsl_pci.h>
	30	+#include <asm/io.h>
	31	+#include <asm/cache.h>
	32	+#include <asm/mmu.h>
	33	+#include <libfdt.h>
	34	+#include <fdt_support.h>
	35	+#include <pca953x.h>
	36	+
	37	+extern void ft_board_pci_setup(void blob, bd_t bd);
	38	+
	39	+int checkboard(void)
	40	+{
	41	+ volatile ccsr_lbc_t lbc = (void )(CONFIG_SYS_MPC85xx_LBC_ADDR);
	42	+ volatile ccsr_local_ecm_t ecm = (void )(CONFIG_SYS_MPC85xx_ECM_ADDR);
	43	+
	44	+ char *s;
	45	+
	46	+ printf("Board: X-ES %s PMC\n", CONFIG_SYS_BOARD_NAME);
	47	+ printf(" ");
	48	+ s = getenv("board_rev");
	49	+ if (s)
	50	+ printf("Rev %s, ", s);
	51	+ s = getenv("serial#");
	52	+ if (s)
	53	+ printf("Serial# %s, ", s);
	54	+ s = getenv("board_cfg");
	55	+ if (s)
	56	+ printf("Cfg %s", s);
	57	+ printf("\n");
	58	+
	59	+ lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
	60	+ lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
	61	+ ecm->eedr = 0xffffffff; /* Clear ecm errors */
	62	+ ecm->eeer = 0xffffffff; /* Enable ecm errors */
	63	+
	64	+ return 0;
	65	+}
	66	+
	67	+static void flash_cs_fixup(void)
	68	+{
	69	+ volatile ccsr_lbc_t lbc = (void )(CONFIG_SYS_MPC85xx_LBC_ADDR);
	70	+ int flash_sel;
	71	+
	72	+ /*
	73	+ * Print boot dev and swap flash flash chip selects if booted from 2nd
	74	+ * flash. Swapping chip selects presents user with a common memory
	75	+ * map regardless of which flash was booted from.
	76	+ */
	77	+ flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
	78	+ CONFIG_SYS_PCA953X_FLASH_PASS_CS));
	79	+ printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
	80	+
	81	+ if (flash_sel) {
	82	+ lbc->br0 = CONFIG_SYS_BR1_PRELIM;
	83	+ lbc->or0 = CONFIG_SYS_OR1_PRELIM;
	84	+
	85	+ lbc->br1 = CONFIG_SYS_BR0_PRELIM;
	86	+ lbc->or1 = CONFIG_SYS_OR0_PRELIM;
	87	+ }
	88	+}
	89	+
	90	+int board_early_init_r(void)
	91	+{
	92	+ /* Initialize PCA9557 devices */
	93	+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
	94	+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
	95	+
	96	+ /*
	97	+ * Remap NOR flash region to caching-inhibited
	98	+ * so that flash can be erased/programmed properly.
	99	+ */
	100	+
	101	+ /* Flush d-cache and invalidate i-cache of any FLASH data */
	102	+ flush_dcache();
	103	+ invalidate_icache();
	104	+
	105	+ /* Invalidate existing TLB entry for NOR flash */
	106	+ disable_tlb(0);
	107	+ set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
	108	+ (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
	109	+ MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	110	+ 0, 0, BOOKE_PAGESZ_256M, 1);
	111	+
	112	+ flash_cs_fixup();
	113	+
	114	+ return 0;
	115	+}
	116	+
	117	+#if defined(CONFIG_OF_BOARD_SETUP)
	118	+void ft_board_setup(void blob, bd_t bd)
	119	+{
	120	+#ifdef CONFIG_PCI
	121	+ ft_board_pci_setup(blob, bd);
	122	+#endif
	123	+ ft_cpu_setup(blob, bd);
	124	+}
	125	+#endif
	1	+/*
	2	+ * Copyright 2008 Extreme Engineering Solutions, Inc.
	3	+ * Copyright 2004-2008 Freescale Semiconductor, Inc.
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+/*
	25	+ * xpedite5200 board configuration file
	26	+ */
	27	+#ifndef __CONFIG_H
	28	+#define __CONFIG_H
	29	+
	30	+/*
	31	+ * High Level Configuration Options
	32	+ */
	33	+#define CONFIG_BOOKE 1 /* BOOKE */
	34	+#define CONFIG_E500 1 /* BOOKE e500 family */
	35	+#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
	36	+#define CONFIG_MPC8548 1
	37	+#define CONFIG_XPEDITE5200 1
	38	+#define CONFIG_SYS_BOARD_NAME "XPedite5200"
	39	+#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
	40	+#define CONFIG_RELOC_FIXUP_WORKS /* Fully relocate to SDRAM */
	41	+
	42	+#define CONFIG_PCI 1 /* Enable PCI/PCIE */
	43	+#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
	44	+#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
	45	+#define CONFIG_PCI1 1 /* PCI controller 1 */
	46	+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
	47	+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
	48	+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
	49	+
	50	+/*
	51	+ * DDR config
	52	+ */
	53	+#define CONFIG_FSL_DDR2
	54	+#undef CONFIG_FSL_DDR_INTERACTIVE
	55	+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
	56	+#define CONFIG_DDR_SPD
	57	+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	58	+#define SPD_EEPROM_ADDRESS 0x54
	59	+#define CONFIG_NUM_DDR_CONTROLLERS 1
	60	+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	61	+#define CONFIG_CHIP_SELECTS_PER_CTRL 2
	62	+#define CONFIG_DDR_ECC
	63	+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
	64	+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
	65	+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	66	+#define CONFIG_VERY_BIG_RAM
	67	+
	68	+#define CONFIG_SYS_CLK_FREQ 66666666
	69	+
	70	+/*
	71	+ * These can be toggled for performance analysis, otherwise use default.
	72	+ */
	73	+#define CONFIG_L2_CACHE /* toggle L2 cache */
	74	+#define CONFIG_BTB /* toggle branch predition */
	75	+#define CONFIG_ENABLE_36BIT_PHYS 1
	76	+
	77	+/*
	78	+ * Base addresses -- Note these are effective addresses where the
	79	+ * actual resources get mapped (not physical addresses)
	80	+ */
	81	+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
	82	+#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
	83	+#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
	84	+#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
	85	+#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000)
	86	+
	87	+/*
	88	+ * Diagnostics
	89	+ */
	90	+#define CONFIG_SYS_ALT_MEMTEST
	91	+#define CONFIG_SYS_MEMTEST_START 0x10000000
	92	+#define CONFIG_SYS_MEMTEST_END 0x20000000
	93	+
	94	+/*
	95	+ * Memory map
	96	+ * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
	97	+ * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable
	98	+ * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
	99	+ * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable
	100	+ * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
	101	+ * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
	102	+ * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable
	103	+ * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable
	104	+ */
	105	+
	106	+#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 \| LCRR_EADC_3)
	107	+
	108	+/*
	109	+ * NAND flash configuration
	110	+ */
	111	+#define CONFIG_SYS_NAND_BASE 0xef800000
	112	+#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
	113	+#define CONFIG_SYS_MAX_NAND_DEVICE 1
	114	+#define CONFIG_NAND_ACTL
	115	+#define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */
	116	+#define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */
	117	+#define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */
	118	+#define CONFIG_SYS_NAND_ACTL_DELAY 25
	119	+
	120	+/*
	121	+ * NOR flash configuration
	122	+ */
	123	+#define CONFIG_SYS_FLASH_BASE 0xfc000000
	124	+#define CONFIG_SYS_FLASH_BASE2 0xf8000000
	125	+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
	126	+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
	127	+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	128	+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	129	+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	130	+#define CONFIG_FLASH_CFI_DRIVER
	131	+#define CONFIG_SYS_FLASH_CFI
	132	+#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
	133	+ {0xfbf40000, 0xc0000} }
	134	+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
	135	+
	136	+/*
	137	+ * Chip select configuration
	138	+ */
	139	+/* NOR Flash 0 on CS0 */
	140	+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \| \
	141	+ BR_PS_16 \| \
	142	+ BR_V)
	143	+#define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB \| \
	144	+ OR_GPCM_ACS_DIV4 \| \
	145	+ OR_GPCM_SCY_8)
	146	+
	147	+/* NOR Flash 1 on CS1 */
	148	+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 \| \
	149	+ BR_PS_16 \| \
	150	+ BR_V)
	151	+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
	152	+
	153	+/* NAND flash on CS2 */
	154	+#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE \| \
	155	+ BR_PS_8 \| \
	156	+ BR_V)
	157	+
	158	+/* NAND flash on CS2 */
	159	+#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB \| \
	160	+ OR_GPCM_BCTLD \| \
	161	+ OR_GPCM_CSNT \| \
	162	+ OR_GPCM_ACS_DIV4 \| \
	163	+ OR_GPCM_SCY_4 \| \
	164	+ OR_GPCM_TRLX \| \
	165	+ OR_GPCM_EHTR)
	166	+
	167	+/* NAND flash on CS3 */
	168	+#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 \| \
	169	+ BR_PS_8 \| \
	170	+ BR_V)
	171	+#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
	172	+
	173	+/*
	174	+ * Use L1 as initial stack
	175	+ */
	176	+#define CONFIG_SYS_INIT_RAM_LOCK 1
	177	+#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
	178	+#define CONFIG_SYS_INIT_RAM_END 0x4000
	179	+
	180	+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
	181	+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	182	+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	183	+
	184	+#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
	185	+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
	186	+
	187	+/*
	188	+ * Serial Port
	189	+ */
	190	+#define CONFIG_CONS_INDEX 1
	191	+#define CONFIG_SYS_NS16550
	192	+#define CONFIG_SYS_NS16550_SERIAL
	193	+#define CONFIG_SYS_NS16550_REG_SIZE 1
	194	+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	195	+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
	196	+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
	197	+#define CONFIG_SYS_BAUDRATE_TABLE \
	198	+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
	199	+#define CONFIG_BAUDRATE 115200
	200	+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	201	+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	202	+
	203	+/*
	204	+ * Use the HUSH parser
	205	+ */
	206	+#define CONFIG_SYS_HUSH_PARSER
	207	+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	208	+
	209	+/*
	210	+ * Pass open firmware flat tree
	211	+ */
	212	+#define CONFIG_OF_LIBFDT 1
	213	+#define CONFIG_OF_BOARD_SETUP 1
	214	+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
	215	+
	216	+#define CONFIG_SYS_64BIT_VSPRINTF 1
	217	+#define CONFIG_SYS_64BIT_STRTOUL 1
	218	+
	219	+/*
	220	+ * I2C
	221	+ */
	222	+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
	223	+#define CONFIG_HARD_I2C /* I2C with hardware support */
	224	+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
	225	+#define CONFIG_SYS_I2C_SLAVE 0x7F
	226	+#define CONFIG_SYS_I2C_OFFSET 0x3000
	227	+#define CONFIG_SYS_I2C2_OFFSET 0x3100
	228	+#define CONFIG_I2C_MULTI_BUS
	229	+#define CONFIG_I2C_CMD_TREE
	230	+
	231	+/* I2C EEPROM */
	232	+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	233	+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	234	+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
	235	+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
	236	+
	237	+/* I2C RTC */
	238	+#define CONFIG_RTC_M41T11 1
	239	+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	240	+#define CONFIG_SYS_M41T11_BASE_YEAR 2000
	241	+
	242	+/* GPIO */
	243	+#define CONFIG_PCA953X
	244	+#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
	245	+#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19
	246	+#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
	247	+
	248	+/* PCA957 @ 0x18 */
	249	+#define CONFIG_SYS_PCA953X_BRD_CFG0 0x01
	250	+#define CONFIG_SYS_PCA953X_BRD_CFG1 0x02
	251	+#define CONFIG_SYS_PCA953X_BRD_CFG2 0x04
	252	+#define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08
	253	+#define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10
	254	+#define CONFIG_SYS_PCA953X_FLASH_WP 0x20
	255	+#define CONFIG_SYS_PCA953X_MONARCH 0x40
	256	+#define CONFIG_SYS_PCA953X_EREADY 0x80
	257	+
	258	+/* PCA957 @ 0x19 */
	259	+#define CONFIG_SYS_PCA953X_P14_IO0 0x01
	260	+#define CONFIG_SYS_PCA953X_P14_IO1 0x02
	261	+#define CONFIG_SYS_PCA953X_P14_IO2 0x04
	262	+#define CONFIG_SYS_PCA953X_P14_IO3 0x08
	263	+#define CONFIG_SYS_PCA953X_P14_IO4 0x10
	264	+#define CONFIG_SYS_PCA953X_P14_IO5 0x20
	265	+#define CONFIG_SYS_PCA953X_P14_IO6 0x40
	266	+#define CONFIG_SYS_PCA953X_P14_IO7 0x80
	267	+
	268	+/*
	269	+ * General PCI
	270	+ * Memory space is mapped 1-1, but I/O space must start from 0.
	271	+ */
	272	+#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
	273	+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
	274	+#define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */
	275	+#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
	276	+#define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000
	277	+#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */
	278	+
	279	+/*
	280	+ * Networking options
	281	+ */
	282	+#define CONFIG_TSEC_ENET /* tsec ethernet support */
	283	+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
	284	+#define CONFIG_NET_MULTI 1
	285	+#define CONFIG_MII 1 /* MII PHY management */
	286	+#define CONFIG_ETHPRIME "eTSEC1"
	287	+
	288	+#define CONFIG_TSEC1 1
	289	+#define CONFIG_TSEC1_NAME "eTSEC1"
	290	+#define TSEC1_FLAGS TSEC_GIGABIT
	291	+#define TSEC1_PHY_ADDR 1
	292	+#define TSEC1_PHYIDX 0
	293	+#define CONFIG_HAS_ETH0
	294	+
	295	+#define CONFIG_TSEC2 1
	296	+#define CONFIG_TSEC2_NAME "eTSEC2"
	297	+#define TSEC2_FLAGS TSEC_GIGABIT
	298	+#define TSEC2_PHY_ADDR 2
	299	+#define TSEC2_PHYIDX 0
	300	+#define CONFIG_HAS_ETH1
	301	+
	302	+#define CONFIG_TSEC3 1
	303	+#define CONFIG_TSEC3_NAME "eTSEC3"
	304	+#define TSEC3_FLAGS TSEC_GIGABIT
	305	+#define TSEC3_PHY_ADDR 3
	306	+#define TSEC3_PHYIDX 0
	307	+#define CONFIG_HAS_ETH2
	308	+
	309	+#define CONFIG_TSEC4 1
	310	+#define CONFIG_TSEC4_NAME "eTSEC4"
	311	+#define TSEC4_FLAGS TSEC_GIGABIT
	312	+#define TSEC4_PHY_ADDR 4
	313	+#define TSEC4_PHYIDX 0
	314	+#define CONFIG_HAS_ETH3
	315	+
	316	+/*
	317	+ * BOOTP options
	318	+ */
	319	+#define CONFIG_BOOTP_BOOTFILESIZE
	320	+#define CONFIG_BOOTP_BOOTPATH
	321	+#define CONFIG_BOOTP_GATEWAY
	322	+
	323	+/*
	324	+ * Command configuration.
	325	+ */
	326	+#include <config_cmd_default.h>
	327	+
	328	+#define CONFIG_CMD_ASKENV
	329	+#define CONFIG_CMD_DATE
	330	+#define CONFIG_CMD_DHCP
	331	+#define CONFIG_CMD_EEPROM
	332	+#define CONFIG_CMD_ELF
	333	+#define CONFIG_CMD_ENV
	334	+#define CONFIG_CMD_FLASH
	335	+#define CONFIG_CMD_I2C
	336	+#define CONFIG_CMD_JFFS2
	337	+#define CONFIG_CMD_MII
	338	+#define CONFIG_CMD_NAND
	339	+#define CONFIG_CMD_NET
	340	+#define CONFIG_CMD_PCA953X
	341	+#define CONFIG_CMD_PCA953X_INFO
	342	+#define CONFIG_CMD_PCI
	343	+#define CONFIG_CMD_PING
	344	+#define CONFIG_CMD_SNTP
	345	+
	346	+/*
	347	+ * Miscellaneous configurable options
	348	+ */
	349	+#define CONFIG_SYS_LONGHELP /* undef to save memory */
	350	+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
	351	+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
	352	+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	353	+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	354	+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	355	+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	356	+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
	357	+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
	358	+#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
	359	+#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
	360	+#define CONFIG_PANIC_HANG /* do not reset board on panic */
	361	+#define CONFIG_PREBOOT /* enable preboot variable */
	362	+#define CONFIG_FIT 1
	363	+#define CONFIG_FIT_VERBOSE 1
	364	+#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
	365	+#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
	366	+
	367	+/*
	368	+ * For booting Linux, the board info and command line data
	369	+ * have to be in the first 16 MB of memory, since this is
	370	+ * the maximum mapped by the Linux kernel during initialization.
	371	+ */
	372	+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
	373	+
	374	+/*
	375	+ * Boot Flags
	376	+ */
	377	+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	378	+#define BOOTFLAG_WARM 0x02 /* Software reboot */
	379	+
	380	+/*
	381	+ * Environment Configuration
	382	+ */
	383	+#define CONFIG_ENV_IS_IN_FLASH 1
	384	+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
	385	+#define CONFIG_ENV_SIZE 0x8000
	386	+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
	387	+
	388	+/*
	389	+ * Flash memory map:
	390	+ * fff80000 - ffffffff Pri U-Boot (512 KB)
	391	+ * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
	392	+ * fff00000 - fff3ffff Pri FDT (256KB)
	393	+ * fef00000 - ffefffff Pri OS image (16MB)
	394	+ * fc000000 - feefffff Pri OS Use/Filesystem (47MB)
	395	+ *
	396	+ * fbf80000 - fbffffff Sec U-Boot (512 KB)
	397	+ * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB)
	398	+ * fbf00000 - fbf3ffff Sec FDT (256KB)
	399	+ * faf00000 - fbefffff Sec OS image (16MB)
	400	+ * f8000000 - faefffff Sec OS Use/Filesystem (47MB)
	401	+ */
	402	+#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000)
	403	+#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xfbf80000)
	404	+#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000)
	405	+#define CONFIG_FDT2_ENV_ADDR MK_STR(0xfbf00000)
	406	+#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
	407	+#define CONFIG_OS2_ENV_ADDR MK_STR(0xfaf00000)
	408	+
	409	+#define CONFIG_PROG_UBOOT1 \
	410	+ "$download_cmd $loadaddr $ubootfile; " \
	411	+ "if test $? -eq 0; then " \
	412	+ "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
	413	+ "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
	414	+ "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
	415	+ "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
	416	+ "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
	417	+ "if test $? -ne 0; then " \
	418	+ "echo PROGRAM FAILED; " \
	419	+ "else; " \
	420	+ "echo PROGRAM SUCCEEDED; " \
	421	+ "fi; " \
	422	+ "else; " \
	423	+ "echo DOWNLOAD FAILED; " \
	424	+ "fi;"
	425	+
	426	+#define CONFIG_PROG_UBOOT2 \
	427	+ "$download_cmd $loadaddr $ubootfile; " \
	428	+ "if test $? -eq 0; then " \
	429	+ "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
	430	+ "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
	431	+ "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
	432	+ "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
	433	+ "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
	434	+ "if test $? -ne 0; then " \
	435	+ "echo PROGRAM FAILED; " \
	436	+ "else; " \
	437	+ "echo PROGRAM SUCCEEDED; " \
	438	+ "fi; " \
	439	+ "else; " \
	440	+ "echo DOWNLOAD FAILED; " \
	441	+ "fi;"
	442	+
	443	+#define CONFIG_BOOT_OS_NET \
	444	+ "$download_cmd $osaddr $osfile; " \
	445	+ "if test $? -eq 0; then " \
	446	+ "if test -n $fdtaddr; then " \
	447	+ "$download_cmd $fdtaddr $fdtfile; " \
	448	+ "if test $? -eq 0; then " \
	449	+ "bootm $osaddr - $fdtaddr; " \
	450	+ "else; " \
	451	+ "echo FDT DOWNLOAD FAILED; " \
	452	+ "fi; " \
	453	+ "else; " \
	454	+ "bootm $osaddr; " \
	455	+ "fi; " \
	456	+ "else; " \
	457	+ "echo OS DOWNLOAD FAILED; " \
	458	+ "fi;"
	459	+
	460	+#define CONFIG_PROG_OS1 \
	461	+ "$download_cmd $osaddr $osfile; " \
	462	+ "if test $? -eq 0; then " \
	463	+ "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
	464	+ "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
	465	+ "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
	466	+ "if test $? -ne 0; then " \
	467	+ "echo OS PROGRAM FAILED; " \
	468	+ "else; " \
	469	+ "echo OS PROGRAM SUCCEEDED; " \
	470	+ "fi; " \
	471	+ "else; " \
	472	+ "echo OS DOWNLOAD FAILED; " \
	473	+ "fi;"
	474	+
	475	+#define CONFIG_PROG_OS2 \
	476	+ "$download_cmd $osaddr $osfile; " \
	477	+ "if test $? -eq 0; then " \
	478	+ "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
	479	+ "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
	480	+ "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
	481	+ "if test $? -ne 0; then " \
	482	+ "echo OS PROGRAM FAILED; " \
	483	+ "else; " \
	484	+ "echo OS PROGRAM SUCCEEDED; " \
	485	+ "fi; " \
	486	+ "else; " \
	487	+ "echo OS DOWNLOAD FAILED; " \
	488	+ "fi;"
	489	+
	490	+#define CONFIG_PROG_FDT1 \
	491	+ "$download_cmd $fdtaddr $fdtfile; " \
	492	+ "if test $? -eq 0; then " \
	493	+ "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
	494	+ "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
	495	+ "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
	496	+ "if test $? -ne 0; then " \
	497	+ "echo FDT PROGRAM FAILED; " \
	498	+ "else; " \
	499	+ "echo FDT PROGRAM SUCCEEDED; " \
	500	+ "fi; " \
	501	+ "else; " \
	502	+ "echo FDT DOWNLOAD FAILED; " \
	503	+ "fi;"
	504	+
	505	+#define CONFIG_PROG_FDT2 \
	506	+ "$download_cmd $fdtaddr $fdtfile; " \
	507	+ "if test $? -eq 0; then " \
	508	+ "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
	509	+ "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
	510	+ "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
	511	+ "if test $? -ne 0; then " \
	512	+ "echo FDT PROGRAM FAILED; " \
	513	+ "else; " \
	514	+ "echo FDT PROGRAM SUCCEEDED; " \
	515	+ "fi; " \
	516	+ "else; " \
	517	+ "echo FDT DOWNLOAD FAILED; " \
	518	+ "fi;"
	519	+
	520	+#define CONFIG_EXTRA_ENV_SETTINGS \
	521	+ "autoload=yes\0" \
	522	+ "download_cmd=tftp\0" \
	523	+ "console_args=console=ttyS0,115200\0" \
	524	+ "root_args=root=/dev/nfs rw\0" \
	525	+ "misc_args=ip=on\0" \
	526	+ "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
	527	+ "bootfile=/home/user/file\0" \
	528	+ "osfile=/home/user/uImage-XPedite5200\0" \
	529	+ "fdtfile=/home/user/xpedite5200.dtb\0" \
	530	+ "ubootfile=/home/user/u-boot.bin\0" \
	531	+ "fdtaddr=c00000\0" \
	532	+ "osaddr=0x1000000\0" \
	533	+ "loadaddr=0x1000000\0" \
	534	+ "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
	535	+ "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
	536	+ "prog_os1="CONFIG_PROG_OS1"\0" \
	537	+ "prog_os2="CONFIG_PROG_OS2"\0" \
	538	+ "prog_fdt1="CONFIG_PROG_FDT1"\0" \
	539	+ "prog_fdt2="CONFIG_PROG_FDT2"\0" \
	540	+ "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
	541	+ "bootcmd_flash1=run set_bootargs; " \
	542	+ "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
	543	+ "bootcmd_flash2=run set_bootargs; " \
	544	+ "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
	545	+ "bootcmd=run bootcmd_flash1\0"
	546	+#endif /* __CONFIG_H */