Add initial support for Matrix Vision mvSMR board based on MPC5200B.

Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>

Add initial support for Matrix Vision mvSMR board based on MPC5200B.
Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Andre Schwarz · Wolfgang Denk
1 parent 9acd4f0e91
Showing 14 changed files with 1088 additions and 1 deletions Side-by-side Diff
CREDITS
MAINTAINERS
MAKEALL
Makefile
board/matrix_vision/mvsmr/Makefile
board/matrix_vision/mvsmr/bootscript
board/matrix_vision/mvsmr/config.mk
board/matrix_vision/mvsmr/fpga.c
board/matrix_vision/mvsmr/fpga.h
board/matrix_vision/mvsmr/mvsmr.c
board/matrix_vision/mvsmr/mvsmr.h
board/matrix_vision/mvsmr/u-boot.lds
doc/README.mvsmr
include/configs/MVSMR.h
@@ -437,7 +437,7 @@
  
 N: Andre Schwarz
 E: andre.schwarz@matrix-vision.de
-D: Support for Matrix Vision boards (MVBLM7/MVBC_P)
+D: Support for Matrix Vision boards (MVBLM7/MVBC_P/MVSMR)
  
 N: Robert Schwebel
 E: r.schwebel@pengutronix.de
@@ -422,6 +422,7 @@
  
 	mvbc_p		MPC5200
 	mvblm7		MPC8343
+	mvsmr		MPC5200
  
 Jon Smirl <jonsmirl@gmail.com>
  
@@ -70,6 +70,7 @@
 	motionpro	\
 	munices		\
 	MVBC_P		\
+	MVSMR		\
 	o2dnt		\
 	pcm030		\
 	pf5200		\
@@ -664,6 +664,11 @@
 	{   	echo "#define CONFIG_MVBC_P" 	>>$(obj)include/config.h; }
 	@$(MKCONFIG) -n $@ -a MVBC_P ppc mpc5xxx mvbc_p matrix_vision
  
+MVSMR_config: unconfig
+	@mkdir -p $(obj)include
+	@mkdir -p $(obj)board/matrix_vision/mvsmr
+	@$(MKCONFIG) $(@:_config=) ppc mpc5xxx mvsmr matrix_vision
+
 o2dnt_config:	unconfig
 	@$(MKCONFIG) o2dnt ppc mpc5xxx o2dnt
  
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004-2008
+# Matrix-Vision GmbH, info@matrix-vision.de
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o fpga.o
+
+SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+	        $(AR) $(ARFLAGS) $@ $(OBJS)
+	@mkimage -T script -C none -n mvSMR_Script -d bootscript bootscript.img
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+echo
+echo "==== running autoscript ===="
+echo
+setenv boot24 'bootm ${kernel_boot} ${mv_initrd_addr_ram}'
+setenv ramkernel 'setenv kernel_boot ${loadaddr}'
+setenv flashkernel 'setenv kernel_boot ${mv_kernel_addr}'
+setenv cpird 'cp ${mv_initrd_addr} ${mv_initrd_addr_ram} ${mv_initrd_length}'
+setenv bootfromflash run flashkernel cpird addcons boot24
+setenv bootfromnet 'tftp ${mv_initrd_addr_ram} ${initrd_name};run ramkernel'
+if test ${console} = yes;
+then
+setenv addcons 'setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8'
+else
+setenv addcons 'setenv bootargs ${bootargs} console=tty0'
+fi
+setenv set_static_ip 'setenv ipaddr ${static_ipaddr}'
+setenv set_static_nm 'setenv netmask ${static_netmask}'
+setenv set_static_gw 'setenv gatewayip ${static_gateway}'
+setenv set_ip 'setenv ip ${ipaddr}::${gatewayip}:${netmask}'
+if test ${servicemode} != yes;
+then
+  echo "=== forced flash mode ==="
+  run set_static_ip set_static_nm set_static_gw set_ip bootfromflash
+fi
+if test ${autoscript_boot} != no;
+then
+  if test ${netboot} = yes;
+  then
+    bootp
+    if test $? = 0;
+    then
+      echo "=== bootp succeeded -> netboot ==="
+      run set_ip bootfromnet addcons boot24
+    else
+      echo "=== netboot failed ==="
+    fi
+  fi
+  echo "=== bootfromflash ==="
+  run set_static_ip set_static_nm set_static_gw set_ip bootfromflash
+else
+  echo "=== boot stopped with autoscript_boot no ==="
+fi
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xFF800000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
+LDSCRIPT := $(SRCTREE)/board/matrix_vision/mvsmr/u-boot.lds
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * (C) Copyright 2010
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <spartan3.h>
+#include <command.h>
+#include <asm/io.h>
+#include "fpga.h"
+#include "mvsmr.h"
+
+Xilinx_Spartan3_Slave_Serial_fns fpga_fns = {
+	fpga_pre_config_fn,
+	fpga_pgm_fn,
+	fpga_clk_fn,
+	fpga_init_fn,
+	fpga_done_fn,
+	fpga_wr_fn,
+	0
+};
+
+Xilinx_desc spartan3 = {
+	Xilinx_Spartan2,
+	slave_serial,
+	XILINX_XC3S200_SIZE,
+	(void *) &fpga_fns,
+	0,
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mvsmr_init_fpga(void)
+{
+	fpga_init();
+	fpga_add(fpga_xilinx, &spartan3);
+
+	return 1;
+}
+
+int fpga_init_fn(int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+	if (in_be32(&gpio->simple_ival) & FPGA_CONFIG)
+		return 0;
+
+	return 1;
+}
+
+int fpga_done_fn(int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	int result = 0;
+
+	udelay(10);
+	if (in_be32(&gpio->simple_ival) & FPGA_DONE)
+		result = 1;
+
+	return result;
+}
+
+int fpga_pgm_fn(int assert, int flush, int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+	if (!assert)
+		setbits_8(&gpio->sint_dvo, FPGA_STATUS);
+	else
+		clrbits_8(&gpio->sint_dvo, FPGA_STATUS);
+
+	return assert;
+}
+
+int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+	if (assert_clk)
+		setbits_be32(&gpio->simple_dvo, FPGA_CCLK);
+	else
+		clrbits_be32(&gpio->simple_dvo, FPGA_CCLK);
+
+	return assert_clk;
+}
+
+int fpga_wr_fn(int assert_write, int flush, int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+	if (assert_write)
+		setbits_be32(&gpio->simple_dvo, FPGA_DIN);
+	else
+		clrbits_be32(&gpio->simple_dvo, FPGA_DIN);
+
+	return assert_write;
+}
+
+int fpga_pre_config_fn(int cookie)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+	setbits_8(&gpio->sint_dvo, FPGA_STATUS);
+
+	return 0;
+}
+/*
+ * (C) Copyright 2008
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+extern int mvsmr_init_fpga(void);
+
+extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
+extern int fpga_init_fn(int cookie);
+extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
+extern int fpga_wr_fn(int assert_write, int flush, int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_pre_config_fn(int cookie);
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2005-2010
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <malloc.h>
+#include <pci.h>
+#include <i2c.h>
+#include <fpga.h>
+#include <environment.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include "fpga.h"
+#include "mvsmr.h"
+#include "../common/mv_common.h"
+
+#define SDRAM_DDR	1
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x715f0f00
+#define SDRAM_CONFIG1	0xd3722930
+#define SDRAM_CONFIG2	0x46770000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void sdram_start(int hi_addr)
+{
+	long hi_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 |
+		hi_bit);
+
+	/* precharge all banks */
+	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 |
+		hi_bit);
+
+	/* set mode register: extended mode */
+	out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
+
+	/* set mode register: reset DLL */
+	out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
+
+	/* precharge all banks */
+	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 |
+		hi_bit);
+
+	/* auto refresh */
+	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 |
+		hi_bit);
+
+	/* set mode register */
+	out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
+
+	/* normal operation */
+	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit);
+}
+
+phys_addr_t initdram(int board_type)
+{
+	ulong dramsize = 0;
+	ulong test1,
+	      test2;
+
+	/* setup SDRAM chip selects */
+	out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
+
+	/* setup config registers */
+	out_be32((u32 *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
+	out_be32((u32 *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else
+		dramsize = test2;
+
+	if (dramsize < (1 << 20))
+		dramsize = 0;
+
+	if (dramsize > 0)
+		out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x13 +
+			__builtin_ffs(dramsize >> 20) - 1);
+	else
+		out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0);
+
+	return dramsize;
+}
+
+void mvsmr_init_gpio(void)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	struct mpc5xxx_wu_gpio *wu_gpio =
+		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+	struct mpc5xxx_gpt_0_7 *timers = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+
+	printf("Ports : 0x%08x\n", gpio->port_config);
+	printf("PORCFG: 0x%08x\n", in_be32((unsigned *)MPC5XXX_CDM_PORCFG));
+
+	out_be32(&gpio->simple_ddr, SIMPLE_DDR);
+	out_be32(&gpio->simple_dvo, SIMPLE_DVO);
+	out_be32(&gpio->simple_ode, SIMPLE_ODE);
+	out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
+
+	out_8(&gpio->sint_ode, SINT_ODE);
+	out_8(&gpio->sint_ddr, SINT_DDR);
+	out_8(&gpio->sint_dvo, SINT_DVO);
+	out_8(&gpio->sint_inten, SINT_INTEN);
+	out_be16(&gpio->sint_itype, SINT_ITYPE);
+	out_8(&gpio->sint_gpioe, SINT_GPIOEN);
+
+	out_8(&wu_gpio->ode, WKUP_ODE);
+	out_8(&wu_gpio->ddr, WKUP_DIR);
+	out_8(&wu_gpio->dvo, WKUP_DO);
+	out_8(&wu_gpio->enable, WKUP_EN);
+
+	out_be32(&timers->gpt0.emsr, 0x00000234); /* OD output high */
+	out_be32(&timers->gpt1.emsr, 0x00000234);
+	out_be32(&timers->gpt2.emsr, 0x00000234);
+	out_be32(&timers->gpt3.emsr, 0x00000234);
+	out_be32(&timers->gpt4.emsr, 0x00000234);
+	out_be32(&timers->gpt5.emsr, 0x00000234);
+	out_be32(&timers->gpt6.emsr, 0x00000024); /* push-pull output low */
+	out_be32(&timers->gpt7.emsr, 0x00000024);
+}
+
+int misc_init_r(void)
+{
+	char *s = getenv("reset_env");
+
+	if (s) {
+		printf(" === FACTORY RESET ===\n");
+		mv_reset_environment();
+		saveenv();
+	}
+
+	return -1;
+}
+
+void mvsmr_get_dbg_present(void)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
+
+	if (in_be32(&gpio->simple_ival) & COP_PRESENT) {
+		setenv("dbg_present", "no\0");
+		setenv("bootstopkey", "abcdefghijklmnopqrstuvwxyz\0");
+	} else {
+		setenv("dbg_present", "yes\0");
+		setenv("bootstopkey", "s\0");
+		setbits_8(&psc->command, PSC_RX_ENABLE);
+	}
+}
+
+void mvsmr_get_service_mode(void)
+{
+	struct mpc5xxx_wu_gpio *wu_gpio =
+		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+
+	if (in_8(&wu_gpio->ival) & SERVICE_MODE)
+		setenv("servicemode", "no\0");
+	else
+		setenv("servicemode", "yes\0");
+}
+
+int mvsmr_get_mac(void)
+{
+	unsigned char mac[6];
+	struct mpc5xxx_wu_gpio *wu_gpio =
+		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+
+	if (in_8(&wu_gpio->ival) & LAN_PRSNT) {
+		setenv("lan_present", "no\0");
+		return -1;
+	} else
+		setenv("lan_present", "yes\0");
+
+	i2c_read(0x50, 0, 1, mac, 6);
+
+	eth_setenv_enetaddr("ethaddr", mac);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	mvsmr_init_gpio();
+	printf("Board: Matrix Vision mvSMR\n");
+
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	clrbits_be32((u32 *)MPC5XXX_BOOTCS_CFG, 0x1);
+}
+
+void flash_afterinit(ulong size)
+{
+	out_be32((u32 *)MPC5XXX_BOOTCS_START,
+		START_REG(CONFIG_SYS_BOOTCS_START | size));
+	out_be32((u32 *)MPC5XXX_CS0_START,
+		START_REG(CONFIG_SYS_BOOTCS_START | size));
+	out_be32((u32 *)MPC5XXX_BOOTCS_STOP,
+		STOP_REG(CONFIG_SYS_BOOTCS_START | size, size));
+	out_be32((u32 *)MPC5XXX_CS0_STOP,
+		STOP_REG(CONFIG_SYS_BOOTCS_START | size, size));
+}
+
+struct pci_controller hose;
+
+void pci_init_board(void)
+{
+	mvsmr_get_dbg_present();
+	mvsmr_get_service_mode();
+	mvsmr_init_fpga();
+	mv_load_fpga();
+	pci_mpc5xxx_init(&hose);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	if (!mvsmr_get_mac())
+		return cpu_eth_init(bis);
+
+	return pci_eth_init(bis);
+}
+#include <pci.h>
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+#define FPGA_DIN	MPC5XXX_GPIO_SIMPLE_PSC3_0
+#define FPGA_CCLK	MPC5XXX_GPIO_SIMPLE_PSC3_1
+#define FPGA_DONE	MPC5XXX_GPIO_SIMPLE_PSC3_2
+#define FPGA_CONFIG	MPC5XXX_GPIO_SIMPLE_PSC3_3
+#define FPGA_STATUS	MPC5XXX_GPIO_SINT_PSC3_4
+#define S_FPGA_DIN	MPC5XXX_GPIO_SINT_PSC3_5
+#define S_FPGA_CCLK	MPC5XXX_GPIO_SIMPLE_PSC3_6
+#define S_FPGA_DONE	MPC5XXX_GPIO_SIMPLE_PSC3_7
+#define S_FPGA_CONFIG	MPC5XXX_GPIO_SINT_PSC3_8
+#define S_FPGA_STATUS	MPC5XXX_GPIO_WKUP_PSC3_9
+
+#define MAN_RST		MPC5XXX_GPIO_WKUP_PSC6_0
+#define WD_TS		MPC5XXX_GPIO_WKUP_PSC6_1
+#define WD_WDI		MPC5XXX_GPIO_SIMPLE_PSC6_2
+#define COP_PRESENT	MPC5XXX_GPIO_SIMPLE_PSC6_3
+#define SERVICE_MODE	MPC5XXX_GPIO_WKUP_6
+#define FLASH_RBY	MPC5XXX_GPIO_WKUP_7
+#define UART_EN1	MPC5XXX_GPIO_WKUP_PSC1_4
+#define LAN_PRSNT	MPC5XXX_GPIO_WKUP_PSC2_4
+
+#define SIMPLE_DDR	(FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI |\
+			 S_FPGA_CCLK)
+#define SIMPLE_DVO	(FPGA_CONFIG)
+#define SIMPLE_ODE	(FPGA_CONFIG)
+#define SIMPLE_GPIOEN	(FPGA_DIN | FPGA_CCLK | FPGA_DONE | FPGA_CONFIG |\
+			 S_FPGA_CCLK | S_FPGA_DONE | WD_WDI | COP_PRESENT)
+
+#define SINT_ODE	0x1
+#define SINT_DDR	0x3
+#define SINT_DVO	0x1
+#define SINT_INTEN	0
+#define SINT_ITYPE	0
+#define SINT_GPIOEN	(FPGA_STATUS | S_FPGA_DIN | S_FPGA_CONFIG)
+
+#define WKUP_ODE	(MAN_RST | S_FPGA_STATUS)
+#define WKUP_DIR	(MAN_RST | WD_TS | S_FPGA_STATUS)
+#define WKUP_DO		(MAN_RST | WD_TS | S_FPGA_STATUS)
+#define WKUP_EN		(MAN_RST | WD_TS | S_FPGA_STATUS | SERVICE_MODE |\
+			 FLASH_RBY | UART_EN1 | LAN_PRSNT)
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2010
+ * André Schwarz, Matrix Vision GmbH, as@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within  */
+    /* the first two sectors (=8KB) of our S29GL flash chip */
+    cpu/mpc5xxx/start.o          (.text)
+    cpu/mpc5xxx/traps.o          (.text)
+    lib_generic/crc32.o         (.text)
+    lib_ppc/cache.o             (.text)
+    lib_ppc/time.o              (.text)
+
+    /* This is only needed to force failure if size of above code will ever */
+    /* increase and grow into reserved space. */
+    . = ALIGN(0x2000);	/* location counter has to be 0x4000 now */
+    . += 0x4000;	/* ->0x8000, i.e. move to env_offset */
+
+    . = env_offset;	/* ld error as soon as above ALIGN misplaces lc */
+    common/env_embedded.o        (.ppcenv)
+
+    *(.text)
+    *(.got1)
+    . = ALIGN(16);
+    *(.eh_frame)
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+Matrix Vision mvSMR
+-------------------
+
+1.	Board Description
+
+	The mvSMR is a 75x130mm single image processing board used
+	in automation. Power Supply is 24VDC.
+
+2	System Components
+
+2.1	CPU
+	Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB.
+	64MB DDR-I @ 133MHz.
+	8 MByte Nor Flash on local bus.
+	2 serial ports. Console running on ttyS0 @ 115200 8N1.
+
+2.2	PCI
+	PCI clock fixed at 33MHz due to old'n'slow Xilinx PCI core.
+
+2.3	FPGA
+	Xilinx Spartan-3 XC3S200 with PCI DMA engine.
+	Connects to Matrix Vision specific CCD/CMOS sensor interface.
+
+2.4	I2C
+	EEPROM @ 0xA0 for vendor specifics.
+	image sensor interface (slave adresses depend on sensor)
+
+3	Flash layout.
+
+	reset vector is 0x00000100, i.e. "LOWBOOT".
+
+	FF800000	u-boot
+	FF806000	u-boot script image
+	FF808000	u-boot environment
+	FF840000	FPGA raw bit file
+	FF880000	root FS
+	FFF00000	kernel
+
+4	Booting
+
+	On startup the bootscript @ FF806000 is executed. This script can be
+	exchanged easily. Default boot mode is "boot from flash", i.e. system
+	works stand-alone.
+
+	This behaviour depends on some environment variables :
+
+	"netboot" : yes ->try dhcp/bootp and boot from network.
+	A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
+	DHCP server configuration, e.g. to provide different images to
+	different devices.
+
+	During netboot the system tries to get 3 image files:
+	1. Kernel - name + data is given during BOOTP.
+	2. Initrd - name is stored in "initrd_name"
+	Fallback files are the flash versions.
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2010
+ * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <version.h>
+
+#define CONFIG_MPC5xxx	1
+#define CONFIG_MPC5200 	1
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000
+
+#define BOOTFLAG_COLD		0x01
+#define BOOTFLAG_WARM		0x02
+
+#define CONFIG_MISC_INIT_R	1
+
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CACHELINE_SHIFT	5
+#endif
+
+#define CONFIG_PSC_CONSOLE	1
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200,\
+						230400}
+
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+#undef	CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#define CONFIG_SYS_XLB_PIPELINING	1
+#define CONFIG_HIGH_BATS	1
+
+#define MV_CI			mvSMR
+#define MV_VCI			mvSMR
+#define MV_FPGA_DATA		0xff840000
+#define MV_FPGA_SIZE		0x1ff88
+#define MV_KERNEL_ADDR		0xfff00000
+#define MV_SCRIPT_ADDR		0xff806000
+#define MV_INITRD_ADDR		0xff880000
+#define MV_INITRD_LENGTH	0x00240000
+#define MV_SCRATCH_ADDR		0xffcc0000
+#define MV_SCRATCH_LENGTH	MV_INITRD_LENGTH
+
+#define CONFIG_SHOW_BOOT_PROGRESS 1
+
+#define MV_KERNEL_ADDR_RAM	0x00100000
+#define MV_INITRD_ADDR_RAM	0x00400000
+
+/*
+ * Supported commands
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SDRAM
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_NTPSERVER
+#define CONFIG_BOOTP_RANDOM_DELAY
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_VENDOREX
+
+/*
+ * Autoboot
+ */
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_STOP_STR 	"abcdefg"
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_BOOTCOMMAND      "source ${script_addr}"
+#define CONFIG_BOOTARGS		"root=/dev/ram ro rootfstype=squashfs" \
+					" allocate=6M"
+
+#define XMK_STR(x)      #x
+#define MK_STR(x)       XMK_STR(x)
+
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"console_nr=0\0"					\
+	"console=no\0"						\
+	"stdin=serial\0"					\
+	"stdout=serial\0"					\
+	"stderr=serial\0"					\
+	"fpga=0\0"						\
+	"fpgadata=" MK_STR(MV_FPGA_DATA) "\0"			\
+	"fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0"		\
+	"mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0"		\
+	"mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0"	\
+	"script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0"		\
+	"mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0"		\
+	"mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0"	\
+	"mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0"	\
+	"mv_scratch_addr=" MK_STR(MV_SCRATCH_ADDR) "\0"		\
+	"mv_scratch_length=" MK_STR(MV_SCRATCH_LENGTH) "\0"	\
+	"mv_version=" U_BOOT_VERSION "\0"			\
+	"dhcp_client_id=" MK_STR(MV_CI) "\0"			\
+	"dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0"	\
+	"netretry=no\0"						\
+	"use_static_ipaddr=no\0"				\
+	"static_ipaddr=192.168.0.101\0"				\
+	"static_netmask=255.255.255.0\0"			\
+	"static_gateway=0.0.0.0\0"				\
+	"initrd_name=uInitrd.mvsmr-rfs\0"			\
+	"zcip=yes\0"						\
+	"netboot=no\0"						\
+	""
+
+#undef XMK_STR
+#undef MK_STR
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
+
+/*
+ * Flash configuration
+ */
+#undef 	CONFIG_FLASH_16BIT
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	50000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+
+#define CONFIG_SYS_LOWBOOT
+#define CONFIG_SYS_FLASH_BASE		TEXT_BASE
+#define CONFIG_SYS_FLASH_SIZE		0x00800000
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#undef	CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_HAS_UID
+#define	CONFIG_OVERWRITE_ETHADDR_ONCE
+
+#define CONFIG_ENV_OFFSET	0x8000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+
+/* used by linker script to wrap code around */
+#define CONFIG_SCRIPT_OFFSET	0x6000
+#define CONFIG_SCRIPT_SECT_SIZE	0x2000
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
+						CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT		1
+#endif
+
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1
+#define CONFIG_SYS_I2C_MODULE	1
+#define CONFIG_SYS_I2C_SPEED	86000
+#define CONFIG_SYS_I2C_SLAVE	0x7F
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_NET_RETRY_COUNT 5
+
+#define CONFIG_MPC5xxx_FEC
+#define CONFIG_MPC5xxx_FEC_MII100
+#define CONFIG_PHY_ADDR		0x00
+#define CONFIG_NETDEV		eth0
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_PROMPT_HUSH_PS2 	"> "
+#undef 	CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT		"=> "
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE		1024
+#else
+#define CONFIG_SYS_CBSIZE		256
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START	0x00800000
+#define CONFIG_SYS_MEMTEST_END		0x02f00000
+
+#define CONFIG_SYS_HZ			1000
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x02000000
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 		0x00200000
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x00050044
+
+#define CONFIG_SYS_HID0_INIT		(HID0_ICE | HID0_ICFI)
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00047800
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+
+#define CONFIG_SYS_CS_BURST		0x000000f0
+#define CONFIG_SYS_CS_DEADCYCLE		0x33333303
+
+#define CONFIG_SYS_RESET_ADDRESS	0x00000100
+
+#undef FPGA_DEBUG
+#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_FPGA		CONFIG_SYS_XILINX_SPARTAN2
+#define CONFIG_FPGA_XILINX	1
+#define CONFIG_FPGA_SPARTAN2	1
+#define CONFIG_FPGA_COUNT	1
+
+#endif
...	...	@@ -437,7 +437,7 @@
437	437
438	438	N: Andre Schwarz
439	439	E: andre.schwarz@matrix-vision.de
440		-D: Support for Matrix Vision boards (MVBLM7/MVBC_P)
	440	+D: Support for Matrix Vision boards (MVBLM7/MVBC_P/MVSMR)
441	441
442	442	N: Robert Schwebel
443	443	E: r.schwebel@pengutronix.de
...	...	@@ -422,6 +422,7 @@
422	422
423	423	mvbc_p MPC5200
424	424	mvblm7 MPC8343
	425	+ mvsmr MPC5200
425	426
426	427	Jon Smirl <jonsmirl@gmail.com>
427	428
...	...	@@ -70,6 +70,7 @@
70	70	motionpro \
71	71	munices \
72	72	MVBC_P \
	73	+ MVSMR \
73	74	o2dnt \
74	75	pcm030 \
75	76	pf5200 \
...	...	@@ -664,6 +664,11 @@
664	664	{ echo "#define CONFIG_MVBC_P" >>$(obj)include/config.h; }
665	665	@$(MKCONFIG) -n $@ -a MVBC_P ppc mpc5xxx mvbc_p matrix_vision
666	666
	667	+MVSMR_config: unconfig
	668	+ @mkdir -p $(obj)include
	669	+ @mkdir -p $(obj)board/matrix_vision/mvsmr
	670	+ @$(MKCONFIG) $(@:_config=) ppc mpc5xxx mvsmr matrix_vision
	671	+
667	672	o2dnt_config: unconfig
668	673	@$(MKCONFIG) o2dnt ppc mpc5xxx o2dnt
669	674
	1	+#
	2	+# (C) Copyright 2003
	3	+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+#
	5	+# (C) Copyright 2004-2008
	6	+# Matrix-Vision GmbH, info@matrix-vision.de
	7	+#
	8	+# See file CREDITS for list of people who contributed to this
	9	+# project.
	10	+#
	11	+# This program is free software; you can redistribute it and/or
	12	+# modify it under the terms of the GNU General Public License as
	13	+# published by the Free Software Foundation; either version 2 of
	14	+# the License, or (at your option) any later version.
	15	+#
	16	+# This program is distributed in the hope that it will be useful,
	17	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	+# GNU General Public License for more details.
	20	+#
	21	+# You should have received a copy of the GNU General Public License
	22	+# along with this program; if not, write to the Free Software
	23	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	+# MA 02111-1307 USA
	25	+#
	26	+
	27	+include $(TOPDIR)/config.mk
	28	+
	29	+LIB = $(obj)lib$(BOARD).a
	30	+
	31	+COBJS := $(BOARD).o fpga.o
	32	+
	33	+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
	34	+OBJS := $(addprefix $(obj),$(COBJS))
	35	+SOBJS := $(addprefix $(obj),$(SOBJS))
	36	+
	37	+$(LIB): $(obj).depend $(OBJS)
	38	+ $(AR) $(ARFLAGS) $@ $(OBJS)
	39	+ @mkimage -T script -C none -n mvSMR_Script -d bootscript bootscript.img
	40	+
	41	+clean:
	42	+ rm -f $(SOBJS) $(OBJS)
	43	+
	44	+distclean: clean
	45	+ rm -f $(LIB) core *.bak $(obj).depend
	46	+
	47	+#########################################################################
	48	+
	49	+include $(SRCTREE)/rules.mk
	50	+
	51	+sinclude $(obj).depend
	1	+echo
	2	+echo "==== running autoscript ===="
	3	+echo
	4	+setenv boot24 'bootm ${kernel_boot} ${mv_initrd_addr_ram}'
	5	+setenv ramkernel 'setenv kernel_boot ${loadaddr}'
	6	+setenv flashkernel 'setenv kernel_boot ${mv_kernel_addr}'
	7	+setenv cpird 'cp ${mv_initrd_addr} ${mv_initrd_addr_ram} ${mv_initrd_length}'
	8	+setenv bootfromflash run flashkernel cpird addcons boot24
	9	+setenv bootfromnet 'tftp ${mv_initrd_addr_ram} ${initrd_name};run ramkernel'
	10	+if test ${console} = yes;
	11	+then
	12	+setenv addcons 'setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8'
	13	+else
	14	+setenv addcons 'setenv bootargs ${bootargs} console=tty0'
	15	+fi
	16	+setenv set_static_ip 'setenv ipaddr ${static_ipaddr}'
	17	+setenv set_static_nm 'setenv netmask ${static_netmask}'
	18	+setenv set_static_gw 'setenv gatewayip ${static_gateway}'
	19	+setenv set_ip 'setenv ip ${ipaddr}::${gatewayip}:${netmask}'
	20	+if test ${servicemode} != yes;
	21	+then
	22	+ echo "=== forced flash mode ==="
	23	+ run set_static_ip set_static_nm set_static_gw set_ip bootfromflash
	24	+fi
	25	+if test ${autoscript_boot} != no;
	26	+then
	27	+ if test ${netboot} = yes;
	28	+ then
	29	+ bootp
	30	+ if test $? = 0;
	31	+ then
	32	+ echo "=== bootp succeeded -> netboot ==="
	33	+ run set_ip bootfromnet addcons boot24
	34	+ else
	35	+ echo "=== netboot failed ==="
	36	+ fi
	37	+ fi
	38	+ echo "=== bootfromflash ==="
	39	+ run set_static_ip set_static_nm set_static_gw set_ip bootfromflash
	40	+else
	41	+ echo "=== boot stopped with autoscript_boot no ==="
	42	+fi
	1	+/*
	2	+ * (C) Copyright 2002
	3	+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
	4	+ * Keith Outwater, keith_outwater@mvis.com.
	5	+ *
	6	+ * (C) Copyright 2010
	7	+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
	8	+ *
	9	+ * See file CREDITS for list of people who contributed to this
	10	+ * project.
	11	+ *
	12	+ * This program is free software; you can redistribute it and/or
	13	+ * modify it under the terms of the GNU General Public License as
	14	+ * published by the Free Software Foundation; either version 2 of
	15	+ * the License, or (at your option) any later version.
	16	+ *
	17	+ * This program is distributed in the hope that it will be useful,
	18	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	+ * GNU General Public License for more details.
	21	+ *
	22	+ * You should have received a copy of the GNU General Public License
	23	+ * along with this program; if not, write to the Free Software
	24	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	+ * MA 02111-1307 USA
	26	+ *
	27	+ */
	28	+
	29	+#include <common.h>
	30	+#include <spartan3.h>
	31	+#include <command.h>
	32	+#include <asm/io.h>
	33	+#include "fpga.h"
	34	+#include "mvsmr.h"
	35	+
	36	+Xilinx_Spartan3_Slave_Serial_fns fpga_fns = {
	37	+ fpga_pre_config_fn,
	38	+ fpga_pgm_fn,
	39	+ fpga_clk_fn,
	40	+ fpga_init_fn,
	41	+ fpga_done_fn,
	42	+ fpga_wr_fn,
	43	+ 0
	44	+};
	45	+
	46	+Xilinx_desc spartan3 = {
	47	+ Xilinx_Spartan2,
	48	+ slave_serial,
	49	+ XILINX_XC3S200_SIZE,
	50	+ (void *) &fpga_fns,
	51	+ 0,
	52	+};
	53	+
	54	+DECLARE_GLOBAL_DATA_PTR;
	55	+
	56	+int mvsmr_init_fpga(void)
	57	+{
	58	+ fpga_init();
	59	+ fpga_add(fpga_xilinx, &spartan3);
	60	+
	61	+ return 1;
	62	+}
	63	+
	64	+int fpga_init_fn(int cookie)
	65	+{
	66	+ struct mpc5xxx_gpio gpio = (struct mpc5xxx_gpio )MPC5XXX_GPIO;
	67	+
	68	+ if (in_be32(&gpio->simple_ival) & FPGA_CONFIG)
	69	+ return 0;
	70	+
	71	+ return 1;
	72	+}
	73	+
	74	+int fpga_done_fn(int cookie)
	75	+{
	76	+ struct mpc5xxx_gpio gpio = (struct mpc5xxx_gpio )MPC5XXX_GPIO;
	77	+ int result = 0;
	78	+
	79	+ udelay(10);
	80	+ if (in_be32(&gpio->simple_ival) & FPGA_DONE)
	81	+ result = 1;
	82	+
	83	+ return result;
	84	+}
	85	+
	86	+int fpga_pgm_fn(int assert, int flush, int cookie)
	87	+{
	88	+ struct mpc5xxx_gpio gpio = (struct mpc5xxx_gpio )MPC5XXX_GPIO;
	89	+
	90	+ if (!assert)
	91	+ setbits_8(&gpio->sint_dvo, FPGA_STATUS);
	92	+ else
	93	+ clrbits_8(&gpio->sint_dvo, FPGA_STATUS);
	94	+
	95	+ return assert;
	96	+}
	97	+
	98	+int fpga_clk_fn(int assert_clk, int flush, int cookie)
	99	+{
	100	+ struct mpc5xxx_gpio gpio = (struct mpc5xxx_gpio )MPC5XXX_GPIO;
	101	+
	102	+ if (assert_clk)
	103	+ setbits_be32(&gpio->simple_dvo, FPGA_CCLK);
	104	+ else
	105	+ clrbits_be32(&gpio->simple_dvo, FPGA_CCLK);
	106	+
	107	+ return assert_clk;
	108	+}
	109	+
	110	+int fpga_wr_fn(int assert_write, int flush, int cookie)
	111	+{
	112	+ struct mpc5xxx_gpio gpio = (struct mpc5xxx_gpio )MPC5XXX_GPIO;
	113	+
	114	+ if (assert_write)
	115	+ setbits_be32(&gpio->simple_dvo, FPGA_DIN);
	116	+ else
	117	+ clrbits_be32(&gpio->simple_dvo, FPGA_DIN);
	118	+
	119	+ return assert_write;
	120	+}
	121	+
	122	+int fpga_pre_config_fn(int cookie)
	123	+{
	124	+ struct mpc5xxx_gpio gpio = (struct mpc5xxx_gpio )MPC5XXX_GPIO;
	125	+
	126	+ setbits_8(&gpio->sint_dvo, FPGA_STATUS);
	127	+
	128	+ return 0;
	129	+}
	1	+/*
	2	+ * (C) Copyright 2008
	3	+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ *
	23	+ */
	24	+
	25	+extern int mvsmr_init_fpga(void);
	26	+
	27	+extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
	28	+extern int fpga_init_fn(int cookie);
	29	+extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
	30	+extern int fpga_wr_fn(int assert_write, int flush, int cookie);
	31	+extern int fpga_done_fn(int cookie);
	32	+extern int fpga_pre_config_fn(int cookie);
	1	+/*
	2	+ * (C) Copyright 2003
	3	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+ *
	5	+ * (C) Copyright 2004
	6	+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
	7	+ *
	8	+ * (C) Copyright 2005-2010
	9	+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
	10	+ *
	11	+ * See file CREDITS for list of people who contributed to this
	12	+ * project.
	13	+ *
	14	+ * This program is free software; you can redistribute it and/or
	15	+ * modify it under the terms of the GNU General Public License as
	16	+ * published by the Free Software Foundation; either version 2 of
	17	+ * the License, or (at your option) any later version.
	18	+ *
	19	+ * This program is distributed in the hope that it will be useful,
	20	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	+ * GNU General Public License for more details.
	23	+ *
	24	+ * You should have received a copy of the GNU General Public License
	25	+ * along with this program; if not, write to the Free Software
	26	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	+ * MA 02111-1307 USA
	28	+ */
	29	+
	30	+#include <common.h>
	31	+#include <mpc5xxx.h>
	32	+#include <malloc.h>
	33	+#include <pci.h>
	34	+#include <i2c.h>
	35	+#include <fpga.h>
	36	+#include <environment.h>
	37	+#include <netdev.h>
	38	+#include <asm/io.h>
	39	+#include "fpga.h"
	40	+#include "mvsmr.h"
	41	+#include "../common/mv_common.h"
	42	+
	43	+#define SDRAM_DDR 1
	44	+#define SDRAM_MODE 0x018D0000
	45	+#define SDRAM_EMODE 0x40090000
	46	+#define SDRAM_CONTROL 0x715f0f00
	47	+#define SDRAM_CONFIG1 0xd3722930
	48	+#define SDRAM_CONFIG2 0x46770000
	49	+
	50	+DECLARE_GLOBAL_DATA_PTR;
	51	+
	52	+static void sdram_start(int hi_addr)
	53	+{
	54	+ long hi_bit = hi_addr ? 0x01000000 : 0;
	55	+
	56	+ /* unlock mode register */
	57	+ out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL \| 0x80000000 \|
	58	+ hi_bit);
	59	+
	60	+ /* precharge all banks */
	61	+ out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL \| 0x80000002 \|
	62	+ hi_bit);
	63	+
	64	+ /* set mode register: extended mode */
	65	+ out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
	66	+
	67	+ /* set mode register: reset DLL */
	68	+ out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE \| 0x04000000);
	69	+
	70	+ /* precharge all banks */
	71	+ out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL \| 0x80000002 \|
	72	+ hi_bit);
	73	+
	74	+ /* auto refresh */
	75	+ out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL \| 0x80000004 \|
	76	+ hi_bit);
	77	+
	78	+ /* set mode register */
	79	+ out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
	80	+
	81	+ /* normal operation */
	82	+ out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL \| hi_bit);
	83	+}
	84	+
	85	+phys_addr_t initdram(int board_type)
	86	+{
	87	+ ulong dramsize = 0;
	88	+ ulong test1,
	89	+ test2;
	90	+
	91	+ /* setup SDRAM chip selects */
	92	+ out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
	93	+
	94	+ /* setup config registers */
	95	+ out_be32((u32 *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
	96	+ out_be32((u32 *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
	97	+
	98	+ /* find RAM size using SDRAM CS0 only */
	99	+ sdram_start(0);
	100	+ test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
	101	+ sdram_start(1);
	102	+ test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
	103	+ if (test1 > test2) {
	104	+ sdram_start(0);
	105	+ dramsize = test1;
	106	+ } else
	107	+ dramsize = test2;
	108	+
	109	+ if (dramsize < (1 << 20))
	110	+ dramsize = 0;
	111	+
	112	+ if (dramsize > 0)
	113	+ out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x13 +
	114	+ __builtin_ffs(dramsize >> 20) - 1);
	115	+ else
	116	+ out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0);
	117	+
	118	+ return dramsize;
	119	+}
	120	+
	121	+void mvsmr_init_gpio(void)
	122	+{
	123	+ struct mpc5xxx_gpio gpio = (struct mpc5xxx_gpio )MPC5XXX_GPIO;
	124	+ struct mpc5xxx_wu_gpio *wu_gpio =
	125	+ (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
	126	+ struct mpc5xxx_gpt_0_7 timers = (struct mpc5xxx_gpt_0_7 )MPC5XXX_GPT;
	127	+
	128	+ printf("Ports : 0x%08x\n", gpio->port_config);
	129	+ printf("PORCFG: 0x%08x\n", in_be32((unsigned *)MPC5XXX_CDM_PORCFG));
	130	+
	131	+ out_be32(&gpio->simple_ddr, SIMPLE_DDR);
	132	+ out_be32(&gpio->simple_dvo, SIMPLE_DVO);
	133	+ out_be32(&gpio->simple_ode, SIMPLE_ODE);
	134	+ out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
	135	+
	136	+ out_8(&gpio->sint_ode, SINT_ODE);
	137	+ out_8(&gpio->sint_ddr, SINT_DDR);
	138	+ out_8(&gpio->sint_dvo, SINT_DVO);
	139	+ out_8(&gpio->sint_inten, SINT_INTEN);
	140	+ out_be16(&gpio->sint_itype, SINT_ITYPE);
	141	+ out_8(&gpio->sint_gpioe, SINT_GPIOEN);
	142	+
	143	+ out_8(&wu_gpio->ode, WKUP_ODE);
	144	+ out_8(&wu_gpio->ddr, WKUP_DIR);
	145	+ out_8(&wu_gpio->dvo, WKUP_DO);
	146	+ out_8(&wu_gpio->enable, WKUP_EN);
	147	+
	148	+ out_be32(&timers->gpt0.emsr, 0x00000234); /* OD output high */
	149	+ out_be32(&timers->gpt1.emsr, 0x00000234);
	150	+ out_be32(&timers->gpt2.emsr, 0x00000234);
	151	+ out_be32(&timers->gpt3.emsr, 0x00000234);
	152	+ out_be32(&timers->gpt4.emsr, 0x00000234);
	153	+ out_be32(&timers->gpt5.emsr, 0x00000234);
	154	+ out_be32(&timers->gpt6.emsr, 0x00000024); /* push-pull output low */
	155	+ out_be32(&timers->gpt7.emsr, 0x00000024);
	156	+}
	157	+
	158	+int misc_init_r(void)
	159	+{
	160	+ char *s = getenv("reset_env");
	161	+
	162	+ if (s) {
	163	+ printf(" === FACTORY RESET ===\n");
	164	+ mv_reset_environment();
	165	+ saveenv();
	166	+ }
	167	+
	168	+ return -1;
	169	+}
	170	+
	171	+void mvsmr_get_dbg_present(void)
	172	+{
	173	+ struct mpc5xxx_gpio gpio = (struct mpc5xxx_gpio )MPC5XXX_GPIO;
	174	+ struct mpc5xxx_psc psc = (struct mpc5xxx_psc )MPC5XXX_PSC1;
	175	+
	176	+ if (in_be32(&gpio->simple_ival) & COP_PRESENT) {
	177	+ setenv("dbg_present", "no\0");
	178	+ setenv("bootstopkey", "abcdefghijklmnopqrstuvwxyz\0");
	179	+ } else {
	180	+ setenv("dbg_present", "yes\0");
	181	+ setenv("bootstopkey", "s\0");
	182	+ setbits_8(&psc->command, PSC_RX_ENABLE);
	183	+ }
	184	+}
	185	+
	186	+void mvsmr_get_service_mode(void)
	187	+{
	188	+ struct mpc5xxx_wu_gpio *wu_gpio =
	189	+ (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
	190	+
	191	+ if (in_8(&wu_gpio->ival) & SERVICE_MODE)
	192	+ setenv("servicemode", "no\0");
	193	+ else
	194	+ setenv("servicemode", "yes\0");
	195	+}
	196	+
	197	+int mvsmr_get_mac(void)
	198	+{
	199	+ unsigned char mac[6];
	200	+ struct mpc5xxx_wu_gpio *wu_gpio =
	201	+ (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
	202	+
	203	+ if (in_8(&wu_gpio->ival) & LAN_PRSNT) {
	204	+ setenv("lan_present", "no\0");
	205	+ return -1;
	206	+ } else
	207	+ setenv("lan_present", "yes\0");
	208	+
	209	+ i2c_read(0x50, 0, 1, mac, 6);
	210	+
	211	+ eth_setenv_enetaddr("ethaddr", mac);
	212	+
	213	+ return 0;
	214	+}
	215	+
	216	+int checkboard(void)
	217	+{
	218	+ mvsmr_init_gpio();
	219	+ printf("Board: Matrix Vision mvSMR\n");
	220	+
	221	+ return 0;
	222	+}
	223	+
	224	+void flash_preinit(void)
	225	+{
	226	+ /*
	227	+ * Now, when we are in RAM, enable flash write
	228	+ * access for detection process.
	229	+ * Note that CS_BOOT cannot be cleared when
	230	+ * executing in flash.
	231	+ */
	232	+ clrbits_be32((u32 *)MPC5XXX_BOOTCS_CFG, 0x1);
	233	+}
	234	+
	235	+void flash_afterinit(ulong size)
	236	+{
	237	+ out_be32((u32 *)MPC5XXX_BOOTCS_START,
	238	+ START_REG(CONFIG_SYS_BOOTCS_START \| size));
	239	+ out_be32((u32 *)MPC5XXX_CS0_START,
	240	+ START_REG(CONFIG_SYS_BOOTCS_START \| size));
	241	+ out_be32((u32 *)MPC5XXX_BOOTCS_STOP,
	242	+ STOP_REG(CONFIG_SYS_BOOTCS_START \| size, size));
	243	+ out_be32((u32 *)MPC5XXX_CS0_STOP,
	244	+ STOP_REG(CONFIG_SYS_BOOTCS_START \| size, size));
	245	+}
	246	+
	247	+struct pci_controller hose;
	248	+
	249	+void pci_init_board(void)
	250	+{
	251	+ mvsmr_get_dbg_present();
	252	+ mvsmr_get_service_mode();
	253	+ mvsmr_init_fpga();
	254	+ mv_load_fpga();
	255	+ pci_mpc5xxx_init(&hose);
	256	+}
	257	+
	258	+int board_eth_init(bd_t *bis)
	259	+{
	260	+ if (!mvsmr_get_mac())
	261	+ return cpu_eth_init(bis);
	262	+
	263	+ return pci_eth_init(bis);
	264	+}
	1	+#include <pci.h>
	2	+
	3	+extern void pci_mpc5xxx_init(struct pci_controller *);
	4	+
	5	+#define FPGA_DIN MPC5XXX_GPIO_SIMPLE_PSC3_0
	6	+#define FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_1
	7	+#define FPGA_DONE MPC5XXX_GPIO_SIMPLE_PSC3_2
	8	+#define FPGA_CONFIG MPC5XXX_GPIO_SIMPLE_PSC3_3
	9	+#define FPGA_STATUS MPC5XXX_GPIO_SINT_PSC3_4
	10	+#define S_FPGA_DIN MPC5XXX_GPIO_SINT_PSC3_5
	11	+#define S_FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_6
	12	+#define S_FPGA_DONE MPC5XXX_GPIO_SIMPLE_PSC3_7
	13	+#define S_FPGA_CONFIG MPC5XXX_GPIO_SINT_PSC3_8
	14	+#define S_FPGA_STATUS MPC5XXX_GPIO_WKUP_PSC3_9
	15	+
	16	+#define MAN_RST MPC5XXX_GPIO_WKUP_PSC6_0
	17	+#define WD_TS MPC5XXX_GPIO_WKUP_PSC6_1
	18	+#define WD_WDI MPC5XXX_GPIO_SIMPLE_PSC6_2
	19	+#define COP_PRESENT MPC5XXX_GPIO_SIMPLE_PSC6_3
	20	+#define SERVICE_MODE MPC5XXX_GPIO_WKUP_6
	21	+#define FLASH_RBY MPC5XXX_GPIO_WKUP_7
	22	+#define UART_EN1 MPC5XXX_GPIO_WKUP_PSC1_4
	23	+#define LAN_PRSNT MPC5XXX_GPIO_WKUP_PSC2_4
	24	+
	25	+#define SIMPLE_DDR (FPGA_DIN \| FPGA_CCLK \| FPGA_CONFIG \| WD_WDI \|\
	26	+ S_FPGA_CCLK)
	27	+#define SIMPLE_DVO (FPGA_CONFIG)
	28	+#define SIMPLE_ODE (FPGA_CONFIG)
	29	+#define SIMPLE_GPIOEN (FPGA_DIN \| FPGA_CCLK \| FPGA_DONE \| FPGA_CONFIG \|\
	30	+ S_FPGA_CCLK \| S_FPGA_DONE \| WD_WDI \| COP_PRESENT)
	31	+
	32	+#define SINT_ODE 0x1
	33	+#define SINT_DDR 0x3
	34	+#define SINT_DVO 0x1
	35	+#define SINT_INTEN 0
	36	+#define SINT_ITYPE 0
	37	+#define SINT_GPIOEN (FPGA_STATUS \| S_FPGA_DIN \| S_FPGA_CONFIG)
	38	+
	39	+#define WKUP_ODE (MAN_RST \| S_FPGA_STATUS)
	40	+#define WKUP_DIR (MAN_RST \| WD_TS \| S_FPGA_STATUS)
	41	+#define WKUP_DO (MAN_RST \| WD_TS \| S_FPGA_STATUS)
	42	+#define WKUP_EN (MAN_RST \| WD_TS \| S_FPGA_STATUS \| SERVICE_MODE \|\
	43	+ FLASH_RBY \| UART_EN1 \| LAN_PRSNT)