Eric Lee / smarc-uboot

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Commit 1f2779187832deea28480c20c16ac687fdaf6ce4

Authored by Michael Brooks
Committed by Ji Luo
1 parent be25ff5c10
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 4 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

MA-14519 Phanbell: Explicitly set buck voltages in SPL 

* Bucks 1-4 will be reconfigured via DVS in the kernel.
* Buck 5 is explicitly set to 1.0V
* Regulator lock/unlock is added, this ensures that in warm or cold
reset the values will be set.

Change-Id: I8d8be74bddbbd081030fe1762b9f9c6534c7fb77

Showing 1 changed file with 19 additions and 10 deletions Inline Diff

board/freescale/imx8mq_aiy/spl.c
Diff comments   View file @ 1f27791
1 /* 1 /*
2 * Copyright 2017 NXP 2 * Copyright 2019 NXP
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <spl.h> 8 #include <spl.h>
9 #include <asm/io.h> 9 #include <asm/io.h>
10 #include <errno.h> 10 #include <errno.h>
11 #include <asm/io.h> 11 #include <asm/io.h>
12 #include <asm/mach-imx/iomux-v3.h> 12 #include <asm/mach-imx/iomux-v3.h>
13 #include <asm/arch/ddr.h> 13 #include <asm/arch/ddr.h>
14 #include <asm/arch/imx8mq_pins.h> 14 #include <asm/arch/imx8mq_pins.h>
15 #include <asm/arch/sys_proto.h> 15 #include <asm/arch/sys_proto.h>
16 #include <power/pmic.h> 16 #include <power/pmic.h>
17 #include <power/bd71837.h> 17 #include <power/bd71837.h>
18 #include <asm/arch/clock.h> 18 #include <asm/arch/clock.h>
19 #include <asm/mach-imx/gpio.h> 19 #include <asm/mach-imx/gpio.h>
20 #include <asm/mach-imx/mxc_i2c.h> 20 #include <asm/mach-imx/mxc_i2c.h>
21 #include <fsl_esdhc.h> 21 #include <fsl_esdhc.h>
22 #include <mmc.h> 22 #include <mmc.h>
23 #include <asm/arch/imx8m_ddr.h> 23 #include <asm/arch/imx8m_ddr.h>
24 24
25 DECLARE_GLOBAL_DATA_PTR; 25 DECLARE_GLOBAL_DATA_PTR;
26 26
27 extern struct dram_timing_info dram_timing_micron_3g; 27 extern struct dram_timing_info dram_timing_micron_3g;
28 extern struct dram_timing_info dram_timing_1g; 28 extern struct dram_timing_info dram_timing_1g;
29 extern int get_imx8m_baseboard_id(void); 29 extern int get_imx8m_baseboard_id(void);
30 30
31 void spl_dram_init(void) 31 void spl_dram_init(void)
32 { 32 {
33 int board_id = get_imx8m_baseboard_id(); 33 int board_id = get_imx8m_baseboard_id();
34 34
35 /* ddr init */ 35 /* ddr init */
36 if ((board_id == AIY_MICRON_1G) || (board_id == AIY_HYNIX_1G)) 36 if ((board_id == AIY_MICRON_1G) || (board_id == AIY_HYNIX_1G))
37 ddr_init(&dram_timing_1g); 37 ddr_init(&dram_timing_1g);
38 else 38 else
39 ddr_init(&dram_timing_micron_3g); 39 ddr_init(&dram_timing_micron_3g);
40 40
41 } 41 }
42 42
43 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) 43 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
44 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 44 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
45 struct i2c_pads_info i2c_pad_info1 = { 45 struct i2c_pads_info i2c_pad_info1 = {
46 .scl = { 46 .scl = {
47 .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC, 47 .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
48 .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC, 48 .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
49 .gp = IMX_GPIO_NR(5, 14), 49 .gp = IMX_GPIO_NR(5, 14),
50 }, 50 },
51 .sda = { 51 .sda = {
52 .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC, 52 .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
53 .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC, 53 .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
54 .gp = IMX_GPIO_NR(5, 15), 54 .gp = IMX_GPIO_NR(5, 15),
55 }, 55 },
56 }; 56 };
57 57
58 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) 58 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
59 #define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) 59 #define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
60 #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) 60 #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
61 61
62 int board_mmc_getcd(struct mmc *mmc) 62 int board_mmc_getcd(struct mmc *mmc)
63 { 63 {
64 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 64 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
65 int ret = 0; 65 int ret = 0;
66 66
67 switch (cfg->esdhc_base) { 67 switch (cfg->esdhc_base) {
68 case USDHC1_BASE_ADDR: 68 case USDHC1_BASE_ADDR:
69 ret = 1; 69 ret = 1;
70 break; 70 break;
71 case USDHC2_BASE_ADDR: 71 case USDHC2_BASE_ADDR:
72 ret = !gpio_get_value(USDHC2_CD_GPIO); 72 ret = !gpio_get_value(USDHC2_CD_GPIO);
73 return ret; 73 return ret;
74 } 74 }
75 75
76 return 1; 76 return 1;
77 } 77 }
78 78
79 #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ 79 #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
80 PAD_CTL_FSEL2) 80 PAD_CTL_FSEL2)
81 #define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) 81 #define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
82 82
83 static iomux_v3_cfg_t const usdhc1_pads[] = { 83 static iomux_v3_cfg_t const usdhc1_pads[] = {
84 IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 84 IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
85 IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 85 IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
86 IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 86 IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
87 IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 87 IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
88 IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 88 IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
89 IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 89 IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
90 IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 90 IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
91 IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 91 IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
92 IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 92 IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
93 IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 93 IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
94 IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), 94 IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
95 }; 95 };
96 96
97 static iomux_v3_cfg_t const usdhc2_pads[] = { 97 static iomux_v3_cfg_t const usdhc2_pads[] = {
98 IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ 98 IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
99 IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ 99 IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
100 IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ 100 IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
101 IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ 101 IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
102 IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ 102 IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
103 IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ 103 IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
104 IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), 104 IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
105 IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), 105 IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
106 }; 106 };
107 107
108 static struct fsl_esdhc_cfg usdhc_cfg[2] = { 108 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
109 {USDHC1_BASE_ADDR, 0, 8}, 109 {USDHC1_BASE_ADDR, 0, 8},
110 {USDHC2_BASE_ADDR, 0, 4}, 110 {USDHC2_BASE_ADDR, 0, 4},
111 }; 111 };
112 112
113 int board_mmc_init(bd_t *bis) 113 int board_mmc_init(bd_t *bis)
114 { 114 {
115 int i, ret; 115 int i, ret;
116 /* 116 /*
117 * According to the board_mmc_init() the following map is done: 117 * According to the board_mmc_init() the following map is done:
118 * (U-Boot device node) (Physical Port) 118 * (U-Boot device node) (Physical Port)
119 * mmc0 USDHC1 119 * mmc0 USDHC1
120 * mmc1 USDHC2 120 * mmc1 USDHC2
121 */ 121 */
122 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 122 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
123 switch (i) { 123 switch (i) {
124 case 0: 124 case 0:
125 usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); 125 usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
126 imx_iomux_v3_setup_multiple_pads( 126 imx_iomux_v3_setup_multiple_pads(
127 usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 127 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
128 gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); 128 gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
129 gpio_direction_output(USDHC1_PWR_GPIO, 0); 129 gpio_direction_output(USDHC1_PWR_GPIO, 0);
130 udelay(500); 130 udelay(500);
131 gpio_direction_output(USDHC1_PWR_GPIO, 1); 131 gpio_direction_output(USDHC1_PWR_GPIO, 1);
132 break; 132 break;
133 case 1: 133 case 1:
134 usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); 134 usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
135 imx_iomux_v3_setup_multiple_pads( 135 imx_iomux_v3_setup_multiple_pads(
136 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 136 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
137 gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); 137 gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
138 gpio_direction_output(USDHC2_PWR_GPIO, 0); 138 gpio_direction_output(USDHC2_PWR_GPIO, 0);
139 udelay(500); 139 udelay(500);
140 gpio_direction_output(USDHC2_PWR_GPIO, 1); 140 gpio_direction_output(USDHC2_PWR_GPIO, 1);
141 break; 141 break;
142 default: 142 default:
143 printf("Warning: you configured more USDHC controllers" 143 printf("Warning: you configured more USDHC controllers"
144 "(%d) than supported by the board\n", i + 1); 144 "(%d) than supported by the board\n", i + 1);
145 return -EINVAL; 145 return -EINVAL;
146 } 146 }
147 147
148 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 148 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
149 if (ret) 149 if (ret)
150 return ret; 150 return ret;
151 } 151 }
152 152
153 return 0; 153 return 0;
154 } 154 }
155 155
156 #ifdef CONFIG_POWER 156 #ifdef CONFIG_POWER
157 #define I2C_PMIC 0 157 #define I2C_PMIC 0
158 int power_init_board(void) 158 int power_init_board(void)
159 { 159 {
160 struct pmic *p; 160 struct pmic *p;
161 int ret; 161 int ret;
162 162
163 ret = power_bd71837_init(I2C_PMIC); 163 ret = power_bd71837_init(I2C_PMIC);
164 if (ret) 164 if (ret)
165 printf("power init failed"); 165 printf("power init failed");
166 166
167 p = pmic_get("BD71837"); 167 p = pmic_get("BD71837");
168 pmic_probe(p); 168 pmic_probe(p);
169 169
170 /* unlock the PMIC regs */ 170 /* Unlock reg */
171 pmic_reg_write(p, BD71837_REGLOCK, 0x1); 171 pmic_reg_write(p, BD71837_REGLOCK, 0x1);
172 172
173 /* Set BUCK2 output for ARM to 0.85v */ 173 /* Set BUCK5 output for DRAM to 1.0V */
174 pmic_reg_write(p, BD71837_BUCK2_VOLT_RUN, 0x0f); 174 /* 0.70,0.80,0.90,1.00, 1.05,1.10,1.20,1.35 */
175 pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x3);
175 176
176 /* Set BUCK5 output for DRAM to 0.9V */ 177 /* Set BUCK3 output for VDD_GPU_0V9 to 0.90V */
177 pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x2); 178 /* 0.7-1.3 (10mVstep) */
179 pmic_reg_write(p, BD71837_BUCK3_VOLT_RUN, 0x14);
178 180
179 /* Set BUCK6 output for VDD_3V3 to 3.1V */ 181 /* Set BUCK4 output for VDD_VPU_0V9 to 0.90V */
180 pmic_reg_write(p, BD71837_BUCK6_VOLT, 0x1); 182 /* 0.7-1.3 (10mVstep) */
183 pmic_reg_write(p, BD71837_BUCK4_VOLT_RUN, 0x14);
181 184
182 /* Set BUCK7 output for VDD_1V8 to 1.695V */ 185 /* Set BUCK2 output for VDD_ARM_0V9 to 0.90V */
183 pmic_reg_write(p, BD71837_BUCK7_VOLT, 0x1); 186 /* 0.7-1.3 (10mVstep) */
187 pmic_reg_write(p, BD71837_BUCK2_VOLT_RUN, 0x14);
184 188
189 /* Set BUCK1 output for VDD_SOC_0V9 to 0.90V */
190 /* 0.7-1.3 (10mVstep) */
191 pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x14);
192
185 /* lock the PMIC regs */ 193 /* lock the PMIC regs */
186 pmic_reg_write(p, BD71837_REGLOCK, 0x11); 194 pmic_reg_write(p, BD71837_REGLOCK, 0x11);
195
187 return 0; 196 return 0;
188 } 197 }
189 #endif 198 #endif
190 199
191 void spl_board_init(void) 200 void spl_board_init(void)
192 { 201 {
193 #ifndef CONFIG_SPL_USB_SDP_SUPPORT 202 #ifndef CONFIG_SPL_USB_SDP_SUPPORT
194 /* Serial download mode */ 203 /* Serial download mode */
195 if (is_usb_boot()) { 204 if (is_usb_boot()) {
196 puts("Back to ROM, SDP\n"); 205 puts("Back to ROM, SDP\n");
197 restore_boot_params(); 206 restore_boot_params();
198 } 207 }
199 #endif 208 #endif
200 init_usb_clk(); 209 init_usb_clk();
201 210
202 puts("Normal Boot\n"); 211 puts("Normal Boot\n");
203 } 212 }
204 213
205 #ifdef CONFIG_SPL_LOAD_FIT 214 #ifdef CONFIG_SPL_LOAD_FIT
206 int board_fit_config_name_match(const char *name) 215 int board_fit_config_name_match(const char *name)
207 { 216 {
208 /* Just empty function now - can't decide what to choose */ 217 /* Just empty function now - can't decide what to choose */
209 debug("%s: %s\n", __func__, name); 218 debug("%s: %s\n", __func__, name);
210 219
211 return 0; 220 return 0;
212 } 221 }
213 #endif 222 #endif
214 223
215 void board_init_f(ulong dummy) 224 void board_init_f(ulong dummy)
216 { 225 {
217 int ret; 226 int ret;
218 227
219 /* Clear global data */ 228 /* Clear global data */
220 memset((void *)gd, 0, sizeof(gd_t)); 229 memset((void *)gd, 0, sizeof(gd_t));
221 230
222 arch_cpu_init(); 231 arch_cpu_init();
223 232
224 init_uart_clk(0); /* Init UART0 clock */ 233 init_uart_clk(0); /* Init UART0 clock */
225 234
226 board_early_init_f(); 235 board_early_init_f();
227 236
228 timer_init(); 237 timer_init();
229 238
230 preloader_console_init(); 239 preloader_console_init();
231 240
232 /* Clear the BSS. */ 241 /* Clear the BSS. */
233 memset(__bss_start, 0, __bss_end - __bss_start); 242 memset(__bss_start, 0, __bss_end - __bss_start);
234 243
235 ret = spl_init(); 244 ret = spl_init();
236 if (ret) { 245 if (ret) {
237 debug("spl_init() failed: %d\n", ret); 246 debug("spl_init() failed: %d\n", ret);
238 hang(); 247 hang();
239 } 248 }
240 249
241 enable_tzc380(); 250 enable_tzc380();
242 251
243 /* Adjust pmic voltage to 1.0V for 800M */ 252 /* Adjust pmic voltage to 1.0V for 800M */
244 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 253 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
245 254
246 power_init_board(); 255 power_init_board();
247 256
248 /* DDR initialization */ 257 /* DDR initialization */
249 spl_dram_init(); 258 spl_dram_init();
250 259
251 board_init_r(NULL, 0); 260 board_init_r(NULL, 0);
252 } 261 }
253 262