Commit 1f4134c85f6416cbdadaf5f4ff6321f6c685c74c
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smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga
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MLK-18703: crypto: caam: Add init TRNG into SPL or U-Boot
The following reasons lead to instantiate the TRNG into U-Boot/SPL: - On some i.MX platforms Linux Kernel could not instantiate RNG - RNG could be used/needed by M4/M0 cores before Kernel stage - Having the RNG instantiation implemented only once for almost i.MX platforms Signed-off-by: Aymen Sghaier <aymen.sghaier@nxp.com>
Showing 3 changed files with 769 additions and 619 deletions Side-by-side Diff
drivers/crypto/fsl_caam.c
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1 | 1 | /* |
2 | 2 | * Copyright (c) 2012-2016, Freescale Semiconductor, Inc. |
3 | 3 | * All rights reserved. |
4 | + * Copyright 2018 NXP | |
4 | 5 | * |
5 | 6 | * Redistribution and use in source and binary forms, with or without modification, |
6 | 7 | * are permitted provided that the following conditions are met: |
7 | 8 | |
8 | 9 | |
9 | 10 | |
10 | 11 | |
11 | 12 | |
12 | 13 | |
13 | 14 | |
14 | 15 | |
15 | 16 | |
16 | 17 | |
17 | 18 | |
18 | 19 | |
19 | 20 | |
... | ... | @@ -29,81 +30,89 @@ |
29 | 30 | */ |
30 | 31 | |
31 | 32 | #include <common.h> |
33 | +#include <malloc.h> | |
34 | +#include <memalign.h> | |
32 | 35 | #include <asm/io.h> |
33 | 36 | #include <asm/arch/crm_regs.h> |
34 | 37 | #include "fsl_caam_internal.h" |
38 | +#include "fsl/desc_constr.h" | |
35 | 39 | #include <fsl_caam.h> |
36 | 40 | |
37 | -/*---------- Global variables ----------*/ | |
38 | -/* Input job ring - single entry input ring */ | |
39 | -uint32_t g_input_ring[JOB_RING_ENTRIES] = {0}; | |
41 | +DECLARE_GLOBAL_DATA_PTR; | |
40 | 42 | |
43 | +static void rng_init(void); | |
44 | +static void caam_clock_enable(void); | |
45 | +static int do_cfg_jrqueue(void); | |
46 | +static int do_job(u32 *desc); | |
47 | +static int jr_reset(void); | |
41 | 48 | |
42 | -/* Output job ring - single entry output ring (consists of two words) */ | |
43 | -uint32_t g_output_ring[2*JOB_RING_ENTRIES] = {0, 0}; | |
44 | - | |
45 | -uint32_t decap_dsc[] = | |
46 | -{ | |
47 | - DECAP_BLOB_DESC1, | |
48 | - DECAP_BLOB_DESC2, | |
49 | - DECAP_BLOB_DESC3, | |
50 | - DECAP_BLOB_DESC4, | |
51 | - DECAP_BLOB_DESC5, | |
52 | - DECAP_BLOB_DESC6, | |
53 | - DECAP_BLOB_DESC7, | |
54 | - DECAP_BLOB_DESC8, | |
55 | - DECAP_BLOB_DESC9 | |
49 | +/* | |
50 | + * Structures | |
51 | + */ | |
52 | +/* Definition of input ring object */ | |
53 | +struct inring_entry { | |
54 | + u32 desc; /* Pointer to input descriptor */ | |
56 | 55 | }; |
57 | 56 | |
58 | -uint32_t encap_dsc[] = | |
59 | -{ | |
60 | - ENCAP_BLOB_DESC1, | |
61 | - ENCAP_BLOB_DESC2, | |
62 | - ENCAP_BLOB_DESC3, | |
63 | - ENCAP_BLOB_DESC4, | |
64 | - ENCAP_BLOB_DESC5, | |
65 | - ENCAP_BLOB_DESC6, | |
66 | - ENCAP_BLOB_DESC7, | |
67 | - ENCAP_BLOB_DESC8, | |
68 | - ENCAP_BLOB_DESC9 | |
57 | +/* Definition of output ring object */ | |
58 | +struct outring_entry { | |
59 | + u32 desc; /* Pointer to output descriptor */ | |
60 | + u32 status; /* Status of the Job Ring */ | |
69 | 61 | }; |
70 | 62 | |
71 | -uint32_t hwrng_dsc[6] = {0}; | |
72 | -uint32_t rng_inst_dsc[] = | |
73 | -{ | |
74 | - RNG_INST_DESC1, | |
75 | - RNG_INST_DESC2, | |
76 | - RNG_INST_DESC3, | |
77 | - RNG_INST_DESC4, | |
78 | - RNG_INST_DESC5, | |
79 | - RNG_INST_DESC6, | |
80 | - RNG_INST_DESC7, | |
81 | - RNG_INST_DESC8, | |
82 | - RNG_INST_DESC9 | |
63 | +/* Main job ring data structure */ | |
64 | +struct jr_data_st { | |
65 | + struct inring_entry *inrings; | |
66 | + struct outring_entry *outrings; | |
67 | + u32 status; /* Ring buffers init status */ | |
68 | + u32 *desc; /* Pointer to output descriptor */ | |
69 | + u32 raw_addr[DESC_MAX_SIZE * 2]; | |
83 | 70 | }; |
84 | 71 | |
85 | -static uint8_t skeymod[] = { | |
72 | +/* | |
73 | + * Global variables | |
74 | + */ | |
75 | +static struct jr_data_st g_jrdata = {0}; | |
76 | + | |
77 | +static u8 skeymod[] = { | |
86 | 78 | 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, |
87 | 79 | 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00 |
88 | 80 | }; |
89 | 81 | |
82 | +/* | |
83 | + * Local functions | |
84 | + */ | |
85 | +static void dump_error(void) | |
86 | +{ | |
87 | + int i; | |
90 | 88 | |
91 | -/* arm v7 need 64 align */ | |
92 | -#define ALIGN_MASK 0xffffffc0 | |
89 | + debug("Dump CAAM Error\n"); | |
90 | + debug("MCFGR 0x%08X\n", __raw_readl(CAAM_MCFGR)); | |
91 | + debug("FAR 0x%08X\n", __raw_readl(CAAM_FAR)); | |
92 | + debug("FAMR 0x%08X\n", __raw_readl(CAAM_FAMR)); | |
93 | + debug("FADR 0x%08X\n", __raw_readl(CAAM_FADR)); | |
94 | + debug("CSTA 0x%08X\n", __raw_readl(CAAM_STA)); | |
95 | + debug("RTMCTL 0x%X\n", __raw_readl(CAAM_RTMCTL)); | |
96 | + debug("RTSTATUS 0x%X\n", __raw_readl(CAAM_RTSTATUS)); | |
97 | + debug("RDSTA 0x%X\n", __raw_readl(CAAM_RDSTA)); | |
93 | 98 | |
99 | + for (i = 0; i < desc_len(g_jrdata.desc); i++) | |
100 | + debug("desc[%d]: 0x%08x\n", i, g_jrdata.desc[i]); | |
101 | +} | |
102 | + | |
94 | 103 | /*! |
95 | 104 | * Secure memory run command. |
96 | 105 | * |
97 | 106 | * @param sec_mem_cmd Secure memory command register |
98 | 107 | * @return cmd_status Secure memory command status register |
99 | 108 | */ |
100 | -uint32_t secmem_set_cmd_1(uint32_t sec_mem_cmd) | |
109 | +u32 secmem_set_cmd_1(u32 sec_mem_cmd) | |
101 | 110 | { |
102 | - uint32_t temp_reg; | |
111 | + u32 temp_reg; | |
103 | 112 | __raw_writel(sec_mem_cmd, CAAM_SMCJR0); |
104 | 113 | do { |
105 | 114 | temp_reg = __raw_readl(CAAM_SMCSJR0); |
106 | - } while(temp_reg & CMD_COMPLETE); | |
115 | + } while (temp_reg & CMD_COMPLETE); | |
107 | 116 | |
108 | 117 | return temp_reg; |
109 | 118 | } |
110 | 119 | |
111 | 120 | |
112 | 121 | |
113 | 122 | |
114 | 123 | |
115 | 124 | |
116 | 125 | |
... | ... | @@ -118,78 +127,35 @@ |
118 | 127 | * |
119 | 128 | * @return SUCCESS or ERROR_XXX |
120 | 129 | */ |
121 | -uint32_t caam_decap_blob(uint32_t plain_text, uint32_t blob_addr, uint32_t size) | |
130 | +u32 caam_decap_blob(u32 plain_text, u32 blob_addr, u32 size) | |
122 | 131 | { |
123 | - uint32_t ret = SUCCESS; | |
132 | + u32 ret = SUCCESS; | |
133 | + u32 key_sz = sizeof(skeymod); | |
134 | + u32 *decap_desc = g_jrdata.desc; | |
124 | 135 | |
125 | - /* Buffer that holds blob */ | |
136 | + /* prepare job descriptor */ | |
137 | + init_job_desc(decap_desc, 0); | |
138 | + append_load(decap_desc, PTR2CAAMDMA(skeymod), key_sz, | |
139 | + LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_KEY); | |
140 | + append_seq_in_ptr_intlen(decap_desc, blob_addr, size + 48, 0); | |
141 | + append_seq_out_ptr_intlen(decap_desc, plain_text, size, 0); | |
142 | + append_operation(decap_desc, OP_TYPE_DECAP_PROTOCOL | OP_PCLID_BLOB); | |
126 | 143 | |
144 | + flush_dcache_range((uintptr_t)blob_addr & ALIGN_MASK, | |
145 | + ((uintptr_t)blob_addr & ALIGN_MASK) | |
146 | + + ROUND(2 * size, ARCH_DMA_MINALIGN)); | |
147 | + flush_dcache_range((uintptr_t)plain_text & ALIGN_MASK, | |
148 | + (plain_text & ALIGN_MASK) | |
149 | + + ROUND(2 * size, ARCH_DMA_MINALIGN)); | |
127 | 150 | |
128 | - /* TODO: Fix Hardcoded Descriptor */ | |
129 | - decap_dsc[0] = (uint32_t)0xB0800008; | |
130 | - decap_dsc[1] = (uint32_t)0x14400010; | |
131 | - decap_dsc[2] = (uint32_t)skeymod; | |
132 | - decap_dsc[3] = (uint32_t)0xF0000000 | (0x0000ffff & (size+48) ); | |
133 | - decap_dsc[4] = blob_addr; | |
134 | - decap_dsc[5] = (uint32_t)0xF8000000 | (0x0000ffff & (size)); | |
135 | - decap_dsc[6] = (uint32_t)(uint8_t*)plain_text; | |
136 | - decap_dsc[7] = (uint32_t)0x860D0000; | |
151 | + /* Run descriptor with result written to blob buffer */ | |
152 | + ret = do_job(decap_desc); | |
137 | 153 | |
138 | -/* uncomment when using descriptor from "fsl_caam_internal.h" | |
139 | - does not use key modifier. */ | |
140 | - | |
141 | - /* Run descriptor with result written to blob buffer */ | |
142 | - /* Add job to input ring */ | |
143 | - g_input_ring[0] = (uint32_t)decap_dsc; | |
144 | - | |
145 | - flush_dcache_range((uint32_t)blob_addr & ALIGN_MASK, | |
146 | - (((uint32_t)blob_addr + 2 * size + 64) & ALIGN_MASK)); | |
147 | - flush_dcache_range((uint32_t)plain_text & ALIGN_MASK, | |
148 | - (((uint32_t)plain_text + 2 * size + 64) & ALIGN_MASK)); | |
149 | - flush_dcache_range((uint32_t)decap_dsc & ALIGN_MASK, | |
150 | - ((uint32_t)decap_dsc & ALIGN_MASK) + 128); | |
151 | - flush_dcache_range((uint32_t)g_input_ring & ALIGN_MASK, | |
152 | - ((uint32_t)g_input_ring & ALIGN_MASK) + 128); | |
153 | - | |
154 | - invalidate_dcache_range((uint32_t)decap_dsc & ALIGN_MASK, | |
155 | - ((uint32_t)decap_dsc & ALIGN_MASK) + 128); | |
156 | - invalidate_dcache_range((uint32_t)g_input_ring & ALIGN_MASK, | |
157 | - ((uint32_t)g_input_ring & ALIGN_MASK) + 128); | |
158 | - invalidate_dcache_range((uint32_t)blob_addr & ALIGN_MASK, | |
159 | - (((uint32_t)blob_addr + 2 * size + 64) & ALIGN_MASK)); | |
160 | - invalidate_dcache_range((uint32_t)plain_text & ALIGN_MASK, | |
161 | - (((uint32_t)plain_text + 2 * size + 64) & ALIGN_MASK)); | |
162 | - /* Increment jobs added */ | |
163 | - __raw_writel(1, CAAM_IRJAR0); | |
164 | - | |
165 | - /* Wait for job ring to complete the job: 1 completed job expected */ | |
166 | - while(__raw_readl(CAAM_ORSFR0) != 1); | |
167 | - | |
168 | - // TODO: check if Secure memory is cacheable. | |
169 | - flush_dcache_range((uint32_t)g_output_ring & ALIGN_MASK, | |
170 | - ((uint32_t)g_output_ring & ALIGN_MASK) + 128); | |
171 | - invalidate_dcache_range((uint32_t)g_output_ring & ALIGN_MASK, | |
172 | - ((uint32_t)g_output_ring & ALIGN_MASK) + 128); | |
173 | - /* check that descriptor address is the one expected in the output ring */ | |
174 | - if(g_output_ring[0] == (uint32_t)decap_dsc) | |
175 | - { | |
176 | - /* check if any error is reported in the output ring */ | |
177 | - if ((g_output_ring[1] & JOB_RING_STS) != 0) | |
178 | - { | |
179 | - printf("Error: blob decap job completed with errors 0x%X\n", | |
180 | - g_output_ring[1]); | |
181 | - } | |
154 | + if (ret != SUCCESS) { | |
155 | + dump_error(); | |
156 | + printf("Error: blob decap job failed 0x%x\n", ret); | |
182 | 157 | } |
183 | - else | |
184 | - { | |
185 | - printf("Error: blob decap job output ring descriptor address does" \ | |
186 | - " not match\n"); | |
187 | - } | |
188 | 158 | |
189 | - | |
190 | - /* Remove job from Job Ring Output Queue */ | |
191 | - __raw_writel(1, CAAM_ORJRR0); | |
192 | - | |
193 | 159 | return ret; |
194 | 160 | } |
195 | 161 | |
196 | 162 | |
197 | 163 | |
198 | 164 | |
199 | 165 | |
200 | 166 | |
201 | 167 | |
202 | 168 | |
203 | 169 | |
204 | 170 | |
205 | 171 | |
206 | 172 | |
207 | 173 | |
208 | 174 | |
209 | 175 | |
210 | 176 | |
211 | 177 | |
... | ... | @@ -201,130 +167,74 @@ |
201 | 167 | * |
202 | 168 | * @return SUCCESS or ERROR_XXX |
203 | 169 | */ |
204 | -uint32_t caam_gen_blob(uint32_t plain_data_addr, uint32_t blob_addr, uint32_t size) | |
170 | +u32 caam_gen_blob(u32 plain_data_addr, u32 blob_addr, u32 size) | |
205 | 171 | { |
206 | - uint32_t ret = SUCCESS; | |
207 | - | |
172 | + u32 ret = SUCCESS; | |
173 | + u32 key_sz = sizeof(skeymod); | |
174 | + u32 *encap_desc = g_jrdata.desc; | |
208 | 175 | /* Buffer to hold the resulting blob */ |
209 | - uint8_t *blob = (uint8_t *)blob_addr; | |
176 | + u8 *blob = (u8 *)CAAMDMA2PTR(blob_addr); | |
210 | 177 | |
211 | 178 | /* initialize the blob array */ |
212 | 179 | memset(blob,0,size); |
213 | 180 | |
181 | + /* prepare job descriptor */ | |
182 | + init_job_desc(encap_desc, 0); | |
183 | + append_load(encap_desc, PTR2CAAMDMA(skeymod), key_sz, | |
184 | + LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_KEY); | |
185 | + append_seq_in_ptr_intlen(encap_desc, plain_data_addr, size, 0); | |
186 | + append_seq_out_ptr_intlen(encap_desc, PTR2CAAMDMA(blob), size + 48, 0); | |
187 | + append_operation(encap_desc, OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB); | |
214 | 188 | |
215 | - /* TODO: Fix Hardcoded Descriptor */ | |
216 | - encap_dsc[0] = (uint32_t)0xB0800008; | |
217 | - encap_dsc[1] = (uint32_t)0x14400010; | |
218 | - encap_dsc[2] = (uint32_t)skeymod; | |
219 | - encap_dsc[3] = (uint32_t)0xF0000000 | (0x0000ffff & (size)); | |
220 | - encap_dsc[4] = (uint32_t)plain_data_addr; | |
221 | - encap_dsc[5] = (uint32_t)0xF8000000 | (0x0000ffff & (size+48)); | |
222 | - encap_dsc[6] = (uint32_t)blob; | |
223 | - encap_dsc[7] = (uint32_t)0x870D0000; | |
189 | + flush_dcache_range((uintptr_t)plain_data_addr & ALIGN_MASK, | |
190 | + (plain_data_addr & ALIGN_MASK) | |
191 | + + ROUND(2 * size, ARCH_DMA_MINALIGN)); | |
192 | + flush_dcache_range((uintptr_t)blob & ALIGN_MASK, | |
193 | + ((uintptr_t)blob & ALIGN_MASK) | |
194 | + + ROUND(2 * size, ARCH_DMA_MINALIGN)); | |
224 | 195 | |
225 | - /* Run descriptor with result written to blob buffer */ | |
226 | - /* Add job to input ring */ | |
227 | - g_input_ring[0] = (uint32_t)encap_dsc; | |
196 | + ret = do_job(encap_desc); | |
228 | 197 | |
229 | - flush_dcache_range((uint32_t)plain_data_addr & ALIGN_MASK, | |
230 | - (((uint32_t)plain_data_addr + 2 * size + 64) & ALIGN_MASK)); | |
231 | - flush_dcache_range((uint32_t)encap_dsc & ALIGN_MASK, | |
232 | - ((uint32_t)encap_dsc & ALIGN_MASK) + 128); | |
233 | - flush_dcache_range((uint32_t)blob & ALIGN_MASK, | |
234 | - (((uint32_t)blob + 2 * size + 64) & ALIGN_MASK)); | |
235 | - flush_dcache_range((uint32_t)g_input_ring & ALIGN_MASK, | |
236 | - ((uint32_t)g_input_ring & ALIGN_MASK) + 128); | |
237 | - | |
238 | - invalidate_dcache_range((uint32_t)blob & ALIGN_MASK, | |
239 | - (((uint32_t)blob + 2 * size + 64) & ALIGN_MASK)); | |
240 | - /* Increment jobs added */ | |
241 | - __raw_writel(1, CAAM_IRJAR0); | |
242 | - | |
243 | - /* Wait for job ring to complete the job: 1 completed job expected */ | |
244 | - while(__raw_readl(CAAM_ORSFR0) != 1); | |
245 | - | |
246 | - // flush cache | |
247 | - flush_dcache_range((uint32_t)g_output_ring & ALIGN_MASK, | |
248 | - ((uint32_t)g_output_ring & ALIGN_MASK) + 128); | |
249 | - /* check that descriptor address is the one expected in the output ring */ | |
250 | - if(g_output_ring[0] == (uint32_t)encap_dsc) | |
251 | - { | |
252 | - /* check if any error is reported in the output ring */ | |
253 | - if ((g_output_ring[1] & JOB_RING_STS) != 0) | |
254 | - { | |
255 | - printf("Error: blob encap job completed with errors 0x%X\n", | |
256 | - g_output_ring[1]); | |
257 | - } | |
198 | + if (ret != SUCCESS) { | |
199 | + dump_error(); | |
200 | + printf("Error: blob encap job failed 0x%x\n", ret); | |
258 | 201 | } |
259 | - else | |
260 | - { | |
261 | - printf("Error: blob encap job output ring descriptor address does" \ | |
262 | - " not match\n"); | |
263 | - } | |
264 | 202 | |
265 | - /* Remove job from Job Ring Output Queue */ | |
266 | - __raw_writel(1, CAAM_ORJRR0); | |
267 | - | |
268 | 203 | return ret; |
269 | 204 | } |
270 | 205 | |
271 | -uint32_t caam_hwrng(uint8_t *output_ptr, uint32_t output_len) { | |
272 | - uint32_t ret = SUCCESS; | |
273 | - | |
206 | +u32 caam_hwrng(u8 *output_ptr, u32 output_len) | |
207 | +{ | |
208 | + u32 ret = SUCCESS; | |
209 | + u32 *hwrng_desc = g_jrdata.desc; | |
274 | 210 | /* Buffer to hold the resulting output*/ |
275 | - uint8_t *output = (uint8_t *)output_ptr; | |
211 | + u8 *output = (u8 *)output_ptr; | |
276 | 212 | |
277 | 213 | /* initialize the output array */ |
278 | 214 | memset(output,0,output_len); |
279 | 215 | |
280 | - int n = 0; | |
281 | - hwrng_dsc[n++] = (uint32_t)0xB0800004; | |
282 | - hwrng_dsc[n++] = (uint32_t)0x82500000; | |
283 | - hwrng_dsc[n++] = (uint32_t)0x60340000| (0x0000ffff & output_len); | |
284 | - hwrng_dsc[n++] = (uint32_t)output; | |
216 | + /* prepare job descriptor */ | |
217 | + init_job_desc(hwrng_desc, 0); | |
218 | + append_operation(hwrng_desc, OP_ALG_ALGSEL_RNG | OP_TYPE_CLASS1_ALG); | |
219 | + append_fifo_store(hwrng_desc, PTR2CAAMDMA(output), | |
220 | + output_len, FIFOST_TYPE_RNGSTORE); | |
285 | 221 | |
286 | - /* Run descriptor with result written to blob buffer */ | |
287 | - /* Add job to input ring */ | |
288 | - // flush cache | |
289 | - g_input_ring[0] = (uint32_t)hwrng_dsc; | |
222 | + /* flush cache */ | |
223 | + flush_dcache_range((uintptr_t)hwrng_desc & ALIGN_MASK, | |
224 | + ((uintptr_t)hwrng_desc & ALIGN_MASK) | |
225 | + + ROUND(DESC_MAX_SIZE, ARCH_DMA_MINALIGN)); | |
290 | 226 | |
291 | - flush_dcache_range((uint32_t)hwrng_dsc & ALIGN_MASK, | |
292 | - ((uint32_t)hwrng_dsc & ALIGN_MASK) + 128); | |
293 | - flush_dcache_range((uint32_t)g_input_ring & ALIGN_MASK, | |
294 | - ((uint32_t)g_input_ring & ALIGN_MASK) + 128); | |
295 | - invalidate_dcache_range((uint32_t)hwrng_dsc & ALIGN_MASK, | |
296 | - ((uint32_t)hwrng_dsc & ALIGN_MASK) + 128); | |
297 | - invalidate_dcache_range((uint32_t)g_input_ring & ALIGN_MASK, | |
298 | - ((uint32_t)g_input_ring & ALIGN_MASK) + 128); | |
299 | - invalidate_dcache_range((uint32_t)output & ALIGN_MASK, | |
300 | - (((uint32_t)output + 2 * output_len + 64) & ALIGN_MASK)); | |
301 | - /* Increment jobs added */ | |
302 | - __raw_writel(1, CAAM_IRJAR0); | |
227 | + ret = do_job(hwrng_desc); | |
303 | 228 | |
304 | - /* Wait for job ring to complete the job: 1 completed job expected */ | |
305 | - size_t timeout = 100000; | |
306 | - while(__raw_readl(CAAM_ORSFR0) != 1 && timeout--); | |
307 | - flush_dcache_range((uint32_t)g_output_ring & ALIGN_MASK, | |
308 | - ((uint32_t)g_output_ring & ALIGN_MASK) + 128); | |
229 | + flush_dcache_range((uintptr_t)output & ALIGN_MASK, | |
230 | + ((uintptr_t)output & ALIGN_MASK) | |
231 | + + ROUND(2 * output_len, ARCH_DMA_MINALIGN)); | |
309 | 232 | |
310 | - /* check that descriptor address is the one expected in the output ring */ | |
311 | - if(g_output_ring[0] == (uint32_t)hwrng_dsc) { | |
312 | - /* check if any error is reported in the output ring */ | |
313 | - if ((g_output_ring[1] & JOB_RING_STS) != 0) { | |
314 | - printf("Error: RNG job completed with errors 0x%X\n", | |
315 | - g_output_ring[1]); | |
316 | - ret = -1; | |
317 | - } | |
318 | - } else { | |
319 | - printf("Error: RNG output ring descriptor address does" \ | |
320 | - " not match\n"); | |
321 | - ret = -1; | |
322 | - | |
233 | + if (ret != SUCCESS) { | |
234 | + dump_error(); | |
235 | + printf("Error: RNG generate failed 0x%x\n", ret); | |
323 | 236 | } |
324 | 237 | |
325 | - /* Remove job from Job Ring Output Queue */ | |
326 | - __raw_writel(1, CAAM_ORJRR0); | |
327 | - | |
328 | 238 | return ret; |
329 | 239 | } |
330 | 240 | |
331 | 241 | |
332 | 242 | |
333 | 243 | |
334 | 244 | |
335 | 245 | |
336 | 246 | |
337 | 247 | |
338 | 248 | |
339 | 249 | |
340 | 250 | |
341 | 251 | |
342 | 252 | |
343 | 253 | |
344 | 254 | |
345 | 255 | |
346 | 256 | |
347 | 257 | |
348 | 258 | |
349 | 259 | |
350 | 260 | |
351 | 261 | |
352 | 262 | |
353 | 263 | |
354 | 264 | |
... | ... | @@ -334,113 +244,496 @@ |
334 | 244 | */ |
335 | 245 | void caam_open(void) |
336 | 246 | { |
337 | - uint32_t temp_reg; | |
338 | - //uint32_t addr; | |
247 | + u32 temp_reg; | |
248 | + int ret; | |
339 | 249 | |
340 | - /* switch on the clock */ | |
341 | -#if defined(CONFIG_MX6) | |
250 | + /* switch on the clock */ | |
251 | +#ifndef CONFIG_ARCH_IMX8 | |
252 | + caam_clock_enable(); | |
253 | +#endif | |
254 | + | |
255 | + /* reset the CAAM */ | |
256 | + temp_reg = __raw_readl(CAAM_MCFGR) | | |
257 | + CAAM_MCFGR_DMARST | CAAM_MCFGR_SWRST; | |
258 | + __raw_writel(temp_reg, CAAM_MCFGR); | |
259 | + while (__raw_readl(CAAM_MCFGR) & CAAM_MCFGR_DMARST) | |
260 | + ; | |
261 | + | |
262 | + jr_reset(); | |
263 | + ret = do_cfg_jrqueue(); | |
264 | + | |
265 | + if (ret != SUCCESS) { | |
266 | + printf("Error CAAM JR initialization\n"); | |
267 | + return; | |
268 | + } | |
269 | + | |
270 | + /* Check if the RNG is already instantiated */ | |
271 | + temp_reg = __raw_readl(CAAM_RDSTA); | |
272 | + if (temp_reg == (RDSTA_IF0 | RDSTA_IF1 | RDSTA_SKVN)) { | |
273 | + printf("RNG already instantiated 0x%X\n", temp_reg); | |
274 | + return; | |
275 | + } | |
276 | + | |
277 | + rng_init(); | |
278 | +} | |
279 | + | |
280 | +static void caam_clock_enable(void) | |
281 | +{ | |
282 | +#if defined(CONFIG_ARCH_MX6) | |
342 | 283 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
343 | - temp_reg = __raw_readl(&mxc_ccm->CCGR0); | |
344 | - temp_reg |= MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK | | |
284 | + u32 reg; | |
285 | + | |
286 | + reg = __raw_readl(&mxc_ccm->CCGR0); | |
287 | + | |
288 | + reg |= (MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK | | |
345 | 289 | MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK | |
346 | - MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK; | |
347 | - __raw_writel(temp_reg, &mxc_ccm->CCGR0); | |
348 | -#elif defined(CONFIG_MX7) | |
349 | - HW_CCM_CCGR_SET(36, MXC_CCM_CCGR36_CAAM_DOMAIN0_MASK); | |
290 | + MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK); | |
291 | + | |
292 | + __raw_writel(reg, &mxc_ccm->CCGR0); | |
293 | + | |
294 | +#ifndef CONFIG_MX6UL | |
295 | + /* EMI slow clk */ | |
296 | + reg = __raw_readl(&mxc_ccm->CCGR6); | |
297 | + reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK; | |
298 | + | |
299 | + __raw_writel(reg, &mxc_ccm->CCGR6); | |
350 | 300 | #endif |
351 | 301 | |
352 | - /* MID for CAAM - already done by HAB in ROM during preconfigure, | |
353 | - * That is JROWN for JR0/1 = 1 (TZ, Secure World, ARM) | |
354 | - * JRNSMID and JRSMID for JR0/1 = 2 (TZ, Secure World, CAAM) | |
355 | - * | |
356 | - * However, still need to initialize Job Rings as these are torn | |
357 | - * down by HAB for each command | |
358 | - */ | |
302 | +#elif defined(CONFIG_ARCH_MX7) | |
303 | + HW_CCM_CCGR_SET(36, MXC_CCM_CCGR36_CAAM_DOMAIN0_MASK); | |
304 | +#elif defined(CONFIG_ARCH_MX7ULP) | |
305 | + pcc_clock_enable(PER_CLK_CAAM, true); | |
306 | +#endif | |
307 | +} | |
359 | 308 | |
360 | - /* Initialize job ring addresses */ | |
361 | - __raw_writel((uint32_t)g_input_ring, CAAM_IRBAR0); // input ring address | |
362 | - __raw_writel((uint32_t)g_output_ring, CAAM_ORBAR0); // output ring address | |
309 | +static void kick_trng(u32 ent_delay) | |
310 | +{ | |
311 | + u32 samples = 512; /* number of bits to generate and test */ | |
312 | + u32 mono_min = 195; | |
313 | + u32 mono_max = 317; | |
314 | + u32 mono_range = mono_max - mono_min; | |
315 | + u32 poker_min = 1031; | |
316 | + u32 poker_max = 1600; | |
317 | + u32 poker_range = poker_max - poker_min + 1; | |
318 | + u32 retries = 2; | |
319 | + u32 lrun_max = 32; | |
320 | + s32 run_1_min = 27; | |
321 | + s32 run_1_max = 107; | |
322 | + s32 run_1_range = run_1_max - run_1_min; | |
323 | + s32 run_2_min = 7; | |
324 | + s32 run_2_max = 62; | |
325 | + s32 run_2_range = run_2_max - run_2_min; | |
326 | + s32 run_3_min = 0; | |
327 | + s32 run_3_max = 39; | |
328 | + s32 run_3_range = run_3_max - run_3_min; | |
329 | + s32 run_4_min = -1; | |
330 | + s32 run_4_max = 26; | |
331 | + s32 run_4_range = run_4_max - run_4_min; | |
332 | + s32 run_5_min = -1; | |
333 | + s32 run_5_max = 18; | |
334 | + s32 run_5_range = run_5_max - run_5_min; | |
335 | + s32 run_6_min = -1; | |
336 | + s32 run_6_max = 17; | |
337 | + s32 run_6_range = run_6_max - run_6_min; | |
338 | + u32 val; | |
363 | 339 | |
364 | - /* Initialize job ring sizes to 1 */ | |
365 | - __raw_writel(JOB_RING_ENTRIES, CAAM_IRSR0); | |
366 | - __raw_writel(JOB_RING_ENTRIES, CAAM_ORSR0); | |
340 | + /* Put RNG in program mode */ | |
341 | + setbits_le32(CAAM_RTMCTL, RTMCTL_PGM); | |
342 | + /* Configure the RNG Entropy Delay | |
343 | + * Performance-wise, it does not make sense to | |
344 | + * set the delay to a value that is lower | |
345 | + * than the last one that worked (i.e. the state handles | |
346 | + * were instantiated properly. Thus, instead of wasting | |
347 | + * time trying to set the values controlling the sample | |
348 | + * frequency, the function simply returns. | |
349 | + */ | |
350 | + val = __raw_readl(CAAM_RTSDCTL); | |
351 | + val &= BM_TRNG_ENT_DLY; | |
352 | + val >>= BS_TRNG_ENT_DLY; | |
353 | + if (ent_delay < val) { | |
354 | + /* Put RNG4 into run mode */ | |
355 | + clrbits_le32(CAAM_RTMCTL, RTMCTL_PGM); | |
356 | + return; | |
357 | + } | |
367 | 358 | |
368 | - /* HAB disables interrupts for JR0 so do the same here */ | |
369 | - temp_reg = __raw_readl(CAAM_JRCFGR0_LS) | JRCFG_LS_IMSK; | |
370 | - __raw_writel(temp_reg, CAAM_JRCFGR0_LS); | |
359 | + val = (ent_delay << BS_TRNG_ENT_DLY) | samples; | |
360 | + __raw_writel(val, CAAM_RTSDCTL); | |
371 | 361 | |
372 | - /********* Initialize and instantiate the RNG *******************/ | |
373 | - /* if RNG already instantiated then skip it */ | |
374 | - if ((__raw_readl(CAAM_RDSTA) & RDSTA_IF0) != RDSTA_IF0) | |
375 | - { | |
376 | - /* Enter TRNG Program mode */ | |
377 | - __raw_writel(RTMCTL_PGM, CAAM_RTMCTL); | |
362 | + /* min. freq. count, equal to 1/2 of the entropy sample length */ | |
363 | + __raw_writel(ent_delay >> 1, CAAM_RTFRQMIN); | |
378 | 364 | |
379 | - /* Set OSC_DIV field to TRNG */ | |
380 | - temp_reg = __raw_readl(CAAM_RTMCTL) | (RNG_TRIM_OSC_DIV << 2); | |
381 | - __raw_writel(temp_reg, CAAM_RTMCTL); | |
365 | + /* max. freq. count, equal to 32 times the entropy sample length */ | |
366 | + __raw_writel(ent_delay << 5, CAAM_RTFRQMAX); | |
382 | 367 | |
383 | - /* Set delay */ | |
384 | - __raw_writel(((RNG_TRIM_ENT_DLY << 16) | 0x09C4), CAAM_RTSDCTL); | |
385 | - __raw_writel((RNG_TRIM_ENT_DLY >> 1), CAAM_RTFRQMIN); | |
386 | - __raw_writel((RNG_TRIM_ENT_DLY << 4), CAAM_RTFRQMAX); | |
368 | + __raw_writel((retries << 16) | lrun_max, CAAM_RTSCMISC); | |
369 | + __raw_writel(poker_max, CAAM_RTPKRMAX); | |
370 | + __raw_writel(poker_range, CAAM_RTPKRRNG); | |
371 | + __raw_writel((mono_range << 16) | mono_max, CAAM_RTSCML); | |
372 | + __raw_writel((run_1_range << 16) | run_1_max, CAAM_RTSCR1L); | |
373 | + __raw_writel((run_2_range << 16) | run_2_max, CAAM_RTSCR2L); | |
374 | + __raw_writel((run_3_range << 16) | run_3_max, CAAM_RTSCR3L); | |
375 | + __raw_writel((run_4_range << 16) | run_4_max, CAAM_RTSCR4L); | |
376 | + __raw_writel((run_5_range << 16) | run_5_max, CAAM_RTSCR5L); | |
377 | + __raw_writel((run_6_range << 16) | run_6_max, CAAM_RTSCR6PL); | |
387 | 378 | |
388 | - /* Resume TRNG Run mode */ | |
389 | - temp_reg = __raw_readl(CAAM_RTMCTL) ^ RTMCTL_PGM; | |
390 | - __raw_writel(temp_reg, CAAM_RTMCTL); | |
379 | + val = __raw_readl(CAAM_RTMCTL); | |
380 | + /* | |
381 | + * Select raw sampling in both entropy shifter | |
382 | + * and statistical checker | |
383 | + */ | |
384 | + val &= ~BM_TRNG_SAMP_MODE; | |
385 | + val |= TRNG_SAMP_MODE_RAW_ES_SC; | |
386 | + /* Put RNG4 into run mode */ | |
387 | + val &= ~RTMCTL_PGM; | |
388 | +/*test with sample mode only */ | |
389 | + __raw_writel(val, CAAM_RTMCTL); | |
391 | 390 | |
392 | 391 | /* Clear the ERR bit in RTMCTL if set. The TRNG error can occur when the |
393 | 392 | * RNG clock is not within 1/2x to 8x the system clock. |
394 | 393 | * This error is possible if ROM code does not initialize the system PLLs |
395 | 394 | * immediately after PoR. |
396 | 395 | */ |
397 | - temp_reg = __raw_readl(CAAM_RTMCTL) | RTMCTL_ERR; | |
398 | - __raw_writel(temp_reg, CAAM_RTMCTL); | |
396 | + /* setbits_le32(CAAM_RTMCTL, RTMCTL_ERR); */ | |
397 | +} | |
399 | 398 | |
400 | - /* Run descriptor to instantiate the RNG */ | |
401 | - /* Add job to input ring */ | |
402 | - g_input_ring[0] = (uint32_t)rng_inst_dsc; | |
399 | +/* | |
400 | + * Descriptors to instantiate SH0, SH1, load the keys | |
401 | + */ | |
402 | +static const u32 rng_inst_sh0_desc[] = { | |
403 | + /* Header, don't setup the size */ | |
404 | + CAAM_HDR_CTYPE | CAAM_HDR_ONE | CAAM_HDR_START_INDEX(0), | |
405 | + /* Operation instantiation (sh0) */ | |
406 | + CAAM_PROTOP_CTYPE | CAAM_C1_RNG | ALGO_RNG_SH(0) | ALGO_RNG_INSTANTIATE, | |
407 | +}; | |
403 | 408 | |
404 | - flush_dcache_range((uint32_t)g_input_ring & 0xffffffe0, | |
405 | - ((uint32_t)g_input_ring & 0xffffffe0) + 128); | |
406 | - /* Increment jobs added */ | |
409 | +static const u32 rng_inst_sh1_desc[] = { | |
410 | + /* wait for done - Jump to next entry */ | |
411 | + CAAM_C1_JUMP | CAAM_JUMP_LOCAL | CAAM_JUMP_TST_ALL_COND_TRUE | |
412 | + | CAAM_JUMP_OFFSET(1), | |
413 | + /* Clear written register (write 1) */ | |
414 | + CAAM_C0_LOAD_IMM | CAAM_DST_CLEAR_WRITTEN | sizeof(u32), | |
415 | + 0x00000001, | |
416 | + /* Operation instantiation (sh1) */ | |
417 | + CAAM_PROTOP_CTYPE | CAAM_C1_RNG | ALGO_RNG_SH(1) | |
418 | + | ALGO_RNG_INSTANTIATE, | |
419 | +}; | |
420 | + | |
421 | +static const u32 rng_inst_load_keys[] = { | |
422 | + /* wait for done - Jump to next entry */ | |
423 | + CAAM_C1_JUMP | CAAM_JUMP_LOCAL | CAAM_JUMP_TST_ALL_COND_TRUE | |
424 | + | CAAM_JUMP_OFFSET(1), | |
425 | + /* Clear written register (write 1) */ | |
426 | + CAAM_C0_LOAD_IMM | CAAM_DST_CLEAR_WRITTEN | sizeof(u32), | |
427 | + 0x00000001, | |
428 | + /* Generate the Key */ | |
429 | + CAAM_PROTOP_CTYPE | CAAM_C1_RNG | BM_ALGO_RNG_SK | ALGO_RNG_GENERATE, | |
430 | +}; | |
431 | + | |
432 | +static void do_inst_desc(u32 *desc, u32 status) | |
433 | +{ | |
434 | + u32 *pdesc = desc; | |
435 | + u8 desc_len; | |
436 | + bool add_sh0 = false; | |
437 | + bool add_sh1 = false; | |
438 | + bool load_keys = false; | |
439 | + | |
440 | + /* | |
441 | + * Modify the the descriptor to remove if necessary: | |
442 | + * - The key loading | |
443 | + * - One of the SH already instantiated | |
444 | + */ | |
445 | + desc_len = RNG_DESC_SH0_SIZE; | |
446 | + if ((status & RDSTA_IF0) != RDSTA_IF0) | |
447 | + add_sh0 = true; | |
448 | + | |
449 | + if ((status & RDSTA_IF1) != RDSTA_IF1) { | |
450 | + add_sh1 = true; | |
451 | + if (add_sh0) | |
452 | + desc_len += RNG_DESC_SH1_SIZE; | |
453 | + } | |
454 | + | |
455 | + if ((status & RDSTA_SKVN) != RDSTA_SKVN) { | |
456 | + load_keys = true; | |
457 | + desc_len += RNG_DESC_KEYS_SIZE; | |
458 | + } | |
459 | + | |
460 | + /* Copy the SH0 descriptor anyway */ | |
461 | + memcpy(pdesc, rng_inst_sh0_desc, sizeof(rng_inst_sh0_desc)); | |
462 | + pdesc += RNG_DESC_SH0_SIZE; | |
463 | + | |
464 | + if (load_keys) { | |
465 | + debug("RNG - Load keys\n"); | |
466 | + memcpy(pdesc, rng_inst_load_keys, sizeof(rng_inst_load_keys)); | |
467 | + pdesc += RNG_DESC_KEYS_SIZE; | |
468 | + } | |
469 | + | |
470 | + if (add_sh1) { | |
471 | + if (add_sh0) { | |
472 | + debug("RNG - Instantiation of SH0 and SH1\n"); | |
473 | + /* Add the sh1 descriptor */ | |
474 | + memcpy(pdesc, rng_inst_sh1_desc, | |
475 | + sizeof(rng_inst_sh1_desc)); | |
476 | + } else { | |
477 | + debug("RNG - Instantiation of SH1 only\n"); | |
478 | + /* Modify the SH0 descriptor to instantiate only SH1 */ | |
479 | + desc[1] &= ~BM_ALGO_RNG_SH; | |
480 | + desc[1] |= ALGO_RNG_SH(1); | |
481 | + } | |
482 | + } | |
483 | + | |
484 | + /* Setup the descriptor size */ | |
485 | + desc[0] &= ~(0x3F); | |
486 | + desc[0] |= CAAM_HDR_DESCLEN(desc_len); | |
487 | +} | |
488 | + | |
489 | +static int jr_reset(void) | |
490 | +{ | |
491 | + /* | |
492 | + * Function reset the Job Ring HW | |
493 | + * Reset is done in 2 steps: | |
494 | + * - Flush all pending jobs (Set RESET bit) | |
495 | + * - Reset the Job Ring (Set RESET bit second time) | |
496 | + */ | |
497 | + u16 timeout = 10000; | |
498 | + u32 reg_val; | |
499 | + | |
500 | + /* Mask interrupts to poll for reset completion status */ | |
501 | + setbits_le32(CAAM_JRCFGR0_LS, BM_JRCFGR_LS_IMSK); | |
502 | + | |
503 | + /* Initiate flush (required prior to reset) */ | |
504 | + __raw_writel(JRCR_RESET, CAAM_JRCR0); | |
505 | + do { | |
506 | + reg_val = __raw_readl(CAAM_JRINTR0); | |
507 | + reg_val &= BM_JRINTR_HALT; | |
508 | + } while ((reg_val == JRINTR_HALT_ONGOING) && --timeout); | |
509 | + | |
510 | + if (!timeout || reg_val != JRINTR_HALT_DONE) { | |
511 | + printf("Failed to flush job ring\n"); | |
512 | + return ERROR_ANY; | |
513 | + } | |
514 | + | |
515 | + /* Initiate reset */ | |
516 | + timeout = 100; | |
517 | + __raw_writel(JRCR_RESET, CAAM_JRCR0); | |
518 | + do { | |
519 | + reg_val = __raw_readl(CAAM_JRCR0); | |
520 | + } while ((reg_val & JRCR_RESET) && --timeout); | |
521 | + | |
522 | + if (!timeout) { | |
523 | + printf("Failed to reset job ring\n"); | |
524 | + return ERROR_ANY; | |
525 | + } | |
526 | + | |
527 | + return 0; | |
528 | +} | |
529 | + | |
530 | +static int do_job(u32 *desc) | |
531 | +{ | |
532 | + int ret; | |
533 | + phys_addr_t p_desc = virt_to_phys(desc); | |
534 | + | |
535 | + if (__raw_readl(CAAM_IRSAR0) == 0) | |
536 | + return ERROR_ANY; | |
537 | + g_jrdata.inrings[0].desc = p_desc; | |
538 | + | |
539 | + flush_dcache_range((uintptr_t)g_jrdata.inrings & ALIGN_MASK, | |
540 | + ((uintptr_t)g_jrdata.inrings & ALIGN_MASK) | |
541 | + + ROUND(DESC_MAX_SIZE, ARCH_DMA_MINALIGN)); | |
542 | + flush_dcache_range((uintptr_t)desc & ALIGN_MASK, | |
543 | + ((uintptr_t)desc & ALIGN_MASK) | |
544 | + + ROUND(DESC_MAX_SIZE, ARCH_DMA_MINALIGN)); | |
545 | + | |
546 | + /* Inform HW that a new JR is available */ | |
407 | 547 | __raw_writel(1, CAAM_IRJAR0); |
548 | + while (__raw_readl(CAAM_ORSFR0) == 0) | |
549 | + ; | |
408 | 550 | |
409 | - /* Wait for job ring to complete the job: 1 completed job expected */ | |
410 | - while(__raw_readl(CAAM_ORSFR0) != 1); | |
551 | + flush_dcache_range((uintptr_t)g_jrdata.outrings & ALIGN_MASK, | |
552 | + ((uintptr_t)g_jrdata.outrings & ALIGN_MASK) | |
553 | + + ROUND(DESC_MAX_SIZE, ARCH_DMA_MINALIGN)); | |
411 | 554 | |
555 | + if (PTR2CAAMDMA(desc) == g_jrdata.outrings[0].desc) { | |
556 | + ret = g_jrdata.outrings[0].status; | |
557 | + } else { | |
558 | + dump_error(); | |
559 | + ret = ERROR_ANY; | |
560 | + } | |
412 | 561 | |
413 | - invalidate_dcache_range((uint32_t)g_output_ring & 0xffffffe0, | |
414 | - ((uint32_t)g_output_ring & 0xffffffe0) + 128); | |
562 | + /* Acknowledge interrupt */ | |
563 | + setbits_le32(CAAM_JRINTR0, JRINTR_JRI); | |
415 | 564 | |
416 | - /* check that descriptor address is the one expected in the out ring */ | |
417 | - if(g_output_ring[0] == (uint32_t)rng_inst_dsc) | |
418 | - { | |
419 | - /* check if any error is reported in the output ring */ | |
420 | - if ((g_output_ring[1] & JOB_RING_STS) != 0) | |
421 | - { | |
422 | - printf("Error: RNG instantiation errors g_output_ring[1]: 0x%X\n" | |
423 | - , g_output_ring[1]); | |
424 | - printf("RTMCTL 0x%X\n", __raw_readl(CAAM_RTMCTL)); | |
425 | - printf("RTSTATUS 0x%X\n", __raw_readl(CAAM_RTSTATUS)); | |
426 | - printf("RTSTA 0x%X\n", __raw_readl(CAAM_RDSTA)); | |
427 | - } | |
565 | + /* Remove the JR from the output list even if no JR caller found */ | |
566 | + __raw_writel(1, CAAM_ORJRR0); | |
567 | + | |
568 | + return ret; | |
569 | +} | |
570 | + | |
571 | +static int do_cfg_jrqueue(void) | |
572 | +{ | |
573 | + u32 value = 0; | |
574 | + phys_addr_t ip_base; | |
575 | + phys_addr_t op_base; | |
576 | + | |
577 | + /* check if already configured after relocation */ | |
578 | + if (g_jrdata.status & RING_RELOC_INIT) | |
579 | + return 0; | |
580 | + | |
581 | + /* | |
582 | + * jr configuration needs to be updated once, after relocation to ensure | |
583 | + * using the right buffers. | |
584 | + * When buffers are updated after relocation the flag RING_RELOC_INIT | |
585 | + * is used to prevent extra updates | |
586 | + */ | |
587 | + if (gd->flags & GD_FLG_RELOC) { | |
588 | + g_jrdata.inrings = (struct inring_entry *) | |
589 | + memalign(ARCH_DMA_MINALIGN, | |
590 | + ARCH_DMA_MINALIGN); | |
591 | + g_jrdata.outrings = (struct outring_entry *) | |
592 | + memalign(ARCH_DMA_MINALIGN, | |
593 | + ARCH_DMA_MINALIGN); | |
594 | + g_jrdata.desc = (u32 *) | |
595 | + memalign(ARCH_DMA_MINALIGN, ARCH_DMA_MINALIGN); | |
596 | + g_jrdata.status |= RING_RELOC_INIT; | |
597 | + } else { | |
598 | + u32 align_idx = 0; | |
599 | + | |
600 | + /* Ensure 64bits buffers addresses alignment */ | |
601 | + if ((uintptr_t)g_jrdata.raw_addr & 0x7) | |
602 | + align_idx = 1; | |
603 | + g_jrdata.inrings = (struct inring_entry *) | |
604 | + (&g_jrdata.raw_addr[align_idx]); | |
605 | + g_jrdata.outrings = (struct outring_entry *) | |
606 | + (&g_jrdata.raw_addr[align_idx + 2]); | |
607 | + g_jrdata.desc = (u32 *)(&g_jrdata.raw_addr[align_idx + 4]); | |
608 | + g_jrdata.status |= RING_EARLY_INIT; | |
428 | 609 | } |
429 | - else | |
430 | - { | |
431 | - printf("Error: RNG job output ring descriptor address does " \ | |
432 | - "not match: 0x%X != 0x%X \n", g_output_ring[0], rng_inst_dsc[0]); | |
610 | + | |
611 | + if (!g_jrdata.inrings || !g_jrdata.outrings) | |
612 | + return ERROR_ANY; | |
613 | + | |
614 | + /* Configure the HW Job Rings */ | |
615 | + ip_base = virt_to_phys((void *)g_jrdata.inrings); | |
616 | + op_base = virt_to_phys((void *)g_jrdata.outrings); | |
617 | + __raw_writel(ip_base, CAAM_IRBAR0); | |
618 | + __raw_writel(1, CAAM_IRSR0); | |
619 | + | |
620 | + __raw_writel(op_base, CAAM_ORBAR0); | |
621 | + __raw_writel(1, CAAM_ORSR0); | |
622 | + | |
623 | + setbits_le32(CAAM_JRINTR0, JRINTR_JRI); | |
624 | + | |
625 | + /* | |
626 | + * Configure interrupts but disable it: | |
627 | + * Optimization to generate an interrupt either when there are | |
628 | + * half of the job done or when there is a job done and | |
629 | + * 10 clock cycles elapse without new job complete | |
630 | + */ | |
631 | + value = 10 << BS_JRCFGR_LS_ICTT; | |
632 | + value |= (1 << BS_JRCFGR_LS_ICDCT) & BM_JRCFGR_LS_ICDCT; | |
633 | + value |= BM_JRCFGR_LS_ICEN; | |
634 | + value |= BM_JRCFGR_LS_IMSK; | |
635 | + __raw_writel(value, CAAM_JRCFGR0_LS); | |
636 | + | |
637 | + /* Enable deco watchdog */ | |
638 | + setbits_le32(CAAM_MCFGR, BM_MCFGR_WDE); | |
639 | + | |
640 | + return 0; | |
641 | +} | |
642 | + | |
643 | +static void do_clear_rng_error(void) | |
644 | +{ | |
645 | + u32 val; | |
646 | + | |
647 | + val = __raw_readl(CAAM_RTMCTL); | |
648 | + | |
649 | + if (val & (RTMCTL_ERR | RTMCTL_FCT_FAIL)) { | |
650 | + setbits_le32(CAAM_RTMCTL, RTMCTL_ERR); | |
651 | + val = __raw_readl(CAAM_RTMCTL); | |
433 | 652 | } |
653 | +} | |
434 | 654 | |
435 | - /* ensure that the RNG was correctly instantiated */ | |
436 | - temp_reg = __raw_readl(CAAM_RDSTA); | |
437 | - if (temp_reg != (RDSTA_IF0 | RDSTA_SKVN)) | |
438 | - { | |
439 | - printf("Error: RNG instantiation failed 0x%X\n", temp_reg); | |
655 | +static int do_instantiation(void) | |
656 | +{ | |
657 | + int ret = ERROR_ANY; | |
658 | + u32 cha_vid_ls; | |
659 | + u32 ent_delay; | |
660 | + u32 status; | |
661 | + | |
662 | + if (!g_jrdata.desc) { | |
663 | + printf("%d: CAAM Descriptor allocation error\n", __LINE__); | |
664 | + return ERROR_ANY; | |
665 | + } | |
666 | + | |
667 | + cha_vid_ls = __raw_readl(CAAM_CHAVID_LS); | |
668 | + | |
669 | + /* | |
670 | + * If SEC has RNG version >= 4 and RNG state handle has not been | |
671 | + * already instantiated, do RNG instantiation | |
672 | + */ | |
673 | + if (((cha_vid_ls & BM_CHAVID_LS_RNGVID) >> BS_CHAVID_LS_RNGVID) < 4) { | |
674 | + printf("%d: RNG already instantiated\n", __LINE__); | |
675 | + return 0; | |
676 | + } | |
677 | + | |
678 | + ent_delay = TRNG_SDCTL_ENT_DLY_MIN; | |
679 | + | |
680 | + do { | |
681 | + /* Read the CAAM RNG status */ | |
682 | + status = __raw_readl(CAAM_RDSTA); | |
683 | + | |
684 | + if ((status & RDSTA_IF0) != RDSTA_IF0) { | |
685 | + /* Configure the RNG entropy delay */ | |
686 | + kick_trng(ent_delay); | |
687 | + ent_delay += 400; | |
440 | 688 | } |
441 | - /* Remove job from Job Ring Output Queue */ | |
442 | - __raw_writel(1, CAAM_ORJRR0); | |
689 | + | |
690 | + do_clear_rng_error(); | |
691 | + | |
692 | + if ((status & (RDSTA_IF0 | RDSTA_IF1)) != | |
693 | + (RDSTA_IF0 | RDSTA_IF1)) { | |
694 | + /* Prepare the instantiation descriptor */ | |
695 | + do_inst_desc(g_jrdata.desc, status); | |
696 | + | |
697 | + /* Run Job */ | |
698 | + ret = do_job(g_jrdata.desc); | |
699 | + | |
700 | + if (ret == ERROR_ANY) { | |
701 | + /* CAAM JR failure ends here */ | |
702 | + printf("RNG Instantiation error\n"); | |
703 | + dump_error(); | |
704 | + goto end_instantation; | |
705 | + } | |
706 | + } else { | |
707 | + ret = SUCCESS; | |
708 | + printf("RNG instantiation done (%d)\n", ent_delay); | |
709 | + goto end_instantation; | |
710 | + } | |
711 | + } while (ent_delay < TRNG_SDCTL_ENT_DLY_MAX); | |
712 | + | |
713 | + printf("RNG Instantation Failure - Entropy delay (%d)\n", ent_delay); | |
714 | + ret = ERROR_ANY; | |
715 | + | |
716 | +end_instantation: | |
717 | + return ret; | |
718 | +} | |
719 | + | |
720 | +static void rng_init(void) | |
721 | +{ | |
722 | + int ret; | |
723 | + | |
724 | + ret = jr_reset(); | |
725 | + if (ret != SUCCESS) { | |
726 | + printf("Error CAAM JR reset\n"); | |
727 | + return; | |
443 | 728 | } |
729 | + | |
730 | + ret = do_instantiation(); | |
731 | + | |
732 | + if (ret != SUCCESS) | |
733 | + printf("Error do_instantiation\n"); | |
734 | + | |
735 | + jr_reset(); | |
736 | + | |
444 | 737 | return; |
445 | 738 | } |
drivers/crypto/fsl_caam_internal.h
1 | 1 | /* |
2 | 2 | * Copyright (c) 2012-2016, Freescale Semiconductor, Inc. |
3 | 3 | * All rights reserved. |
4 | + * Copyright 2018 NXP | |
4 | 5 | * |
5 | 6 | * Redistribution and use in source and binary forms, with or without modification, |
6 | 7 | * are permitted provided that the following conditions are met: |
... | ... | @@ -29,7 +30,7 @@ |
29 | 30 | */ |
30 | 31 | |
31 | 32 | #ifndef __CAAM_INTERNAL_H__ |
32 | -#define __CAAM_INTERNAL_H__ | |
33 | +#define __CAAM_INTERNAL_H__ | |
33 | 34 | |
34 | 35 | /* 4kbyte pages */ |
35 | 36 | #define CAAM_SEC_RAM_START_ADDR CAAM_ARB_BASE_ADDR |
36 | 37 | |
37 | 38 | |
38 | 39 | |
39 | 40 | |
40 | 41 | |
... | ... | @@ -40,69 +41,82 @@ |
40 | 41 | #define SEC_MEM_PAGE3 (CAAM_SEC_RAM_START_ADDR + 0x3000) |
41 | 42 | |
42 | 43 | /* Configuration and special key registers */ |
43 | -#define CAAM_MCFGR CONFIG_SYS_FSL_SEC_ADDR + 0x0004 | |
44 | -#define CAAM_SCFGR CONFIG_SYS_FSL_SEC_ADDR + 0x000c | |
45 | -#define CAAM_JR0MIDR CONFIG_SYS_FSL_SEC_ADDR + 0x0010 | |
46 | -#define CAAM_JR1MIDR CONFIG_SYS_FSL_SEC_ADDR + 0x0018 | |
47 | -#define CAAM_DECORR CONFIG_SYS_FSL_SEC_ADDR + 0x009c | |
48 | -#define CAAM_DECO0MID CONFIG_SYS_FSL_SEC_ADDR + 0x00a0 | |
49 | -#define CAAM_DAR CONFIG_SYS_FSL_SEC_ADDR + 0x0120 | |
50 | -#define CAAM_DRR CONFIG_SYS_FSL_SEC_ADDR + 0x0124 | |
51 | -#define CAAM_JDKEKR CONFIG_SYS_FSL_SEC_ADDR + 0x0400 | |
52 | -#define CAAM_TDKEKR CONFIG_SYS_FSL_SEC_ADDR + 0x0420 | |
53 | -#define CAAM_TDSKR CONFIG_SYS_FSL_SEC_ADDR + 0x0440 | |
54 | -#define CAAM_SKNR CONFIG_SYS_FSL_SEC_ADDR + 0x04e0 | |
55 | -#define CAAM_SMSTA CONFIG_SYS_FSL_SEC_ADDR + 0x0FB4 | |
56 | -#define CAAM_STA CONFIG_SYS_FSL_SEC_ADDR + 0x0FD4 | |
57 | -#define CAAM_SMPO_0 CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC | |
44 | +#define CAAM_MCFGR (CONFIG_SYS_FSL_SEC_ADDR + 0x0004) | |
45 | +#define CAAM_SCFGR (CONFIG_SYS_FSL_SEC_ADDR + 0x000c) | |
46 | +#define CAAM_JR0MIDR (CONFIG_SYS_FSL_SEC_ADDR + 0x0010) | |
47 | +#define CAAM_JR1MIDR (CONFIG_SYS_FSL_SEC_ADDR + 0x0018) | |
48 | +#define CAAM_DECORR (CONFIG_SYS_FSL_SEC_ADDR + 0x009c) | |
49 | +#define CAAM_DECO0MID (CONFIG_SYS_FSL_SEC_ADDR + 0x00a0) | |
50 | +#define CAAM_DAR (CONFIG_SYS_FSL_SEC_ADDR + 0x0120) | |
51 | +#define CAAM_DRR (CONFIG_SYS_FSL_SEC_ADDR + 0x0124) | |
52 | +#define CAAM_JDKEKR (CONFIG_SYS_FSL_SEC_ADDR + 0x0400) | |
53 | +#define CAAM_TDKEKR (CONFIG_SYS_FSL_SEC_ADDR + 0x0420) | |
54 | +#define CAAM_TDSKR (CONFIG_SYS_FSL_SEC_ADDR + 0x0440) | |
55 | +#define CAAM_SKNR (CONFIG_SYS_FSL_SEC_ADDR + 0x04e0) | |
56 | +#define CAAM_SMSTA (CONFIG_SYS_FSL_SEC_ADDR + 0x0FB4) | |
57 | +#define CAAM_STA (CONFIG_SYS_FSL_SEC_ADDR + 0x0FD4) | |
58 | +#define CAAM_SMPO_0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC) | |
59 | +#define CAAM_CHAVID_LS (CONFIG_SYS_FSL_SEC_ADDR + 0x0FEC) | |
60 | +#define CAAM_FAR (CONFIG_SYS_FSL_SEC_ADDR + 0x0FC0) | |
61 | +#define CAAM_FAMR (CONFIG_SYS_FSL_SEC_ADDR + 0x0FC8) | |
62 | +#define CAAM_FADR (CONFIG_SYS_FSL_SEC_ADDR + 0x0FCC) | |
58 | 63 | |
59 | 64 | /* RNG registers */ |
60 | -#define CAAM_RTMCTL CONFIG_SYS_FSL_SEC_ADDR + 0x0600 | |
61 | -#define CAAM_RTSDCTL CONFIG_SYS_FSL_SEC_ADDR + 0x0610 | |
62 | -#define CAAM_RTFRQMIN CONFIG_SYS_FSL_SEC_ADDR + 0x0618 | |
63 | -#define CAAM_RTFRQMAX CONFIG_SYS_FSL_SEC_ADDR + 0x061C | |
64 | -#define CAAM_RTSTATUS CONFIG_SYS_FSL_SEC_ADDR + 0x063C | |
65 | -#define CAAM_RDSTA CONFIG_SYS_FSL_SEC_ADDR + 0x06C0 | |
65 | +#define CAAM_RTMCTL (CONFIG_SYS_FSL_SEC_ADDR + 0x0600) | |
66 | +#define CAAM_RTSCMISC (CONFIG_SYS_FSL_SEC_ADDR + 0x0604) | |
67 | +#define CAAM_RTPKRRNG (CONFIG_SYS_FSL_SEC_ADDR + 0x0608) | |
68 | +#define CAAM_RTPKRMAX (CONFIG_SYS_FSL_SEC_ADDR + 0x060C) | |
69 | +#define CAAM_RTSDCTL (CONFIG_SYS_FSL_SEC_ADDR + 0x0610) | |
70 | +#define CAAM_RTFRQMIN (CONFIG_SYS_FSL_SEC_ADDR + 0x0618) | |
71 | +#define CAAM_RTFRQMAX (CONFIG_SYS_FSL_SEC_ADDR + 0x061C) | |
72 | +#define CAAM_RTSCML (CONFIG_SYS_FSL_SEC_ADDR + 0x0620) | |
73 | +#define CAAM_RTSCR1L (CONFIG_SYS_FSL_SEC_ADDR + 0x0624) | |
74 | +#define CAAM_RTSCR2L (CONFIG_SYS_FSL_SEC_ADDR + 0x0628) | |
75 | +#define CAAM_RTSCR3L (CONFIG_SYS_FSL_SEC_ADDR + 0x062C) | |
76 | +#define CAAM_RTSCR4L (CONFIG_SYS_FSL_SEC_ADDR + 0x0630) | |
77 | +#define CAAM_RTSCR5L (CONFIG_SYS_FSL_SEC_ADDR + 0x0634) | |
78 | +#define CAAM_RTSCR6PL (CONFIG_SYS_FSL_SEC_ADDR + 0x0638) | |
79 | +#define CAAM_RTSTATUS (CONFIG_SYS_FSL_SEC_ADDR + 0x063C) | |
80 | +#define CAAM_RDSTA (CONFIG_SYS_FSL_SEC_ADDR + 0x06C0) | |
66 | 81 | |
67 | 82 | /* Job Ring 0 registers */ |
68 | -#define CAAM_IRBAR0 CONFIG_SYS_FSL_SEC_ADDR + 0x1004 | |
69 | -#define CAAM_IRSR0 CONFIG_SYS_FSL_SEC_ADDR + 0x100c | |
70 | -#define CAAM_IRSAR0 CONFIG_SYS_FSL_SEC_ADDR + 0x1014 | |
71 | -#define CAAM_IRJAR0 CONFIG_SYS_FSL_SEC_ADDR + 0x101c | |
72 | -#define CAAM_ORBAR0 CONFIG_SYS_FSL_SEC_ADDR + 0x1024 | |
73 | -#define CAAM_ORSR0 CONFIG_SYS_FSL_SEC_ADDR + 0x102c | |
74 | -#define CAAM_ORJRR0 CONFIG_SYS_FSL_SEC_ADDR + 0x1034 | |
75 | -#define CAAM_ORSFR0 CONFIG_SYS_FSL_SEC_ADDR + 0x103c | |
76 | -#define CAAM_JRSTAR0 CONFIG_SYS_FSL_SEC_ADDR + 0x1044 | |
77 | -#define CAAM_JRINTR0 CONFIG_SYS_FSL_SEC_ADDR + 0x104c | |
78 | -#define CAAM_JRCFGR0_MS CONFIG_SYS_FSL_SEC_ADDR + 0x1050 | |
79 | -#define CAAM_JRCFGR0_LS CONFIG_SYS_FSL_SEC_ADDR + 0x1054 | |
80 | -#define CAAM_IRRIR0 CONFIG_SYS_FSL_SEC_ADDR + 0x105c | |
81 | -#define CAAM_ORWIR0 CONFIG_SYS_FSL_SEC_ADDR + 0x1064 | |
82 | -#define CAAM_JRCR0 CONFIG_SYS_FSL_SEC_ADDR + 0x106c | |
83 | -#define CAAM_SMCJR0 CONFIG_SYS_FSL_SEC_ADDR + 0x10f4 | |
84 | -#define CAAM_SMCSJR0 CONFIG_SYS_FSL_SEC_ADDR + 0x10fc | |
83 | +#define CAAM_IRBAR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1004) | |
84 | +#define CAAM_IRSR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x100c) | |
85 | +#define CAAM_IRSAR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1014) | |
86 | +#define CAAM_IRJAR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x101c) | |
87 | +#define CAAM_ORBAR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1024) | |
88 | +#define CAAM_ORSR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x102c) | |
89 | +#define CAAM_ORJRR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1034) | |
90 | +#define CAAM_ORSFR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x103c) | |
91 | +#define CAAM_JRSTAR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1044) | |
92 | +#define CAAM_JRINTR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x104c) | |
93 | +#define CAAM_JRCFGR0_MS (CONFIG_SYS_FSL_SEC_ADDR + 0x1050) | |
94 | +#define CAAM_JRCFGR0_LS (CONFIG_SYS_FSL_SEC_ADDR + 0x1054) | |
95 | +#define CAAM_IRRIR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x105c) | |
96 | +#define CAAM_ORWIR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1064) | |
97 | +#define CAAM_JRCR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x106c) | |
98 | +#define CAAM_SMCJR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x10f4) | |
99 | +#define CAAM_SMCSJR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x10fc) | |
85 | 100 | #define CAAM_SMAPJR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x1104 + y*16) |
86 | 101 | #define CAAM_SMAG2JR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x1108 + y*16) |
87 | 102 | #define CAAM_SMAG1JR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x110C + y*16) |
88 | -#define CAAM_SMAPJR0_PRTN1 CONFIG_SYS_FSL_SEC_ADDR + 0x1114 | |
89 | -#define CAAM_SMAG2JR0_PRTN1 CONFIG_SYS_FSL_SEC_ADDR + 0x1118 | |
90 | -#define CAAM_SMAG1JR0_PRTN1 CONFIG_SYS_FSL_SEC_ADDR + 0x111c | |
91 | -#define CAAM_SMPO CONFIG_SYS_FSL_SEC_ADDR + 0x1fbc | |
103 | +#define CAAM_SMAPJR0_PRTN1 (CONFIG_SYS_FSL_SEC_ADDR + 0x1114) | |
104 | +#define CAAM_SMAG2JR0_PRTN1 (CONFIG_SYS_FSL_SEC_ADDR + 0x1118) | |
105 | +#define CAAM_SMAG1JR0_PRTN1 (CONFIG_SYS_FSL_SEC_ADDR + 0x111c) | |
106 | +#define CAAM_SMPO (CONFIG_SYS_FSL_SEC_ADDR + 0x1fbc) | |
92 | 107 | |
93 | -#define JRCFG_LS_IMSK 0x00000001 /* Interrupt Mask */ | |
94 | -#define JR_MID 2 /* Matches ROM configuration */ | |
95 | -#define KS_G1 (1 << JR_MID) /* CAAM only */ | |
96 | -#define PERM 0x0000B008 /* Clear on release, | |
97 | - * lock SMAP | |
98 | - * lock SMAG | |
99 | - * group 1 Blob | |
100 | - */ | |
108 | +#define DESC_MAX_SIZE (0x40) /* Descriptor max size */ | |
109 | +#define JRCFG_LS_IMSK (0x01) /* Interrupt Mask */ | |
110 | +#define JR_MID (0x02) /* Matches ROM configuration */ | |
111 | +#define KS_G1 BIT(JR_MID) /* CAAM only */ | |
112 | +#define PERM (0x0000B008) /* Clear on release, lock SMAP, | |
113 | + * lock SMAG and group 1 Blob | |
114 | + */ | |
101 | 115 | |
102 | -#define CMD_PAGE_ALLOC 0x1 | |
103 | -#define CMD_PAGE_DEALLOC 0x2 | |
104 | -#define CMD_PART_DEALLOC 0x3 | |
105 | -#define CMD_INQUIRY 0x5 | |
116 | +#define CMD_PAGE_ALLOC (0x1) | |
117 | +#define CMD_PAGE_DEALLOC (0x2) | |
118 | +#define CMD_PART_DEALLOC (0x3) | |
119 | +#define CMD_INQUIRY (0x5) | |
106 | 120 | #define PAGE(x) (x << 16) |
107 | 121 | #define PARTITION(x) (x << 8) |
108 | 122 | |
109 | 123 | |
110 | 124 | |
111 | 125 | |
112 | 126 | |
113 | 127 | |
114 | 128 | |
... | ... | @@ -111,28 +125,56 @@ |
111 | 125 | #define CMD_COMPLETE (3 << 14) |
112 | 126 | |
113 | 127 | #define SMCSJR_PO (3 << 6) |
114 | -#define PAGE_AVAILABLE 0 | |
128 | +#define PAGE_AVAILABLE (0) | |
115 | 129 | #define PAGE_OWNED (3 << 6) |
116 | 130 | |
117 | 131 | #define PARTITION_OWNER(x) (0x3 << (x*2)) |
118 | 132 | |
119 | -#define CAAM_BUSY_MASK 0x00000001 /* BUSY from status reg */ | |
120 | -#define CAAM_IDLE_MASK 0x00000002 /* IDLE from status reg */ | |
133 | +#define CAAM_BUSY_MASK (0x00000001) /* BUSY from status reg */ | |
134 | +#define CAAM_IDLE_MASK (0x00000002) /* IDLE from status reg */ | |
135 | +#define CAAM_MCFGR_SWRST BIT(31) /* CAAM SW reset */ | |
136 | +#define CAAM_MCFGR_DMARST BIT(28) /* CAAM DMA reset */ | |
121 | 137 | |
122 | -#define JOB_RING_ENTRIES 1 | |
138 | +#define JOB_RING_ENTRIES (1) | |
123 | 139 | #define JOB_RING_STS (0xF << 28) |
124 | 140 | |
125 | 141 | /** OSC_DIV in RNG trim fuses */ |
126 | -#define RNG_TRIM_OSC_DIV 0 | |
142 | +#define RNG_TRIM_OSC_DIV (0) | |
127 | 143 | /** ENT_DLY multiplier in RNG trim fuses */ |
128 | -//#define RNG_TRIM_ENT_DLY 200*4 | |
129 | -#define RNG_TRIM_ENT_DLY 3200 | |
144 | +#define TRNG_SDCTL_ENT_DLY_MIN (3200) | |
145 | +#define TRNG_SDCTL_ENT_DLY_MAX (4800) | |
130 | 146 | |
131 | -#define RTMCTL_PGM (1 << 16) | |
132 | -#define RTMCTL_ERR (1 << 12) | |
133 | -#define RDSTA_IF0 1 | |
134 | -#define RDSTA_SKVN (1 << 30) | |
147 | +#define RTMCTL_PGM BIT(16) | |
148 | +#define RTMCTL_ERR BIT(12) | |
149 | +#define RTMCTL_RST BIT(6) | |
150 | +#define RDSTA_IF0 (1) | |
151 | +#define RDSTA_IF1 (2) | |
152 | +#define RDSTA_SKVN BIT(30) | |
153 | +#define JRCR_RESET (1) | |
154 | +#define RTMCTL_FCT_FAIL BIT(8) | |
135 | 155 | |
156 | +#define BS_TRNG_ENT_DLY (16) | |
157 | +#define BM_TRNG_ENT_DLY (0xffff << BS_TRNG_ENT_DLY) | |
158 | +#define BM_TRNG_SAMP_MODE (3) | |
159 | +#define TRNG_SAMP_MODE_RAW_ES_SC (1) | |
160 | +#define BS_JRINTR_HALT (2) | |
161 | +#define BM_JRINTR_HALT (0x3 << BS_JRINTR_HALT) | |
162 | +#define JRINTR_HALT_ONGOING (0x1 << BS_JRINTR_HALT) | |
163 | +#define JRINTR_HALT_DONE (0x2 << BS_JRINTR_HALT) | |
164 | +#define JRINTR_JRI (0x1) | |
165 | +#define BS_JRCFGR_LS_ICTT (16) | |
166 | +#define BM_JRCFGR_LS_ICTT (0xFFFF << BS_JRCFGR_LS_ICTT) | |
167 | +#define BS_JRCFGR_LS_ICDCT (8) | |
168 | +#define BM_JRCFGR_LS_ICDCT (0xFF << BS_JRCFGR_LS_ICDCT) | |
169 | +#define BS_JRCFGR_LS_ICEN (1) | |
170 | +#define BM_JRCFGR_LS_ICEN (0x1 << BS_JRCFGR_LS_ICEN) | |
171 | +#define BS_JRCFGR_LS_IMSK (0) | |
172 | +#define BM_JRCFGR_LS_IMSK (0x1 << BS_JRCFGR_LS_IMSK) | |
173 | +#define BS_CHAVID_LS_RNGVID (16) | |
174 | +#define BM_CHAVID_LS_RNGVID (0xF << BS_CHAVID_LS_RNGVID) | |
175 | +#define BS_MCFGR_WDE (30) | |
176 | +#define BM_MCFGR_WDE (0x1 << BS_MCFGR_WDE) | |
177 | + | |
136 | 178 | typedef enum { |
137 | 179 | PAGE_0, |
138 | 180 | PAGE_1, |
139 | 181 | |
140 | 182 | |
141 | 183 | |
142 | 184 | |
143 | 185 | |
144 | 186 | |
145 | 187 | |
146 | 188 | |
147 | 189 | |
148 | 190 | |
149 | 191 | |
... | ... | @@ -151,252 +193,64 @@ |
151 | 193 | PARTITION_7, |
152 | 194 | } partition_num_e; |
153 | 195 | |
154 | -/***************************************** | |
155 | - *----- Blob decapsulate descriptor -----* | |
156 | - *****************************************/ | |
157 | -/* 1. Header | |
158 | - * | |
159 | - * 1011 0000 1000 0000 0000 0000 0000 1001 | |
160 | - * |||| | |||| | |
161 | - * ++++-+-- Header ++++-- 9 words in descriptor | |
162 | - */ | |
163 | -#define DECAP_BLOB_DESC1 0xB0800009 | |
164 | 196 | |
165 | -/* 2. Load command KEY 2 immediate | |
166 | - * | |
167 | - * 0001 0100 1100 0000 0000 1100 0000 1000 | |
168 | - * |||| ||| |||| |||| |||| |||| |||| |||| | |
169 | - * |||| ||| |||| |||| |||| |||| ++++-++++-- Length | |
170 | - * |||| ||| |||| |||| ++++-++++-- Offset | |
171 | - * |||| ||| |+++-++++-- DST (Destination Register) Key2 | |
172 | - * |||| ||| +-- IMM (Immediate flag) | |
173 | - * |||| |++-- class 2 | |
174 | - * ++++-+-- Load command | |
197 | +/* | |
198 | + * Local defines | |
175 | 199 | */ |
176 | -#define DECAP_BLOB_DESC2 0x14C00C08 | |
200 | +/* arm v7 need 64 align */ | |
201 | +#define ALIGN_MASK ~(ARCH_DMA_MINALIGN - 1) | |
202 | +/* caam dma and pointer conversion for arm and arm64 architectures */ | |
203 | +#ifdef CONFIG_IMX_CONFIG | |
204 | + #define PTR2CAAMDMA(x) (u32)((uintptr_t)(x) & 0xffffffff) | |
205 | + #define CAAMDMA2PTR(x) (uintptr_t)((x) & 0xffffffff) | |
206 | +#else | |
207 | + #define PTR2CAAMDMA(x) (uintptr_t)(x) | |
208 | + #define CAAMDMA2PTR(x) (uintptr_t)(x) | |
209 | +#endif | |
210 | +#define RING_EARLY_INIT (0x01) | |
211 | +#define RING_RELOC_INIT (0x02) | |
177 | 212 | |
178 | -/* 3. 8 bytes for load command above - aad data | |
179 | - * | |
180 | - * 0000 0000 0001 0000 0101 0101 0110 0110 | |
181 | - * |||| |||| |||| |||| |||| |||| |||| |||| | |
182 | - * |||| |||| |||| |||| |||| |||| ++++-++++-- CCM Mode | |
183 | - * |||| |||| |||| |||| ++++-++++-- AES | |
184 | - * |||| |||| ++++-++++-- Length | |
185 | - * ++++-++++-- Flag | |
186 | - */ | |
187 | -#define DECAP_BLOB_DESC3 0x00105566 | |
188 | -#define DECAP_BLOB_DESC4 0x00000000 | |
213 | +#define CAAM_HDR_CTYPE (0x16u << 27) | |
214 | +#define CAAM_HDR_ONE BIT(23) | |
215 | +#define CAAM_HDR_START_INDEX(x) (((x) & 0x3F) << 16) | |
216 | +#define CAAM_HDR_DESCLEN(x) ((x) & 0x3F) | |
217 | +#define CAAM_PROTOP_CTYPE (0x10u << 27) | |
189 | 218 | |
190 | -/* 5. SEQ In Ptr | |
191 | - * | |
192 | - * 1111 0000 0000 0000 0000 0000 0100 0000 | |
193 | - * |||| | |||| |||| |||| |||| | |
194 | - * |||| | ++++-++++-++++-++++-- Length in bytes (64) | |
195 | - * ++++-+-- Seq In Ptr | |
196 | - */ | |
197 | -#define DECAP_BLOB_DESC5 0xF0000400 | |
198 | -//#define DECAP_BLOB_DESC5 0xF0000040 | |
219 | +/* State Handle */ | |
220 | +#define BS_ALGO_RNG_SH (4) | |
221 | +#define BM_ALGO_RNG_SH (0x3 << BS_ALGO_RNG_SH) | |
222 | +#define ALGO_RNG_SH(id) (((id) << BS_ALGO_RNG_SH) & BM_ALGO_RNG_SH) | |
199 | 223 | |
200 | -/* 6. Pointer for above SEQ In ptr command */ | |
201 | -/* Address is provided during run time */ | |
202 | -#define DECAP_BLOB_DESC6 0x00000000 | |
224 | +/* Secure Key */ | |
225 | +#define BS_ALGO_RNG_SK (12) | |
226 | +#define BM_ALGO_RNG_SK BIT(BS_ALGO_RNG_SK) | |
203 | 227 | |
204 | -/* 7. SEQ Out Ptr | |
205 | - * | |
206 | - * 1111 1000 0000 0000 0000 0000 0001 0000 | |
207 | - * |||| | |||| |||| |||| |||| | |
208 | - * |||| | ++++-++++-++++-++++-- Length in bytes (16) | |
209 | - * ++++-+-- Seq In Ptr | |
210 | - */ | |
211 | -#define DECAP_BLOB_DESC7 0xF80003d0 | |
212 | -//#define DECAP_BLOB_DESC7 0xF8000010 | |
228 | +/* State */ | |
229 | +#define BS_ALGO_RNG_AS (2) | |
230 | +#define BM_ALGO_RNG_AS (0x3 << BS_ALGO_RNG_AS) | |
231 | +#define ALGO_RNG_GENERATE (0x0 << BS_ALGO_RNG_AS) | |
232 | +#define ALGO_RNG_INSTANTIATE BIT(BS_ALGO_RNG_AS) | |
213 | 233 | |
214 | -/* 8. Pointer for above SEQ Out ptr command */ | |
215 | -/* Address could be changed during run time */ | |
216 | -#define DECAP_BLOB_DESC8 SEC_MEM_PAGE1 | |
234 | +#define CAAM_C1_RNG ((0x50 << 16) | (2 << 24)) | |
217 | 235 | |
218 | -/* 9. Protocol | |
219 | - * | |
220 | - * 1000 0110 0000 1101 0000 0000 0000 1000 | |
221 | - * |||| |||| |||| |||| |||| |||| |||| |||| | |
222 | - * |||| |||| |||| |||| ++++-++++-++++-++++-- Proto Info = sec mem blob | |
223 | - * |||| |||| ++++-++++-- Protocol ID = Blob | |
224 | - * |||| |+++-- Optype - decapsulation protocol | |
225 | - * ++++-+-- Seq In Ptr | |
226 | - */ | |
227 | -#define DECAP_BLOB_DESC9 0x860D0008 | |
236 | +#define BS_JUMP_LOCAL_OFFSET (0) | |
237 | +#define BM_JUMP_LOCAL_OFFSET (0xFF << BS_JUMP_LOCAL_OFFSET) | |
228 | 238 | |
229 | -/***************************************** | |
230 | - *----- Blob encapsulate descriptor -----* | |
231 | - *****************************************/ | |
232 | -/* Blob Header | |
233 | - * | |
234 | - * 1011 0000 1000 0000 0000 0000 0000 1001 | |
235 | - * |||| | | | |
236 | - * ++++-+-- Header +-- 9 words in descriptor | |
237 | - */ | |
238 | -#define ENCAP_BLOB_DESC1 0xB0800009 | |
239 | +#define CAAM_C1_JUMP ((0x14u << 27) | (1 << 25)) | |
240 | +#define CAAM_JUMP_LOCAL (0 << 20) | |
241 | +#define CAAM_JUMP_TST_ALL_COND_TRUE (0 << 16) | |
242 | +#define CAAM_JUMP_OFFSET(off) (((off) << BS_JUMP_LOCAL_OFFSET) \ | |
243 | + & BM_JUMP_LOCAL_OFFSET) | |
239 | 244 | |
240 | -/* 2. Load command KEY 2 immediate | |
241 | - * | |
242 | - * 0001 0100 1100 0000 0000 1100 0000 1000 | |
243 | - * |||| ||| |||| |||| |||| |||| |||| |||| | |
244 | - * |||| ||| |||| |||| |||| |||| ++++-++++-- Length | |
245 | - * |||| ||| |||| |||| ++++-++++-- Offset | |
246 | - * |||| ||| |+++-++++-- DST (Destination Register) Key2 | |
247 | - * |||| ||| +-- IMM (Immediate flag) | |
248 | - * |||| |++-- class 2 | |
249 | - * ++++-+-- Load command | |
250 | - */ | |
251 | -#define ENCAP_BLOB_DESC2 0x14C00C08 | |
245 | +#define CAAM_C0_LOAD_IMM ((0x2 << 27) | (1 << 23)) | |
246 | +#define CAAM_DST_CLEAR_WRITTEN (0x8 << 16) | |
252 | 247 | |
253 | -/* 3. 8 bytes for load command above - aad data | |
254 | - * | |
255 | - * 0000 0000 0001 0000 0101 0101 0110 0110 | |
256 | - * |||| |||| |||| |||| |||| |||| |||| |||| | |
257 | - * |||| |||| |||| |||| |||| |||| ++++-++++-- CCM Mode | |
258 | - * |||| |||| |||| |||| ++++-++++-- AES | |
259 | - * |||| |||| ++++-++++-- Length | |
260 | - * ++++-++++-- Flag | |
261 | - */ | |
262 | -#define ENCAP_BLOB_DESC3 0x00105566 | |
263 | -#define ENCAP_BLOB_DESC4 0x00000000 | |
264 | - | |
265 | -/* 5. SEQ In Ptr | |
266 | - * | |
267 | - * 1111 0000 0000 0000 0000 0000 0001 0000 | |
268 | - * |||| | |||| |||| |||| |||| | |
269 | - * |||| | ++++-++++-++++-++++-- Length in bytes (16) | |
270 | - * ++++-+-- Seq In Ptr | |
271 | - */ | |
272 | -#define ENCAP_BLOB_DESC5 0xF00003d0 | |
273 | -//#define ENCAP_BLOB_DESC5 0xF0000010 | |
274 | - | |
275 | -/* 6. Pointer for above SEQ In ptr command */ | |
276 | -/* Address could be changed during run time */ | |
277 | -#define ENCAP_BLOB_DESC6 SEC_MEM_PAGE1 | |
278 | - | |
279 | -/* 7. SEQ Out Ptr | |
280 | - * | |
281 | - * 1111 1000 0000 0000 0000 0000 0100 0000 | |
282 | - * |||| | |||| |||| |||| |||| | |
283 | - * |||| | ++++-++++-++++-++++-- Length in bytes (64) | |
284 | - * ++++-+-- Seq Out Ptr | |
285 | - */ | |
286 | -#define ENCAP_BLOB_DESC7 0xF8000400 | |
287 | -//#define ENCAP_BLOB_DESC7 0xF8000040 | |
288 | - | |
289 | -/* 8. Pointer for above SEQ Out ptr command */ | |
290 | -/* Address is provided during run time */ | |
291 | -#define ENCAP_BLOB_DESC8 0x00000000 | |
292 | - | |
293 | -/* 9. Protocol | |
294 | - * | |
295 | - * 1000 0111 0000 1101 0000 0000 0000 1000 | |
296 | - * |||| |||| |||| |||| |||| |||| |||| |||| | |
297 | - * |||| |||| |||| |||| ++++-++++-++++-++++-- Proto Info = sec mem blob | |
298 | - * |||| |||| ++++-++++-- Protocol ID = Blob | |
299 | - * |||| |+++-- Optype - encapsulation protocol | |
300 | - * ++++-+-- Seq In Ptr | |
301 | - */ | |
302 | -#define ENCAP_BLOB_DESC9 0x870D0008 | |
303 | - | |
304 | -/**************************************** | |
305 | - *----- Data encryption descriptor -----* | |
306 | - ****************************************/ | |
307 | -/* 1. Header | |
308 | - * | |
309 | - * 1011 0000 1000 0000 0000 0000 0000 1000 | |
310 | - * |||| | | |||| | |
311 | - * ++++-+-- Header +-++++-- 8 words in descriptor | |
312 | - */ | |
313 | -#define ENCRYPT_DESC1 0xB0800008 | |
314 | - | |
315 | -/* 2. Load AES-128 key from secure memory | |
316 | - * | |
317 | - * 0010 0010 0000 0000 0000 0000 0001 0000 | |
318 | - * |||| | | |||| |||| |||| |||| | |
319 | - * |||| | | ++++-++++-++++-++++-- 16 bytes | |
320 | - * |||| | +-- Load FIFO with data for Class 1 CHA | |
321 | - * ++++-+-- FIFO Load | |
322 | - */ | |
323 | -#define ENCRYPT_DESC2 0x02200010 | |
324 | - | |
325 | -/* 3. Pointer to key data in secure memory */ | |
326 | -/* Address is provided during run time */ | |
327 | -#define ENCRYPT_DESC3 0x00000000 | |
328 | - | |
329 | -/* 4. Algorith Operation - Decrypt with ECB mode | |
330 | - * | |
331 | - * 1000 0010 0001 0000 0000 0010 0000 1101 | |
332 | - * |||| |||| |||| |||| |||| |||| |||| |||| | |
333 | - * |||| |||| |||| |||| |||| |||| |||| |||+-- Encrypt | |
334 | - * |||| |||| |||| |||| |||| |||| |||| ++-- Initialize/Finalize | |
335 | - * |||| |||| |||| |||| ---+-++++-++++-- ECB mode | |
336 | - * |||| |||| ++++-++++-- AES | |
337 | - * |||| |+++-- Optype: Class 1 algorithm | |
338 | - * ++++-+-- ALGORITHM OP. | |
339 | - */ | |
340 | -#define ENCRYPT_DESC4 0x8210020D | |
341 | - | |
342 | -/* 5. Load 16 bytes of message data | |
343 | - * | |
344 | - * 0010 0010 0001 0010 0000 0000 0001 0000 | |
345 | - * |||| |||| |||| |||| |||| |||| |||| |||| | |
346 | - * |||| |||| |||| |||| |||| |||| |||| |||| | |
347 | - * |||| |||| |||| |||| |||| |||| |||| |||| | |
348 | - * |||| |||| |||| |||| ++++-++++-++++-++++-- Msg Length = 16Bytes | |
349 | - * |||| |||| ||++-++++-- Input data type: Msg data LC1=1 | |
350 | - * |||| |||| |+-- EXT: No extended length | |
351 | - * |||| |||| +-- IMM: data begins at the location pointed to by the next word | |
352 | - * |||| |||++-SGT/VLF: FIFO Load-Pointer points to actual data | |
353 | - * |||| |++-- Load FIFO with data for Class 1 CHA | |
354 | - * ++++-+-- FIFO Load | |
355 | - */ | |
356 | -#define ENCRYPT_DESC5 0x22120010 | |
357 | - | |
358 | -/* 6. Pointer to plain text test vector message */ | |
359 | -/* Address is provided during run time */ | |
360 | -#define ENCRYPT_DESC6 0x00000000 | |
361 | - | |
362 | -/* 7. FIFO STORE - encrypted result. | |
363 | - * 0110 0000 0011 0000 0000 0000 0001 0000 | |
364 | - * |||| |||| |||| |||| |||| |||| |||| |||| | |
365 | - * |||| |||| |||| |||| ++++-++++-++++-++++-- Length = 16Bytes | |
366 | - * |||| |||| ||++-++++-- Output data type: Msg Data | |
367 | - * |||| |||| |+-- EXT: No extended length | |
368 | - * |||| |||| +-- CONT: No continue | |
369 | - * |||| |||+-- SGT/VLF: Pointer points to actual data | |
370 | - * |||| |++-- AUX: None | |
371 | - * ++++-+-- FIFO Store | |
372 | - */ | |
373 | -#define ENCRYPT_DESC7 0x60300010 | |
374 | - | |
375 | -/* 8. Pointer to ciphered text buffer */ | |
376 | -/* Address is provided during run time */ | |
377 | -#define ENCRYPT_DESC8 0x00000000 | |
378 | - | |
379 | -/********************************************************************* | |
380 | - *----- Descriptor to instantiate RNG in non-deterministic mode -----* | |
381 | - *********************************************************************/ | |
382 | -// Header | |
383 | -#define RNG_INST_DESC1 0xB0800009 | |
384 | -// Class 1 context load for personalization string, 8bytes | |
385 | -#define RNG_INST_DESC2 0x12A00008 | |
386 | -// 8 bytes of personalization string (8-byte UID + zeros) | |
387 | -#define RNG_INST_DESC3 0x01020304 | |
388 | -#define RNG_INST_DESC4 0x05060708 | |
389 | -// Instantiate State Handle 0 using entropy from TRNG | |
390 | -// without prediction resistance | |
391 | -#define RNG_INST_DESC5 0x82500404 | |
392 | -// Wait for Class 1 done | |
393 | -#define RNG_INST_DESC6 0xA2000001 | |
394 | -// Immediate 4 byte load to clear written register | |
395 | -#define RNG_INST_DESC7 0x10880004 | |
396 | -// Clear primary mode bit | |
397 | -#define RNG_INST_DESC8 0x00000001 | |
398 | -// Generate secure keys without prediction resistance | |
399 | -#define RNG_INST_DESC9 0x82501000 | |
248 | +#define RNG_DESC_SH0_SIZE (ARRAY_SIZE(rng_inst_sh0_desc)) | |
249 | +#define RNG_DESC_SH1_SIZE (ARRAY_SIZE(rng_inst_sh1_desc)) | |
250 | +#define RNG_DESC_KEYS_SIZE (ARRAY_SIZE(rng_inst_load_keys)) | |
251 | +#define RNG_DESC_MAX_SIZE (RNG_DESC_SH0_SIZE + \ | |
252 | + RNG_DESC_SH1_SIZE + \ | |
253 | + RNG_DESC_KEYS_SIZE) | |
400 | 254 | |
401 | 255 | #endif /* __CAAM_INTERNAL_H__ */ |
include/fsl_caam.h
1 | 1 | /* |
2 | 2 | * Copyright (c) 2012-2016, Freescale Semiconductor, Inc. |
3 | 3 | * All rights reserved. |
4 | + * Copyright 2018 NXP | |
4 | 5 | * |
5 | 6 | * Redistribution and use in source and binary forms, with or without modification, |
6 | 7 | * are permitted provided that the following conditions are met: |
... | ... | @@ -37,6 +38,7 @@ |
37 | 38 | #define SUCCESS (0) |
38 | 39 | #endif |
39 | 40 | |
41 | +#define ERROR_ANY (-1) | |
40 | 42 | #define ERROR_IN_PAGE_ALLOC (1) |
41 | 43 | |
42 | 44 |
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