Commit 1f4edad6618ac1473b3123ec5a094f6ff9b8af2c
Committed by
Lokesh Vutla
1 parent
40e76546f3
Exists in
v2017.01-smarct4x
and in
2 other branches
davinci: omapl138_lcdk: fix tXSNR DDR2 timing value
As per the datasheet[1] available for DDR2 part on board the OMAP-L138 LCDK, the tXSNR (exit self refresh to a non-read command) is 137.5 ns. This corresponds to a value of 20 to be written to T_XSNR register field of OMAP-L138's DDR configuration. The DDR2 is at 150 MHz. Fix this. The correct value also appears on the initialization scripts (called CCS GEL files) available on TI's wiki pages[2] [1] http://www.samsung.com/global/business/semiconductor/file/product/ds_k4t1gxx4qf_rev12-0.pdf [2] http://processors.wiki.ti.com/index.php/L138/C6748_Development_Kit_(LCDK)#CCS_XML_.26_GEL_Files Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Showing 1 changed file with 1 additions and 1 deletions Side-by-side Diff
include/configs/omapl138_lcdk.h
... | ... | @@ -111,7 +111,7 @@ |
111 | 111 | (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ |
112 | 112 | (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ |
113 | 113 | (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ |
114 | - (10 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ | |
114 | + (20 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ | |
115 | 115 | (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ |
116 | 116 | (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ |
117 | 117 | (2 << DV_DDR_SDTMR2_CKE_SHIFT)) |