Eric Lee / smarc-uboot

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Commit 1f6e9bd2a730e23c69ec08537d3dd4c1731db7dc

Authored by Jagan Teki
Committed by Stefano Babic
1 parent a1797beed2
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

i.MX6Q: icore: Add SPL_OF_CONTROL support 

Add OF_CONTROL support for SPL code.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

Showing 9 changed files with 31 additions and 187 deletions Side-by-side Diff

arch/arm/dts/imx6qdl-icore-rqs.dtsi
Diff comments   View file @ 1f6e9bd
... ... @@ -100,6 +100,7 @@
100 100 };
101 101  
102 102 &usdhc3 {
  103 + u-boot,dm-spl;
103 104 pinctrl-names = "default";
104 105 pinctrl-0 = <&pinctrl_usdhc3>;
105 106 cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
... ... @@ -165,6 +166,7 @@
165 166 };
166 167  
167 168 pinctrl_usdhc3: usdhc3grp {
  169 + u-boot,dm-spl;
168 170 fsl,pins = <
169 171 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17070
170 172 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10070
arch/arm/dts/imx6qdl-icore.dtsi
Diff comments   View file @ 1f6e9bd
... ... @@ -118,6 +118,7 @@
118 118 };
119 119  
120 120 &usdhc1 {
  121 + u-boot,dm-spl;
121 122 pinctrl-names = "default";
122 123 pinctrl-0 = <&pinctrl_usdhc1>;
123 124 cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
... ... @@ -208,6 +209,7 @@
208 209 };
209 210  
210 211 pinctrl_usdhc1: usdhc1grp {
  212 + u-boot,dm-spl;
211 213 fsl,pins = <
212 214 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17070
213 215 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10070
arch/arm/dts/imx6qdl.dtsi
Diff comments   View file @ 1f6e9bd
... ... @@ -77,6 +77,7 @@
77 77 compatible = "simple-bus";
78 78 interrupt-parent = <&gpc>;
79 79 ranges;
  80 + u-boot,dm-spl;
80 81  
81 82 dma_apbh: dma-apbh@00110000 {
82 83 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
... ... @@ -225,6 +226,7 @@
225 226 #size-cells = <1>;
226 227 reg = <0x02000000 0x100000>;
227 228 ranges;
  229 + u-boot,dm-spl;
228 230  
229 231 spba-bus@02000000 {
230 232 compatible = "fsl,spba-bus", "simple-bus";
... ... @@ -516,6 +518,7 @@
516 518 #gpio-cells = <2>;
517 519 interrupt-controller;
518 520 #interrupt-cells = <2>;
  521 + u-boot,dm-spl;
519 522 };
520 523  
521 524 gpio2: gpio@020a0000 {
... ... @@ -805,6 +808,7 @@
805 808 iomuxc: iomuxc@020e0000 {
806 809 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
807 810 reg = <0x020e0000 0x4000>;
  811 + u-boot,dm-spl;
808 812 };
809 813  
810 814 ldb: ldb@020e0008 {
... ... @@ -889,6 +893,7 @@
889 893 #size-cells = <1>;
890 894 reg = <0x02100000 0x100000>;
891 895 ranges;
  896 + u-boot,dm-spl;
892 897  
893 898 crypto: caam@2100000 {
894 899 compatible = "fsl,sec-v4.0";
arch/arm/mach-imx/mx6/Kconfig
Diff comments   View file @ 1f6e9bd
... ... @@ -219,6 +219,10 @@
219 219 select DM_THERMAL
220 220 select SUPPORT_SPL
221 221 select SPL_LOAD_FIT
  222 + select SPL_DM if SPL
  223 + select SPL_OF_CONTROL if SPL
  224 + select SPL_SEPARATE_BSS if SPL
  225 + select SPL_PINCTRL if SPL
222 226  
223 227 config TARGET_MX6Q_ICORE_RQS
224 228 bool "Support Engicam i.Core RQS"
... ... @@ -234,6 +238,10 @@
234 238 select DM_THERMAL
235 239 select SUPPORT_SPL
236 240 select SPL_LOAD_FIT
  241 + select SPL_DM if SPL
  242 + select SPL_OF_CONTROL if SPL
  243 + select SPL_SEPARATE_BSS if SPL
  244 + select SPL_PINCTRL if SPL
237 245  
238 246 config TARGET_MX6SABREAUTO
239 247 bool "mx6sabreauto"
board/engicam/icorem6/icorem6.c
Diff comments   View file @ 1f6e9bd
... ... @@ -7,7 +7,6 @@
7 7 */
8 8  
9 9 #include <common.h>
10   -#include <mmc.h>
11 10  
12 11 #include <asm/io.h>
13 12 #include <asm/gpio.h>
... ... @@ -191,78 +190,4 @@
191 190 writel(reg, &iomux->gpr[3]);
192 191 }
193 192 #endif /* CONFIG_VIDEO_IPUV3 */
194   -
195   -#ifdef CONFIG_SPL_BUILD
196   -/* MMC board initialization is needed till adding DM support in SPL */
197   -#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
198   -#include <mmc.h>
199   -#include <fsl_esdhc.h>
200   -
201   -#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
202   - PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
203   - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
204   -
205   -static iomux_v3_cfg_t const usdhc1_pads[] = {
206   - IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
207   - IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
208   - IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
209   - IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
210   - IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
211   - IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
212   - IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
213   -};
214   -
215   -#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
216   -
217   -struct fsl_esdhc_cfg usdhc_cfg[1] = {
218   - {USDHC1_BASE_ADDR, 0, 4},
219   -};
220   -
221   -int board_mmc_getcd(struct mmc *mmc)
222   -{
223   - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
224   - int ret = 0;
225   -
226   - switch (cfg->esdhc_base) {
227   - case USDHC1_BASE_ADDR:
228   - ret = !gpio_get_value(USDHC1_CD_GPIO);
229   - break;
230   - }
231   -
232   - return ret;
233   -}
234   -
235   -int board_mmc_init(bd_t *bis)
236   -{
237   - int i, ret;
238   -
239   - /*
240   - * According to the board_mmc_init() the following map is done:
241   - * (U-boot device node) (Physical Port)
242   - * mmc0 USDHC1
243   - */
244   - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
245   - switch (i) {
246   - case 0:
247   - SETUP_IOMUX_PADS(usdhc1_pads);
248   - gpio_direction_input(USDHC1_CD_GPIO);
249   - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
250   - break;
251   - default:
252   - printf("Warning - USDHC%d controller not supporting\n",
253   - i + 1);
254   - return 0;
255   - }
256   -
257   - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
258   - if (ret) {
259   - printf("Warning: failed to initialize mmc dev %d\n", i);
260   - return ret;
261   - }
262   - }
263   -
264   - return 0;
265   -}
266   -#endif
267   -#endif /* CONFIG_SPL_BUILD */
board/engicam/icorem6_rqs/icorem6_rqs.c
Diff comments   View file @ 1f6e9bd
... ... @@ -6,22 +6,8 @@
6 6 * SPDX-License-Identifier: GPL-2.0+
7 7 */
8 8  
9   -#include <common.h>
10   -#include <mmc.h>
11   -
12   -#include <asm/io.h>
13   -#include <asm/gpio.h>
14   -#include <linux/sizes.h>
15   -
16   -#include <asm/arch/clock.h>
17   -#include <asm/arch/crm_regs.h>
18   -#include <asm/arch/iomux.h>
19   -#include <asm/arch/mx6-pins.h>
20 9 #include <asm/arch/sys_proto.h>
21   -#include <asm/mach-imx/iomux-v3.h>
22 10  
23   -#include "../common/board.h"
24   -
25 11 DECLARE_GLOBAL_DATA_PTR;
26 12  
27 13 #ifdef CONFIG_ENV_IS_IN_MMC
... ... @@ -34,93 +20,6 @@
34 20 #ifdef CONFIG_SPL_BUILD
35 21 #include <spl.h>
36 22  
37   -/* MMC board initialization is needed till adding DM support in SPL */
38   -#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
39   -#include <mmc.h>
40   -#include <fsl_esdhc.h>
41   -
42   -#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
43   - PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
44   - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
45   -
46   -static iomux_v3_cfg_t const usdhc3_pads[] = {
47   - IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
48   - IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
49   - IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
50   - IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
51   - IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
52   - IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
53   -};
54   -
55   -static iomux_v3_cfg_t const usdhc4_pads[] = {
56   - IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
57   - IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
58   - IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
59   - IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
60   - IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
61   - IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
62   - IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
63   - IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
64   - IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
65   - IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
66   -};
67   -
68   -struct fsl_esdhc_cfg usdhc_cfg[2] = {
69   - {USDHC3_BASE_ADDR, 1, 4},
70   - {USDHC4_BASE_ADDR, 1, 8},
71   -};
72   -
73   -int board_mmc_getcd(struct mmc *mmc)
74   -{
75   - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
76   - int ret = 0;
77   -
78   - switch (cfg->esdhc_base) {
79   - case USDHC3_BASE_ADDR:
80   - case USDHC4_BASE_ADDR:
81   - ret = 1;
82   - break;
83   - }
84   -
85   - return ret;
86   -}
87   -
88   -int board_mmc_init(bd_t *bis)
89   -{
90   - int i, ret;
91   -
92   - /*
93   - * According to the board_mmc_init() the following map is done:
94   - * (U-boot device node) (Physical Port)
95   - * mmc0 USDHC3
96   - * mmc1 USDHC4
97   - */
98   - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
99   - switch (i) {
100   - case 0:
101   - SETUP_IOMUX_PADS(usdhc3_pads);
102   - usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
103   - break;
104   - case 1:
105   - SETUP_IOMUX_PADS(usdhc4_pads);
106   - usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
107   - break;
108   - default:
109   - printf("Warning - USDHC%d controller not supporting\n",
110   - i + 1);
111   - return 0;
112   - }
113   -
114   - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
115   - if (ret) {
116   - printf("Warning: failed to initialize mmc dev %d\n", i);
117   - return ret;
118   - }
119   - }
120   -
121   - return 0;
122   -}
123   -
124 23 #ifdef CONFIG_ENV_IS_IN_MMC
125 24 void board_boot_order(u32 *spl_boot_list)
126 25 {
... ... @@ -145,7 +44,6 @@
145 44  
146 45 spl_boot_list[0] = boot_dev;
147 46 }
148   -#endif
149 47 #endif
150 48 #endif /* CONFIG_SPL_BUILD */
configs/imx6qdl_icore_mmc_defconfig
Diff comments   View file @ 1f6e9bd
... ... @@ -48,4 +48,5 @@
48 48 CONFIG_IMX_THERMAL=y
49 49 CONFIG_VIDEO=y
50 50 CONFIG_VIDEO_IPUV3=y
  51 +CONFIG_SYS_MALLOC_F_LEN=0x2000
configs/imx6qdl_icore_rqs_defconfig
Diff comments   View file @ 1f6e9bd
... ... @@ -40,4 +40,5 @@
40 40 CONFIG_PINCTRL=y
41 41 CONFIG_PINCTRL_IMX6=y
42 42 CONFIG_MXC_UART=y
  43 +CONFIG_SYS_MALLOC_F_LEN=0x2000
include/configs/imx6-engicam.h
Diff comments   View file @ 1f6e9bd
... ... @@ -216,16 +216,18 @@
216 216  
217 217 # include "imx6_spl.h"
218 218 # ifdef CONFIG_SPL_BUILD
219   -# if defined(CONFIG_TARGET_MX6Q_ICORE_RQS) || defined(CONFIG_TARGET_MX6UL_ISIOT)
220   -# define CONFIG_SYS_FSL_USDHC_NUM 2
221   -# else
222   -# define CONFIG_SYS_FSL_USDHC_NUM 1
223   -# endif
  219 +# if defined(CONFIG_IMX6UL)
  220 +# if defined(CONFIG_TARGET_MX6UL_ISIOT)
  221 +# define CONFIG_SYS_FSL_USDHC_NUM 2
  222 +# else
  223 +# define CONFIG_SYS_FSL_USDHC_NUM 1
  224 +# endif
224 225  
225   -# define CONFIG_SYS_FSL_ESDHC_ADDR 0
226   -# undef CONFIG_DM_GPIO
227   -# undef CONFIG_DM_MMC
228   -# endif
  226 +# define CONFIG_SYS_FSL_ESDHC_ADDR 0
  227 +# undef CONFIG_DM_GPIO
  228 +# undef CONFIG_DM_MMC
  229 +# endif /* CONFIG_IMX6UL */
  230 +# endif /* CONFIG_SPL_BUILD */
229 231 #endif
230 232  
231 233 #endif /* __IMX6_ENGICAM_CONFIG_H */