arm: mxs: olinuxino: Fine-tune DRAM configuration

Add fine-tuning for the DRAM configuration according to the DRAM chip datasheet. THis configuration applies to both Hynix HY5DU12622DTP and Samsung K5H511538J-D43 . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>

arm: mxs: olinuxino: Fine-tune DRAM configuration
Add fine-tuning for the DRAM configuration according to the DRAM chip datasheet. THis configuration applies to both Hynix HY5DU12622DTP and Samsung K5H511538J-D43 . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
Marek Vasut · Stefano Babic
1 parent ca11db2603
Showing 1 changed file with 30 additions and 0 deletions Side-by-side Diff
board/olimex/mx23_olinuxino/mx23_olinuxino.c
@@ -78,4 +78,34 @@
  
 	return 0;
 }
+
+/* Fine-tune the DRAM configuration. */
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+	/* Enable Auto Precharge. */
+	dram_vals[3] |= 1 << 8;
+	/* Enable Fast Writes. */
+	dram_vals[5] |= 1 << 8;
+	/* tEMRS = 3*tCK */
+	dram_vals[10] &= ~(0x3 << 8);
+	dram_vals[10] |= (0x3 << 8);
+	/* CASLAT = 3*tCK */
+	dram_vals[11] &= ~(0x3 << 0);
+	dram_vals[11] |= (0x3 << 0);
+	/* tCKE = 1*tCK */
+	dram_vals[12] &= ~(0x7 << 0);
+	dram_vals[12] |= (0x1 << 0);
+	/* CASLAT_LIN_GATE = 3*tCK , CASLAT_LIN = 3*tCK, tWTR=2*tCK */
+	dram_vals[13] &= ~((0xf << 16) | (0xf << 24) | (0xf << 0));
+	dram_vals[13] |= (0x6 << 16) | (0x6 << 24) | (0x2 << 0);
+	/* tDAL = 6*tCK */
+	dram_vals[15] &= ~(0xf << 16);
+	dram_vals[15] |= (0x6 << 16);
+	/* tREF = 1040*tCK */
+	dram_vals[26] &= ~0xffff;
+	dram_vals[26] |= 0x0410;
+	/* tRAS_MAX = 9334*tCK */
+	dram_vals[32] &= ~0xffff;
+	dram_vals[32] |= 0x2475;
+}
...	...	@@ -78,4 +78,34 @@
78	78
79	79	return 0;
80	80	}
	81	+
	82	+/* Fine-tune the DRAM configuration. */
	83	+void mxs_adjust_memory_params(uint32_t *dram_vals)
	84	+{
	85	+ /* Enable Auto Precharge. */
	86	+ dram_vals[3] \|= 1 << 8;
	87	+ /* Enable Fast Writes. */
	88	+ dram_vals[5] \|= 1 << 8;
	89	+ /* tEMRS = 3tCK /
	90	+ dram_vals[10] &= ~(0x3 << 8);
	91	+ dram_vals[10] \|= (0x3 << 8);
	92	+ /* CASLAT = 3tCK /
	93	+ dram_vals[11] &= ~(0x3 << 0);
	94	+ dram_vals[11] \|= (0x3 << 0);
	95	+ /* tCKE = 1tCK /
	96	+ dram_vals[12] &= ~(0x7 << 0);
	97	+ dram_vals[12] \|= (0x1 << 0);
	98	+ /* CASLAT_LIN_GATE = 3tCK , CASLAT_LIN = 3tCK, tWTR=2tCK /
	99	+ dram_vals[13] &= ~((0xf << 16) \| (0xf << 24) \| (0xf << 0));
	100	+ dram_vals[13] \|= (0x6 << 16) \| (0x6 << 24) \| (0x2 << 0);
	101	+ /* tDAL = 6tCK /
	102	+ dram_vals[15] &= ~(0xf << 16);
	103	+ dram_vals[15] \|= (0x6 << 16);
	104	+ /* tREF = 1040tCK /
	105	+ dram_vals[26] &= ~0xffff;
	106	+ dram_vals[26] \|= 0x0410;
	107	+ /* tRAS_MAX = 9334tCK /
	108	+ dram_vals[32] &= ~0xffff;
	109	+ dram_vals[32] \|= 0x2475;
	110	+}