Rename common ns16550 constants with UART_ prefix to prevent conflicts

Fix problems introduced in commit 7b5611cdd12ca0cc33f994f0d4a4454788fc3124 [inka4x0: Add hardware diagnosis functions for inka4x0] which redefined MSR_RI which is already used on PowerPC systems. Also eliminate redundant definitions in ps2mult.h. More cleanup will be needed for other redundant occurrences though. Signed-off-by: Detlev Zundel <dzu@denx.de>

Rename common ns16550 constants with UART_ prefix to prevent conflicts
Fix problems introduced in commit 7b5611cdd12ca0cc33f994f0d4a4454788fc3124 [inka4x0: Add hardware diagnosis functions for inka4x0] which redefined MSR_RI which is already used on PowerPC systems. Also eliminate redundant definitions in ps2mult.h. More cleanup will be needed for other redundant occurrences though. Signed-off-by: Detlev Zundel <dzu@denx.de>
Detlev Zundel · Wolfgang Denk
1 parent 74de7aefd7
Showing 6 changed files with 139 additions and 182 deletions Side-by-side Diff
board/inka4x0/inkadiag.c
board/linkstation/avr.c
drivers/input/ps2ser.c
drivers/serial/ns16550.c
include/ns16550.h
include/ps2mult.h
@@ -280,48 +280,48 @@
 	if ((num >= 0) && (num <= 7)) {
 		if (mode & 1) {
 			/* turn on 'loopback' mode */
-			out_8(&uart->mcr, MCR_LOOP);
+			out_8(&uart->mcr, UART_MCR_LOOP);
 		} else {
 			/*
 			 * establish the UART's operational parameters
 			 * set DLAB=1, so rbr accesses DLL
 			 */
-			out_8(&uart->lcr, LCR_DLAB);
+			out_8(&uart->lcr, UART_LCR_DLAB);
 			/* set baudrate */
 			out_8(&uart->rbr, combrd);
 			/* set data-format: 8-N-1 */
-			out_8(&uart->lcr, LCR_WLS_8);
+			out_8(&uart->lcr, UART_LCR_WLS_8);
 		}
  
 		if (mode & 2) {
 			/* set request to send */
-			out_8(&uart->mcr, MCR_RTS);
+			out_8(&uart->mcr, UART_MCR_RTS);
 			udelay(10);
 			/* check clear to send */
-			if ((in_8(&uart->msr) & MSR_CTS) == 0x00)
+			if ((in_8(&uart->msr) & UART_MSR_CTS) == 0x00)
 				return -1;
 		}
 		if (mode & 4) {
 			/* set data terminal ready */
-			out_8(&uart->mcr, MCR_DTR);
+			out_8(&uart->mcr, UART_MCR_DTR);
 			udelay(10);
 			/* check data set ready and carrier detect */
-			if ((in_8(&uart->msr) & (MSR_DSR | MSR_DCD))
-			    != (MSR_DSR | MSR_DCD))
+			if ((in_8(&uart->msr) & (UART_MSR_DSR | UART_MSR_DCD))
+			    != (UART_MSR_DSR | UART_MSR_DCD))
 				return -1;
 		}
  
 		/* write each message-character, read it back, and display it */
 		for (i = 0, len = strlen(argv[3]); i < len; ++i) {
 			j = 0;
-			while ((in_8(&uart->lsr) & LSR_THRE) ==	0x00) {
+			while ((in_8(&uart->lsr) & UART_LSR_THRE) ==	0x00) {
 				if (j++ > CONFIG_SYS_HZ)
 					break;
 				udelay(10);
 			}
 			out_8(&uart->rbr, argv[3][i]);
 			j = 0;
-			while ((in_8(&uart->lsr) & LSR_DR) == 0x00) {
+			while ((in_8(&uart->lsr) & UART_LSR_DR) == 0x00) {
 				if (j++ > CONFIG_SYS_HZ)
 					break;
 				udelay(10);
@@ -90,12 +90,12 @@
 	 */
 	AVR_port->lcr = 0x00;
 	AVR_port->ier = 0x00;
-	AVR_port->lcr = LCR_BKSE;
+	AVR_port->lcr = UART_LCR_BKSE;
 	AVR_port->dll = clock_divisor & 0xff;
 	AVR_port->dlm = (clock_divisor >> 8) & 0xff;
-	AVR_port->lcr = LCR_WLS_8 | LCR_PEN | LCR_EPS;
+	AVR_port->lcr = UART_LCR_WLS_8 | UART_LCR_PEN | UART_LCR_EPS;
 	AVR_port->mcr = 0x00;
-	AVR_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;
+	AVR_port->fcr = UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR;
  
 	miconCntl_DisWDT();
  
 /***********************************************************************
  *
- * (C) Copyright 2004
+ * (C) Copyright 2004-2009
  * DENX Software Engineering
  * Wolfgang Denk, wd@denx.de
  * All rights reserved.
  
@@ -18,9 +18,11 @@
 #include <asm/io.h>
 #include <asm/atomic.h>
 #include <ps2mult.h>
-#if defined(CONFIG_SYS_NS16550) || defined(CONFIG_MPC85xx)
-#include <ns16550.h>
+/* This is needed for ns16550.h */
+#ifndef CONFIG_SYS_NS16550_REG_SIZE
+#define CONFIG_SYS_NS16550_REG_SIZE 1
 #endif
+#include <ns16550.h>
  
 DECLARE_GLOBAL_DATA_PTR;
  
  
@@ -128,12 +130,12 @@
 	NS16550_t com_port = (NS16550_t)COM_BASE;
  
 	com_port->ier = 0x00;
-	com_port->lcr = LCR_BKSE | LCR_8N1;
+	com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1;
 	com_port->dll = (CONFIG_SYS_NS16550_CLK / 16 / PS2SER_BAUD) & 0xff;
 	com_port->dlm = ((CONFIG_SYS_NS16550_CLK / 16 / PS2SER_BAUD) >> 8) & 0xff;
-	com_port->lcr = LCR_8N1;
-	com_port->mcr = (MCR_DTR | MCR_RTS);
-	com_port->fcr = (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR);
+	com_port->lcr = UART_LCR_8N1;
+	com_port->mcr = (UART_MCR_DTR | UART_MCR_RTS);
+	com_port->fcr = (UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR);
  
 	return (0);
 }
@@ -202,7 +204,7 @@
 	psc->psc_buffer_8 = chr;
 #elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
       defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
-	while ((com_port->lsr & LSR_THRE) == 0);
+	while ((com_port->lsr & UART_LSR_THRE) == 0);
 	com_port->thr = chr;
 #else
 	while (!(ps2ser_in(UART_LSR) & UART_LSR_THRE));
@@ -227,7 +229,7 @@
 	}
 #elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
       defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
-	if (com_port->lsr & LSR_DR) {
+	if (com_port->lsr & UART_LSR_DR) {
 		res = com_port->rbr;
 	}
 #else
@@ -315,7 +317,7 @@
 	} while (status & PSC_SR_RXRDY);
 #elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
       defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
-	} while (status & LSR_DR);
+	} while (status & UART_LSR_DR);
 #else
 	} while (status & UART_IIR_RDI);
 #endif
@@ -7,9 +7,12 @@
 #include <config.h>
 #include <ns16550.h>
  
-#define LCRVAL LCR_8N1					/* 8 data, 1 stop, no parity */
-#define MCRVAL (MCR_DTR | MCR_RTS)			/* RTS/DTR */
-#define FCRVAL (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR)	/* Clear & enable FIFOs */
+#define UART_LCRVAL UART_LCR_8N1		/* 8 data, 1 stop, no parity */
+#define UART_MCRVAL (UART_MCR_DTR | \
+		     UART_MCR_RTS)		/* RTS/DTR */
+#define UART_FCRVAL (UART_FCR_FIFO_EN |	\
+		     UART_FCR_RXSR |	\
+		     UART_FCR_TXSR)		/* Clear & enable FIFOs */
  
 void NS16550_init (NS16550_t com_port, int baud_divisor)
 {
  
  
@@ -17,16 +20,16 @@
 #ifdef CONFIG_OMAP
 	com_port->mdr1 = 0x7;	/* mode select reset TL16C750*/
 #endif
-	com_port->lcr = LCR_BKSE | LCRVAL;
+	com_port->lcr = UART_LCR_BKSE | UART_LCRVAL;
 	com_port->dll = 0;
 	com_port->dlm = 0;
-	com_port->lcr = LCRVAL;
-	com_port->mcr = MCRVAL;
-	com_port->fcr = FCRVAL;
-	com_port->lcr = LCR_BKSE | LCRVAL;
+	com_port->lcr = UART_LCRVAL;
+	com_port->mcr = UART_MCRVAL;
+	com_port->fcr = UART_FCRVAL;
+	com_port->lcr = UART_LCR_BKSE | UART_LCRVAL;
 	com_port->dll = baud_divisor & 0xff;
 	com_port->dlm = (baud_divisor >> 8) & 0xff;
-	com_port->lcr = LCRVAL;
+	com_port->lcr = UART_LCRVAL;
 #if defined(CONFIG_OMAP)
 #if defined(CONFIG_APTIX)
 	com_port->mdr1 = 3;	/* /13 mode so Aptix 6MHz can hit 115200 */
  
  
  
  
@@ -40,29 +43,29 @@
 void NS16550_reinit (NS16550_t com_port, int baud_divisor)
 {
 	com_port->ier = 0x00;
-	com_port->lcr = LCR_BKSE | LCRVAL;
+	com_port->lcr = UART_LCR_BKSE | UART_LCRVAL;
 	com_port->dll = 0;
 	com_port->dlm = 0;
-	com_port->lcr = LCRVAL;
-	com_port->mcr = MCRVAL;
-	com_port->fcr = FCRVAL;
-	com_port->lcr = LCR_BKSE;
+	com_port->lcr = UART_LCRVAL;
+	com_port->mcr = UART_MCRVAL;
+	com_port->fcr = UART_FCRVAL;
+	com_port->lcr = UART_LCR_BKSE;
 	com_port->dll = baud_divisor & 0xff;
 	com_port->dlm = (baud_divisor >> 8) & 0xff;
-	com_port->lcr = LCRVAL;
+	com_port->lcr = UART_LCRVAL;
 }
 #endif /* CONFIG_NS16550_MIN_FUNCTIONS */
  
 void NS16550_putc (NS16550_t com_port, char c)
 {
-	while ((com_port->lsr & LSR_THRE) == 0);
+	while ((com_port->lsr & UART_LSR_THRE) == 0);
 	com_port->thr = c;
 }
  
 #ifndef CONFIG_NS16550_MIN_FUNCTIONS
 char NS16550_getc (NS16550_t com_port)
 {
-	while ((com_port->lsr & LSR_DR) == 0) {
+	while ((com_port->lsr & UART_LSR_DR) == 0) {
 #ifdef CONFIG_USB_TTY
 		extern void usbtty_poll(void);
 		usbtty_poll();
@@ -73,7 +76,7 @@
  
 int NS16550_tstc (NS16550_t com_port)
 {
-	return ((com_port->lsr & LSR_DR) != 0);
+	return ((com_port->lsr & UART_LSR_DR) != 0);
 }
  
 #endif /* CONFIG_NS16550_MIN_FUNCTIONS */
 /*
  * NS16550 Serial Port
  * originally from linux source (arch/ppc/boot/ns16550.h)
+ *
+ * Cleanup and unification
+ * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH
+ *
  * modified slightly to
  * have addresses as offsets from CONFIG_SYS_ISA_BASE
  * added a few more definitions
  
  
  
  
  
  
  
@@ -115,53 +119,100 @@
  
 typedef volatile struct NS16550 *NS16550_t;
  
-#define FCR_FIFO_EN     0x01		/* Fifo enable */
-#define FCR_RXSR        0x02		/* Receiver soft reset */
-#define FCR_TXSR        0x04		/* Transmitter soft reset */
+/*
+ * These are the definitions for the FIFO Control Register
+ */
+#define UART_FCR_FIFO_EN 	0x01 /* Fifo enable */
+#define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
+#define UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
+#define UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
+#define UART_FCR_TRIGGER_MASK	0xC0 /* Mask for the FIFO trigger range */
+#define UART_FCR_TRIGGER_1	0x00 /* Mask for trigger set at 1 */
+#define UART_FCR_TRIGGER_4	0x40 /* Mask for trigger set at 4 */
+#define UART_FCR_TRIGGER_8	0x80 /* Mask for trigger set at 8 */
+#define UART_FCR_TRIGGER_14	0xC0 /* Mask for trigger set at 14 */
  
-#define MCR_DTR         0x01
-#define MCR_RTS         0x02
-#define MCR_DMA_EN      0x04
-#define MCR_TX_DFR      0x08
-#define MCR_LOOP	0x10		/* Enable loopback test mode */
+#define UART_FCR_RXSR		0x02 /* Receiver soft reset */
+#define UART_FCR_TXSR		0x04 /* Transmitter soft reset */
  
-#define LCR_WLS_MSK	0x03		/* character length select mask */
-#define LCR_WLS_5	0x00		/* 5 bit character length */
-#define LCR_WLS_6	0x01		/* 6 bit character length */
-#define LCR_WLS_7	0x02		/* 7 bit character length */
-#define LCR_WLS_8	0x03		/* 8 bit character length */
-#define LCR_STB		0x04		/* Number of stop Bits, off = 1, on = 1.5 or 2) */
-#define LCR_PEN		0x08		/* Parity eneble */
-#define LCR_EPS		0x10		/* Even Parity Select */
-#define LCR_STKP	0x20		/* Stick Parity */
-#define LCR_SBRK	0x40		/* Set Break */
-#define LCR_BKSE	0x80		/* Bank select enable */
-#define LCR_DLAB	0x80		/* Divisor latch access bit */
+/*
+ * These are the definitions for the Modem Control Register
+ */
+#define UART_MCR_DTR	0x01		/* DTR   */
+#define UART_MCR_RTS	0x02		/* RTS   */
+#define UART_MCR_OUT1	0x04		/* Out 1 */
+#define UART_MCR_OUT2	0x08		/* Out 2 */
+#define UART_MCR_LOOP	0x10		/* Enable loopback test mode */
  
-#define LSR_DR		0x01		/* Data ready */
-#define LSR_OE		0x02		/* Overrun */
-#define LSR_PE		0x04		/* Parity error */
-#define LSR_FE		0x08		/* Framing error */
-#define LSR_BI		0x10		/* Break */
-#define LSR_THRE	0x20		/* Xmit holding register empty */
-#define LSR_TEMT	0x40		/* Xmitter empty */
-#define LSR_ERR		0x80		/* Error */
+#define UART_MCR_DMA_EN	0x04
+#define UART_MCR_TX_DFR	0x08
  
-#define MSR_DCD		0x80		/* Data Carrier Detect */
-#define MSR_RI		0x40		/* Ring Indicator */
-#define MSR_DSR		0x20		/* Data Set Ready */
-#define MSR_CTS		0x10		/* Clear to Send */
-#define MSR_DDCD	0x08		/* Delta DCD */
-#define MSR_TERI	0x04		/* Trailing edge ring indicator */
-#define MSR_DDSR	0x02		/* Delta DSR */
-#define MSR_DCTS	0x01		/* Delta CTS */
+/*
+ * These are the definitions for the Line Control Register
+ *
+ * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
+ * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
+ */
+#define UART_LCR_WLS_MSK 0x03		/* character length select mask */
+#define UART_LCR_WLS_5	0x00		/* 5 bit character length */
+#define UART_LCR_WLS_6	0x01		/* 6 bit character length */
+#define UART_LCR_WLS_7	0x02		/* 7 bit character length */
+#define UART_LCR_WLS_8	0x03		/* 8 bit character length */
+#define UART_LCR_STB	0x04		/* Number of stop Bits, off = 1, on = 1.5 or 2) */
+#define UART_LCR_PEN	0x08		/* Parity eneble */
+#define UART_LCR_EPS	0x10		/* Even Parity Select */
+#define UART_LCR_STKP	0x20		/* Stick Parity */
+#define UART_LCR_SBRK	0x40		/* Set Break */
+#define UART_LCR_BKSE	0x80		/* Bank select enable */
+#define UART_LCR_DLAB	0x80		/* Divisor latch access bit */
  
+/*
+ * These are the definitions for the Line Status Register
+ */
+#define UART_LSR_DR	0x01		/* Data ready */
+#define UART_LSR_OE	0x02		/* Overrun */
+#define UART_LSR_PE	0x04		/* Parity error */
+#define UART_LSR_FE	0x08		/* Framing error */
+#define UART_LSR_BI	0x10		/* Break */
+#define UART_LSR_THRE	0x20		/* Xmit holding register empty */
+#define UART_LSR_TEMT	0x40		/* Xmitter empty */
+#define UART_LSR_ERR	0x80		/* Error */
+
+#define UART_MSR_DCD	0x80		/* Data Carrier Detect */
+#define UART_MSR_RI	0x40		/* Ring Indicator */
+#define UART_MSR_DSR	0x20		/* Data Set Ready */
+#define UART_MSR_CTS	0x10		/* Clear to Send */
+#define UART_MSR_DDCD	0x08		/* Delta DCD */
+#define UART_MSR_TERI	0x04		/* Trailing edge ring indicator */
+#define UART_MSR_DDSR	0x02		/* Delta DSR */
+#define UART_MSR_DCTS	0x01		/* Delta CTS */
+
+/*
+ * These are the definitions for the Interrupt Identification Register
+ */
+#define UART_IIR_NO_INT	0x01	/* No interrupts pending */
+#define UART_IIR_ID	0x06	/* Mask for the interrupt ID */
+
+#define UART_IIR_MSI	0x00	/* Modem status interrupt */
+#define UART_IIR_THRI	0x02	/* Transmitter holding register empty */
+#define UART_IIR_RDI	0x04	/* Receiver data interrupt */
+#define UART_IIR_RLSI	0x06	/* Receiver line status interrupt */
+
+/*
+ * These are the definitions for the Interrupt Enable Register
+ */
+#define UART_IER_MSI	0x08	/* Enable Modem status interrupt */
+#define UART_IER_RLSI	0x04	/* Enable receiver line status interrupt */
+#define UART_IER_THRI	0x02	/* Enable Transmitter holding register int. */
+#define UART_IER_RDI	0x01	/* Enable receiver data interrupt */
+
+
 #ifdef CONFIG_OMAP1510
-#define OSC_12M_SEL	0x01		/* selects 6.5 * current clk div */
+#define OSC_12M_SEL	0x01	/* selects 6.5 * current clk div */
 #endif
  
 /* useful defaults for LCR */
-#define LCR_8N1		0x03
+#define UART_LCR_8N1	0x03
  
 void	NS16550_init   (NS16550_t com_port, int baud_divisor);
 void	NS16550_putc   (NS16550_t com_port, char c);
@@ -53,104 +53,5 @@
 	u8	*iomem_base;
 };
  
-#define UART_RX		0	/* In:  Receive buffer (DLAB=0) */
-#define UART_TX		0	/* Out: Transmit buffer (DLAB=0) */
-#define UART_DLL	0	/* Out: Divisor Latch Low (DLAB=1) */
-
-#define UART_DLM	1	/* Out: Divisor Latch High (DLAB=1) */
-#define UART_IER	1	/* Out: Interrupt Enable Register */
-
-#define UART_IIR	2	/* In:  Interrupt ID Register */
-#define UART_FCR	2	/* Out: FIFO Control Register */
-
-#define UART_LCR	3	/* Out: Line Control Register */
-#define UART_MCR	4	/* Out: Modem Control Register */
-#define UART_LSR	5	/* In:  Line Status Register */
-#define UART_MSR	6	/* In:  Modem Status Register */
-#define UART_SCR	7	/* I/O: Scratch Register */
-
-/*
- * These are the definitions for the FIFO Control Register
- * (16650 only)
- */
-#define UART_FCR_ENABLE_FIFO	0x01 /* Enable the FIFO */
-#define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
-#define UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
-#define UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
-#define UART_FCR_TRIGGER_MASK	0xC0 /* Mask for the FIFO trigger range */
-#define UART_FCR_TRIGGER_1	0x00 /* Mask for trigger set at 1 */
-#define UART_FCR_TRIGGER_4	0x40 /* Mask for trigger set at 4 */
-#define UART_FCR_TRIGGER_8	0x80 /* Mask for trigger set at 8 */
-#define UART_FCR_TRIGGER_14	0xC0 /* Mask for trigger set at 14 */
-
-/*
- * These are the definitions for the Line Control Register
- *
- * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
- * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
- */
-#define UART_LCR_DLAB	0x80	/* Divisor latch access bit */
-#define UART_LCR_SBC	0x40	/* Set break control */
-#define UART_LCR_SPAR	0x20	/* Stick parity (?) */
-#define UART_LCR_EPAR	0x10	/* Even parity select */
-#define UART_LCR_PARITY	0x08	/* Parity Enable */
-#define UART_LCR_STOP	0x04	/* Stop bits: 0=1 stop bit, 1= 2 stop bits */
-#define UART_LCR_WLEN5  0x00	/* Wordlength: 5 bits */
-#define UART_LCR_WLEN6  0x01	/* Wordlength: 6 bits */
-#define UART_LCR_WLEN7  0x02	/* Wordlength: 7 bits */
-#define UART_LCR_WLEN8  0x03	/* Wordlength: 8 bits */
-
-/*
- * These are the definitions for the Line Status Register
- */
-#define UART_LSR_TEMT	0x40	/* Transmitter empty */
-#define UART_LSR_THRE	0x20	/* Transmit-hold-register empty */
-#define UART_LSR_BI	0x10	/* Break interrupt indicator */
-#define UART_LSR_FE	0x08	/* Frame error indicator */
-#define UART_LSR_PE	0x04	/* Parity error indicator */
-#define UART_LSR_OE	0x02	/* Overrun error indicator */
-#define UART_LSR_DR	0x01	/* Receiver data ready */
-
-/*
- * These are the definitions for the Interrupt Identification Register
- */
-#define UART_IIR_NO_INT	0x01	/* No interrupts pending */
-#define UART_IIR_ID	0x06	/* Mask for the interrupt ID */
-
-#define UART_IIR_MSI	0x00	/* Modem status interrupt */
-#define UART_IIR_THRI	0x02	/* Transmitter holding register empty */
-#define UART_IIR_RDI	0x04	/* Receiver data interrupt */
-#define UART_IIR_RLSI	0x06	/* Receiver line status interrupt */
-
-/*
- * These are the definitions for the Interrupt Enable Register
- */
-#define UART_IER_MSI	0x08	/* Enable Modem status interrupt */
-#define UART_IER_RLSI	0x04	/* Enable receiver line status interrupt */
-#define UART_IER_THRI	0x02	/* Enable Transmitter holding register int. */
-#define UART_IER_RDI	0x01	/* Enable receiver data interrupt */
-
-/*
- * These are the definitions for the Modem Control Register
- */
-#define UART_MCR_LOOP	0x10	/* Enable loopback test mode */
-#define UART_MCR_OUT2	0x08	/* Out2 complement */
-#define UART_MCR_OUT1	0x04	/* Out1 complement */
-#define UART_MCR_RTS	0x02	/* RTS complement */
-#define UART_MCR_DTR	0x01	/* DTR complement */
-
-/*
- * These are the definitions for the Modem Status Register
- */
-#define UART_MSR_DCD	0x80	/* Data Carrier Detect */
-#define UART_MSR_RI	0x40	/* Ring Indicator */
-#define UART_MSR_DSR	0x20	/* Data Set Ready */
-#define UART_MSR_CTS	0x10	/* Clear to Send */
-#define UART_MSR_DDCD	0x08	/* Delta DCD */
-#define UART_MSR_TERI	0x04	/* Trailing edge ring indicator */
-#define UART_MSR_DDSR	0x02	/* Delta DSR */
-#define UART_MSR_DCTS	0x01	/* Delta CTS */
-#define UART_MSR_ANY_DELTA 0x0F	/* Any of the delta bits! */
-
 #endif /* __LINUX_PS2MULT_H */
...	...	@@ -280,48 +280,48 @@
280	280	if ((num >= 0) && (num <= 7)) {
281	281	if (mode & 1) {
282	282	/* turn on 'loopback' mode */
283		- out_8(&uart->mcr, MCR_LOOP);
	283	+ out_8(&uart->mcr, UART_MCR_LOOP);
284	284	} else {
285	285	/*
286	286	* establish the UART's operational parameters
287	287	* set DLAB=1, so rbr accesses DLL
288	288	*/
289		- out_8(&uart->lcr, LCR_DLAB);
	289	+ out_8(&uart->lcr, UART_LCR_DLAB);
290	290	/* set baudrate */
291	291	out_8(&uart->rbr, combrd);
292	292	/* set data-format: 8-N-1 */
293		- out_8(&uart->lcr, LCR_WLS_8);
	293	+ out_8(&uart->lcr, UART_LCR_WLS_8);
294	294	}
295	295
296	296	if (mode & 2) {
297	297	/* set request to send */
298		- out_8(&uart->mcr, MCR_RTS);
	298	+ out_8(&uart->mcr, UART_MCR_RTS);
299	299	udelay(10);
300	300	/* check clear to send */
301		- if ((in_8(&uart->msr) & MSR_CTS) == 0x00)
	301	+ if ((in_8(&uart->msr) & UART_MSR_CTS) == 0x00)
302	302	return -1;
303	303	}
304	304	if (mode & 4) {
305	305	/* set data terminal ready */
306		- out_8(&uart->mcr, MCR_DTR);
	306	+ out_8(&uart->mcr, UART_MCR_DTR);
307	307	udelay(10);
308	308	/* check data set ready and carrier detect */
309		- if ((in_8(&uart->msr) & (MSR_DSR \| MSR_DCD))
310		- != (MSR_DSR \| MSR_DCD))
	309	+ if ((in_8(&uart->msr) & (UART_MSR_DSR \| UART_MSR_DCD))
	310	+ != (UART_MSR_DSR \| UART_MSR_DCD))
311	311	return -1;
312	312	}
313	313
314	314	/* write each message-character, read it back, and display it */
315	315	for (i = 0, len = strlen(argv[3]); i < len; ++i) {
316	316	j = 0;
317		- while ((in_8(&uart->lsr) & LSR_THRE) == 0x00) {
	317	+ while ((in_8(&uart->lsr) & UART_LSR_THRE) == 0x00) {
318	318	if (j++ > CONFIG_SYS_HZ)
319	319	break;
320	320	udelay(10);
321	321	}
322	322	out_8(&uart->rbr, argv[3][i]);
323	323	j = 0;
324		- while ((in_8(&uart->lsr) & LSR_DR) == 0x00) {
	324	+ while ((in_8(&uart->lsr) & UART_LSR_DR) == 0x00) {
325	325	if (j++ > CONFIG_SYS_HZ)
326	326	break;
327	327	udelay(10);
...	...	@@ -90,12 +90,12 @@
90	90	*/
91	91	AVR_port->lcr = 0x00;
92	92	AVR_port->ier = 0x00;
93		- AVR_port->lcr = LCR_BKSE;
	93	+ AVR_port->lcr = UART_LCR_BKSE;
94	94	AVR_port->dll = clock_divisor & 0xff;
95	95	AVR_port->dlm = (clock_divisor >> 8) & 0xff;
96		- AVR_port->lcr = LCR_WLS_8 \| LCR_PEN \| LCR_EPS;
	96	+ AVR_port->lcr = UART_LCR_WLS_8 \| UART_LCR_PEN \| UART_LCR_EPS;
97	97	AVR_port->mcr = 0x00;
98		- AVR_port->fcr = FCR_FIFO_EN \| FCR_RXSR \| FCR_TXSR;
	98	+ AVR_port->fcr = UART_FCR_FIFO_EN \| UART_FCR_RXSR \| UART_FCR_TXSR;
99	99
100	100	miconCntl_DisWDT();
101	101
1	1	/***********************************************************************
2	2	*
3		- * (C) Copyright 2004
	3	+ * (C) Copyright 2004-2009
4	4	* DENX Software Engineering
5	5	* Wolfgang Denk, wd@denx.de
6	6	* All rights reserved.
7	7
...	...	@@ -18,9 +18,11 @@
18	18	#include <asm/io.h>
19	19	#include <asm/atomic.h>
20	20	#include <ps2mult.h>
21		-#if defined(CONFIG_SYS_NS16550) \|\| defined(CONFIG_MPC85xx)
22		-#include <ns16550.h>
	21	+/* This is needed for ns16550.h */
	22	+#ifndef CONFIG_SYS_NS16550_REG_SIZE
	23	+#define CONFIG_SYS_NS16550_REG_SIZE 1
23	24	#endif
	25	+#include <ns16550.h>
24	26
25	27	DECLARE_GLOBAL_DATA_PTR;
26	28
27	29
...	...	@@ -128,12 +130,12 @@
128	130	NS16550_t com_port = (NS16550_t)COM_BASE;
129	131
130	132	com_port->ier = 0x00;
131		- com_port->lcr = LCR_BKSE \| LCR_8N1;
	133	+ com_port->lcr = UART_LCR_BKSE \| UART_LCR_8N1;
132	134	com_port->dll = (CONFIG_SYS_NS16550_CLK / 16 / PS2SER_BAUD) & 0xff;
133	135	com_port->dlm = ((CONFIG_SYS_NS16550_CLK / 16 / PS2SER_BAUD) >> 8) & 0xff;
134		- com_port->lcr = LCR_8N1;
135		- com_port->mcr = (MCR_DTR \| MCR_RTS);
136		- com_port->fcr = (FCR_FIFO_EN \| FCR_RXSR \| FCR_TXSR);
	136	+ com_port->lcr = UART_LCR_8N1;
	137	+ com_port->mcr = (UART_MCR_DTR \| UART_MCR_RTS);
	138	+ com_port->fcr = (UART_FCR_FIFO_EN \| UART_FCR_RXSR \| UART_FCR_TXSR);
137	139
138	140	return (0);
139	141	}
...	...	@@ -202,7 +204,7 @@
202	204	psc->psc_buffer_8 = chr;
203	205	#elif defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| \
204	206	defined(CONFIG_MPC8548) \|\| defined(CONFIG_MPC8555)
205		- while ((com_port->lsr & LSR_THRE) == 0);
	207	+ while ((com_port->lsr & UART_LSR_THRE) == 0);
206	208	com_port->thr = chr;
207	209	#else
208	210	while (!(ps2ser_in(UART_LSR) & UART_LSR_THRE));
...	...	@@ -227,7 +229,7 @@
227	229	}
228	230	#elif defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| \
229	231	defined(CONFIG_MPC8548) \|\| defined(CONFIG_MPC8555)
230		- if (com_port->lsr & LSR_DR) {
	232	+ if (com_port->lsr & UART_LSR_DR) {
231	233	res = com_port->rbr;
232	234	}
233	235	#else
...	...	@@ -315,7 +317,7 @@
315	317	} while (status & PSC_SR_RXRDY);
316	318	#elif defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| \
317	319	defined(CONFIG_MPC8548) \|\| defined(CONFIG_MPC8555)
318		- } while (status & LSR_DR);
	320	+ } while (status & UART_LSR_DR);
319	321	#else
320	322	} while (status & UART_IIR_RDI);
321	323	#endif
...	...	@@ -7,9 +7,12 @@
7	7	#include <config.h>
8	8	#include <ns16550.h>
9	9
10		-#define LCRVAL LCR_8N1 /* 8 data, 1 stop, no parity */
11		-#define MCRVAL (MCR_DTR \| MCR_RTS) /* RTS/DTR */
12		-#define FCRVAL (FCR_FIFO_EN \| FCR_RXSR \| FCR_TXSR) /* Clear & enable FIFOs */
	10	+#define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */
	11	+#define UART_MCRVAL (UART_MCR_DTR \| \
	12	+ UART_MCR_RTS) /* RTS/DTR */
	13	+#define UART_FCRVAL (UART_FCR_FIFO_EN \| \
	14	+ UART_FCR_RXSR \| \
	15	+ UART_FCR_TXSR) /* Clear & enable FIFOs */
13	16
14	17	void NS16550_init (NS16550_t com_port, int baud_divisor)
15	18	{
16	19
17	20
...	...	@@ -17,16 +20,16 @@
17	20	#ifdef CONFIG_OMAP
18	21	com_port->mdr1 = 0x7; /* mode select reset TL16C750*/
19	22	#endif
20		- com_port->lcr = LCR_BKSE \| LCRVAL;
	23	+ com_port->lcr = UART_LCR_BKSE \| UART_LCRVAL;
21	24	com_port->dll = 0;
22	25	com_port->dlm = 0;
23		- com_port->lcr = LCRVAL;
24		- com_port->mcr = MCRVAL;
25		- com_port->fcr = FCRVAL;
26		- com_port->lcr = LCR_BKSE \| LCRVAL;
	26	+ com_port->lcr = UART_LCRVAL;
	27	+ com_port->mcr = UART_MCRVAL;
	28	+ com_port->fcr = UART_FCRVAL;
	29	+ com_port->lcr = UART_LCR_BKSE \| UART_LCRVAL;
27	30	com_port->dll = baud_divisor & 0xff;
28	31	com_port->dlm = (baud_divisor >> 8) & 0xff;
29		- com_port->lcr = LCRVAL;
	32	+ com_port->lcr = UART_LCRVAL;
30	33	#if defined(CONFIG_OMAP)
31	34	#if defined(CONFIG_APTIX)
32	35	com_port->mdr1 = 3; /* /13 mode so Aptix 6MHz can hit 115200 */
33	36
34	37
35	38
36	39
...	...	@@ -40,29 +43,29 @@
40	43	void NS16550_reinit (NS16550_t com_port, int baud_divisor)
41	44	{
42	45	com_port->ier = 0x00;
43		- com_port->lcr = LCR_BKSE \| LCRVAL;
	46	+ com_port->lcr = UART_LCR_BKSE \| UART_LCRVAL;
44	47	com_port->dll = 0;
45	48	com_port->dlm = 0;
46		- com_port->lcr = LCRVAL;
47		- com_port->mcr = MCRVAL;
48		- com_port->fcr = FCRVAL;
49		- com_port->lcr = LCR_BKSE;
	49	+ com_port->lcr = UART_LCRVAL;
	50	+ com_port->mcr = UART_MCRVAL;
	51	+ com_port->fcr = UART_FCRVAL;
	52	+ com_port->lcr = UART_LCR_BKSE;
50	53	com_port->dll = baud_divisor & 0xff;
51	54	com_port->dlm = (baud_divisor >> 8) & 0xff;
52		- com_port->lcr = LCRVAL;
	55	+ com_port->lcr = UART_LCRVAL;
53	56	}
54	57	#endif /* CONFIG_NS16550_MIN_FUNCTIONS */
55	58
56	59	void NS16550_putc (NS16550_t com_port, char c)
57	60	{
58		- while ((com_port->lsr & LSR_THRE) == 0);
	61	+ while ((com_port->lsr & UART_LSR_THRE) == 0);
59	62	com_port->thr = c;
60	63	}
61	64
62	65	#ifndef CONFIG_NS16550_MIN_FUNCTIONS
63	66	char NS16550_getc (NS16550_t com_port)
64	67	{
65		- while ((com_port->lsr & LSR_DR) == 0) {
	68	+ while ((com_port->lsr & UART_LSR_DR) == 0) {
66	69	#ifdef CONFIG_USB_TTY
67	70	extern void usbtty_poll(void);
68	71	usbtty_poll();
...	...	@@ -73,7 +76,7 @@
73	76
74	77	int NS16550_tstc (NS16550_t com_port)
75	78	{
76		- return ((com_port->lsr & LSR_DR) != 0);
	79	+ return ((com_port->lsr & UART_LSR_DR) != 0);
77	80	}
78	81
79	82	#endif /* CONFIG_NS16550_MIN_FUNCTIONS */
1	1	/*
2	2	* NS16550 Serial Port
3	3	* originally from linux source (arch/ppc/boot/ns16550.h)
	4	+ *
	5	+ * Cleanup and unification
	6	+ * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH
	7	+ *
4	8	* modified slightly to
5	9	* have addresses as offsets from CONFIG_SYS_ISA_BASE
6	10	* added a few more definitions
7	11
8	12
9	13
10	14
11	15
12	16
13	17
...	...	@@ -115,53 +119,100 @@
115	119
116	120	typedef volatile struct NS16550 *NS16550_t;
117	121
118		-#define FCR_FIFO_EN 0x01 /* Fifo enable */
119		-#define FCR_RXSR 0x02 /* Receiver soft reset */
120		-#define FCR_TXSR 0x04 /* Transmitter soft reset */
	122	+/*
	123	+ * These are the definitions for the FIFO Control Register
	124	+ */
	125	+#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
	126	+#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
	127	+#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
	128	+#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
	129	+#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
	130	+#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
	131	+#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
	132	+#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
	133	+#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
121	134
122		-#define MCR_DTR 0x01
123		-#define MCR_RTS 0x02
124		-#define MCR_DMA_EN 0x04
125		-#define MCR_TX_DFR 0x08
126		-#define MCR_LOOP 0x10 /* Enable loopback test mode */
	135	+#define UART_FCR_RXSR 0x02 /* Receiver soft reset */
	136	+#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
127	137
128		-#define LCR_WLS_MSK 0x03 /* character length select mask */
129		-#define LCR_WLS_5 0x00 /* 5 bit character length */
130		-#define LCR_WLS_6 0x01 /* 6 bit character length */
131		-#define LCR_WLS_7 0x02 /* 7 bit character length */
132		-#define LCR_WLS_8 0x03 /* 8 bit character length */
133		-#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
134		-#define LCR_PEN 0x08 /* Parity eneble */
135		-#define LCR_EPS 0x10 /* Even Parity Select */
136		-#define LCR_STKP 0x20 /* Stick Parity */
137		-#define LCR_SBRK 0x40 /* Set Break */
138		-#define LCR_BKSE 0x80 /* Bank select enable */
139		-#define LCR_DLAB 0x80 /* Divisor latch access bit */
	138	+/*
	139	+ * These are the definitions for the Modem Control Register
	140	+ */
	141	+#define UART_MCR_DTR 0x01 /* DTR */
	142	+#define UART_MCR_RTS 0x02 /* RTS */
	143	+#define UART_MCR_OUT1 0x04 /* Out 1 */
	144	+#define UART_MCR_OUT2 0x08 /* Out 2 */
	145	+#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
140	146
141		-#define LSR_DR 0x01 /* Data ready */
142		-#define LSR_OE 0x02 /* Overrun */
143		-#define LSR_PE 0x04 /* Parity error */
144		-#define LSR_FE 0x08 /* Framing error */
145		-#define LSR_BI 0x10 /* Break */
146		-#define LSR_THRE 0x20 /* Xmit holding register empty */
147		-#define LSR_TEMT 0x40 /* Xmitter empty */
148		-#define LSR_ERR 0x80 /* Error */
	147	+#define UART_MCR_DMA_EN 0x04
	148	+#define UART_MCR_TX_DFR 0x08
149	149
150		-#define MSR_DCD 0x80 /* Data Carrier Detect */
151		-#define MSR_RI 0x40 /* Ring Indicator */
152		-#define MSR_DSR 0x20 /* Data Set Ready */
153		-#define MSR_CTS 0x10 /* Clear to Send */
154		-#define MSR_DDCD 0x08 /* Delta DCD */
155		-#define MSR_TERI 0x04 /* Trailing edge ring indicator */
156		-#define MSR_DDSR 0x02 /* Delta DSR */
157		-#define MSR_DCTS 0x01 /* Delta CTS */
	150	+/*
	151	+ * These are the definitions for the Line Control Register
	152	+ *
	153	+ * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
	154	+ * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
	155	+ */
	156	+#define UART_LCR_WLS_MSK 0x03 /* character length select mask */
	157	+#define UART_LCR_WLS_5 0x00 /* 5 bit character length */
	158	+#define UART_LCR_WLS_6 0x01 /* 6 bit character length */
	159	+#define UART_LCR_WLS_7 0x02 /* 7 bit character length */
	160	+#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
	161	+#define UART_LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
	162	+#define UART_LCR_PEN 0x08 /* Parity eneble */
	163	+#define UART_LCR_EPS 0x10 /* Even Parity Select */
	164	+#define UART_LCR_STKP 0x20 /* Stick Parity */
	165	+#define UART_LCR_SBRK 0x40 /* Set Break */
	166	+#define UART_LCR_BKSE 0x80 /* Bank select enable */
	167	+#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
158	168
	169	+/*
	170	+ * These are the definitions for the Line Status Register
	171	+ */
	172	+#define UART_LSR_DR 0x01 /* Data ready */
	173	+#define UART_LSR_OE 0x02 /* Overrun */
	174	+#define UART_LSR_PE 0x04 /* Parity error */
	175	+#define UART_LSR_FE 0x08 /* Framing error */
	176	+#define UART_LSR_BI 0x10 /* Break */
	177	+#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
	178	+#define UART_LSR_TEMT 0x40 /* Xmitter empty */
	179	+#define UART_LSR_ERR 0x80 /* Error */
	180	+
	181	+#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
	182	+#define UART_MSR_RI 0x40 /* Ring Indicator */
	183	+#define UART_MSR_DSR 0x20 /* Data Set Ready */
	184	+#define UART_MSR_CTS 0x10 /* Clear to Send */
	185	+#define UART_MSR_DDCD 0x08 /* Delta DCD */
	186	+#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
	187	+#define UART_MSR_DDSR 0x02 /* Delta DSR */
	188	+#define UART_MSR_DCTS 0x01 /* Delta CTS */
	189	+
	190	+/*
	191	+ * These are the definitions for the Interrupt Identification Register
	192	+ */
	193	+#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
	194	+#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
	195	+
	196	+#define UART_IIR_MSI 0x00 /* Modem status interrupt */
	197	+#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
	198	+#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
	199	+#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
	200	+
	201	+/*
	202	+ * These are the definitions for the Interrupt Enable Register
	203	+ */
	204	+#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
	205	+#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
	206	+#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
	207	+#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
	208	+
	209	+
159	210	#ifdef CONFIG_OMAP1510
160		-#define OSC_12M_SEL 0x01 /* selects 6.5 * current clk div */
	211	+#define OSC_12M_SEL 0x01 /* selects 6.5 * current clk div */
161	212	#endif
162	213
163	214	/* useful defaults for LCR */
164		-#define LCR_8N1 0x03
	215	+#define UART_LCR_8N1 0x03
165	216
166	217	void NS16550_init (NS16550_t com_port, int baud_divisor);
167	218	void NS16550_putc (NS16550_t com_port, char c);
...	...	@@ -53,104 +53,5 @@
53	53	u8 *iomem_base;
54	54	};
55	55
56		-#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
57		-#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
58		-#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
59		-
60		-#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
61		-#define UART_IER 1 /* Out: Interrupt Enable Register */
62		-
63		-#define UART_IIR 2 /* In: Interrupt ID Register */
64		-#define UART_FCR 2 /* Out: FIFO Control Register */
65		-
66		-#define UART_LCR 3 /* Out: Line Control Register */
67		-#define UART_MCR 4 /* Out: Modem Control Register */
68		-#define UART_LSR 5 /* In: Line Status Register */
69		-#define UART_MSR 6 /* In: Modem Status Register */
70		-#define UART_SCR 7 /* I/O: Scratch Register */
71		-
72		-/*
73		- * These are the definitions for the FIFO Control Register
74		- * (16650 only)
75		- */
76		-#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
77		-#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
78		-#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
79		-#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
80		-#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
81		-#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
82		-#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
83		-#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
84		-#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
85		-
86		-/*
87		- * These are the definitions for the Line Control Register
88		- *
89		- * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
90		- * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
91		- */
92		-#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
93		-#define UART_LCR_SBC 0x40 /* Set break control */
94		-#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
95		-#define UART_LCR_EPAR 0x10 /* Even parity select */
96		-#define UART_LCR_PARITY 0x08 /* Parity Enable */
97		-#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
98		-#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
99		-#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
100		-#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
101		-#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
102		-
103		-/*
104		- * These are the definitions for the Line Status Register
105		- */
106		-#define UART_LSR_TEMT 0x40 /* Transmitter empty */
107		-#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
108		-#define UART_LSR_BI 0x10 /* Break interrupt indicator */
109		-#define UART_LSR_FE 0x08 /* Frame error indicator */
110		-#define UART_LSR_PE 0x04 /* Parity error indicator */
111		-#define UART_LSR_OE 0x02 /* Overrun error indicator */
112		-#define UART_LSR_DR 0x01 /* Receiver data ready */
113		-
114		-/*
115		- * These are the definitions for the Interrupt Identification Register
116		- */
117		-#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
118		-#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
119		-
120		-#define UART_IIR_MSI 0x00 /* Modem status interrupt */
121		-#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
122		-#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
123		-#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
124		-
125		-/*
126		- * These are the definitions for the Interrupt Enable Register
127		- */
128		-#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
129		-#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
130		-#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
131		-#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
132		-
133		-/*
134		- * These are the definitions for the Modem Control Register
135		- */
136		-#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
137		-#define UART_MCR_OUT2 0x08 /* Out2 complement */
138		-#define UART_MCR_OUT1 0x04 /* Out1 complement */
139		-#define UART_MCR_RTS 0x02 /* RTS complement */
140		-#define UART_MCR_DTR 0x01 /* DTR complement */
141		-
142		-/*
143		- * These are the definitions for the Modem Status Register
144		- */
145		-#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
146		-#define UART_MSR_RI 0x40 /* Ring Indicator */
147		-#define UART_MSR_DSR 0x20 /* Data Set Ready */
148		-#define UART_MSR_CTS 0x10 /* Clear to Send */
149		-#define UART_MSR_DDCD 0x08 /* Delta DCD */
150		-#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
151		-#define UART_MSR_DDSR 0x02 /* Delta DSR */
152		-#define UART_MSR_DCTS 0x01 /* Delta CTS */
153		-#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
154		-
155	56	#endif /* __LINUX_PS2MULT_H */