mx6: soc: update get_cpu_rev and get_imx_type for mx6solo/sololite

Previously, the same value was returned for both mx6dl and mx6solo. Check number of processors to differeniate. Also, a freescale patch says that sololite has its cpu/rev stored at 0x280 instead of 0x260. I don't have a sololite to verify. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

mx6: soc: update get_cpu_rev and get_imx_type for mx6solo/sololite
Previously, the same value was returned for both mx6dl and mx6solo. Check number of processors to differeniate. Also, a freescale patch says that sololite has its cpu/rev stored at 0x280 instead of 0x260. I don't have a sololite to verify. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Troy Kisky · Stefano Babic
1 parent 3e4d27b06d
Showing 5 changed files with 51 additions and 17 deletions Side-by-side Diff
arch/arm/cpu/armv7/mx6/soc.c
arch/arm/imx-common/cpu.c
arch/arm/include/asm/arch-mx5/sys_proto.h
arch/arm/include/asm/arch-mx6/imx-regs.h
arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -31,17 +31,33 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/imx-common/boot_mode.h>
  
+struct scu_regs {
+	u32	ctrl;
+	u32	config;
+	u32	status;
+	u32	invalidate;
+	u32	fpga_rev;
+};
+
 u32 get_cpu_rev(void)
 {
 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
-	int reg = readl(&anatop->digprog);
+	u32 reg = readl(&anatop->digprog_sololite);
+	u32 type = ((reg >> 16) & 0xff);
  
-	/* Read mx6 variant: quad, dual or solo */
-	int system_rev = (reg >> 4) & 0xFF000;
-	/* Read mx6 silicon revision */
-	system_rev |= (reg & 0xFF) + 0x10;
+	if (type != MXC_CPU_MX6SL) {
+		reg = readl(&anatop->digprog);
+		type = ((reg >> 16) & 0xff);
+		if (type == MXC_CPU_MX6DL) {
+			struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
+			u32 cfg = readl(&scu->config) & 3;
  
-	return system_rev;
+			if (!cfg)
+				type = MXC_CPU_MX6SOLO;
+		}
+	}
+	reg &= 0xff;		/* mx6 silicon revision */
+	return (type << 12) | (reg + 0x10);
 }
  
 void init_aips(void)
@@ -67,18 +67,20 @@
  
 #if defined(CONFIG_DISPLAY_CPUINFO)
  
-static const char *get_imx_type(u32 imxtype)
+const char *get_imx_type(u32 imxtype)
 {
 	switch (imxtype) {
-	case 0x63:
+	case MXC_CPU_MX6Q:
 		return "6Q";	/* Quad-core version of the mx6 */
-	case 0x61:
-		return "6DS";	/* Dual/Solo version of the mx6 */
-	case 0x60:
+	case MXC_CPU_MX6DL:
+		return "6DL";	/* Dual Lite version of the mx6 */
+	case MXC_CPU_MX6SOLO:
+		return "6SOLO";	/* Solo version of the mx6 */
+	case MXC_CPU_MX6SL:
 		return "6SL";	/* Solo-Lite version of the mx6 */
-	case 0x51:
+	case MXC_CPU_MX51:
 		return "51";
-	case 0x53:
+	case MXC_CPU_MX53:
 		return "53";
 	default:
 		return "??";
@@ -24,8 +24,15 @@
 #ifndef _SYS_PROTO_H_
 #define _SYS_PROTO_H_
  
-u32 get_cpu_rev(void);
+#define MXC_CPU_MX51		0x51
+#define MXC_CPU_MX53		0x53
+#define MXC_CPU_MX6SL		0x60
+#define MXC_CPU_MX6DL		0x61
+#define MXC_CPU_MX6SOLO		0x62
+#define MXC_CPU_MX6Q		0x63
+
 #define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
+u32 get_cpu_rev(void);
 void sdelay(unsigned long);
 void set_chipselect_size(int const);
  
@@ -564,6 +564,8 @@
 	u32	usb2_misc_clr;		/* 0x258 */
 	u32	usb2_misc_tog;		/* 0x25c */
 	u32	digprog;		/* 0x260 */
+	u32	reserved1[7];
+	u32	digprog_sololite;	/* 0x280 */
 };
  
 #define ANATOP_PFD_480_PFD0_FRAC_SHIFT		0
@@ -24,9 +24,16 @@
 #ifndef _SYS_PROTO_H_
 #define _SYS_PROTO_H_
  
-#define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
+#define MXC_CPU_MX51		0x51
+#define MXC_CPU_MX53		0x53
+#define MXC_CPU_MX6SL		0x60
+#define MXC_CPU_MX6DL		0x61
+#define MXC_CPU_MX6SOLO		0x62
+#define MXC_CPU_MX6Q		0x63
  
+#define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
 u32 get_cpu_rev(void);
+const char *get_imx_type(u32 imxtype);
  
 void set_vddsoc(u32 mv);
...	...	@@ -31,17 +31,33 @@
31	31	#include <asm/arch/sys_proto.h>
32	32	#include <asm/imx-common/boot_mode.h>
33	33
	34	+struct scu_regs {
	35	+ u32 ctrl;
	36	+ u32 config;
	37	+ u32 status;
	38	+ u32 invalidate;
	39	+ u32 fpga_rev;
	40	+};
	41	+
34	42	u32 get_cpu_rev(void)
35	43	{
36	44	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
37		- int reg = readl(&anatop->digprog);
	45	+ u32 reg = readl(&anatop->digprog_sololite);
	46	+ u32 type = ((reg >> 16) & 0xff);
38	47
39		- /* Read mx6 variant: quad, dual or solo */
40		- int system_rev = (reg >> 4) & 0xFF000;
41		- /* Read mx6 silicon revision */
42		- system_rev \|= (reg & 0xFF) + 0x10;
	48	+ if (type != MXC_CPU_MX6SL) {
	49	+ reg = readl(&anatop->digprog);
	50	+ type = ((reg >> 16) & 0xff);
	51	+ if (type == MXC_CPU_MX6DL) {
	52	+ struct scu_regs scu = (struct scu_regs )SCU_BASE_ADDR;
	53	+ u32 cfg = readl(&scu->config) & 3;
43	54
44		- return system_rev;
	55	+ if (!cfg)
	56	+ type = MXC_CPU_MX6SOLO;
	57	+ }
	58	+ }
	59	+ reg &= 0xff; /* mx6 silicon revision */
	60	+ return (type << 12) \| (reg + 0x10);
45	61	}
46	62
47	63	void init_aips(void)
...	...	@@ -67,18 +67,20 @@
67	67
68	68	#if defined(CONFIG_DISPLAY_CPUINFO)
69	69
70		-static const char *get_imx_type(u32 imxtype)
	70	+const char *get_imx_type(u32 imxtype)
71	71	{
72	72	switch (imxtype) {
73		- case 0x63:
	73	+ case MXC_CPU_MX6Q:
74	74	return "6Q"; /* Quad-core version of the mx6 */
75		- case 0x61:
76		- return "6DS"; /* Dual/Solo version of the mx6 */
77		- case 0x60:
	75	+ case MXC_CPU_MX6DL:
	76	+ return "6DL"; /* Dual Lite version of the mx6 */
	77	+ case MXC_CPU_MX6SOLO:
	78	+ return "6SOLO"; /* Solo version of the mx6 */
	79	+ case MXC_CPU_MX6SL:
78	80	return "6SL"; /* Solo-Lite version of the mx6 */
79		- case 0x51:
	81	+ case MXC_CPU_MX51:
80	82	return "51";
81		- case 0x53:
	83	+ case MXC_CPU_MX53:
82	84	return "53";
83	85	default:
84	86	return "??";
...	...	@@ -24,8 +24,15 @@
24	24	#ifndef _SYS_PROTO_H_
25	25	#define _SYS_PROTO_H_
26	26
27		-u32 get_cpu_rev(void);
	27	+#define MXC_CPU_MX51 0x51
	28	+#define MXC_CPU_MX53 0x53
	29	+#define MXC_CPU_MX6SL 0x60
	30	+#define MXC_CPU_MX6DL 0x61
	31	+#define MXC_CPU_MX6SOLO 0x62
	32	+#define MXC_CPU_MX6Q 0x63
	33	+
28	34	#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
	35	+u32 get_cpu_rev(void);
29	36	void sdelay(unsigned long);
30	37	void set_chipselect_size(int const);
31	38
...	...	@@ -564,6 +564,8 @@
564	564	u32 usb2_misc_clr; /* 0x258 */
565	565	u32 usb2_misc_tog; /* 0x25c */
566	566	u32 digprog; /* 0x260 */
	567	+ u32 reserved1[7];
	568	+ u32 digprog_sololite; /* 0x280 */
567	569	};
568	570
569	571	#define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0
...	...	@@ -24,9 +24,16 @@
24	24	#ifndef _SYS_PROTO_H_
25	25	#define _SYS_PROTO_H_
26	26
27		-#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
	27	+#define MXC_CPU_MX51 0x51
	28	+#define MXC_CPU_MX53 0x53
	29	+#define MXC_CPU_MX6SL 0x60
	30	+#define MXC_CPU_MX6DL 0x61
	31	+#define MXC_CPU_MX6SOLO 0x62
	32	+#define MXC_CPU_MX6Q 0x63
28	33
	34	+#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
29	35	u32 get_cpu_rev(void);
	36	+const char *get_imx_type(u32 imxtype);
30	37
31	38	void set_vddsoc(u32 mv);
32	39