Eric Lee / smarc-uboot

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Commit 20680b560a17fb29c862de77930cfbf76b24f83c

Authored by Tom Rini
2 parents db6ce2312d 2a0b9ea306
Exists in v2017.01-smarct4x and in 30 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

Merge branch 'master' of git://git.denx.de/u-boot-atmel

Showing 80 changed files Side-by-side Diff

arch/arm/mach-at91/Kconfig
Diff comments   View file @ 20680b5
... ... @@ -96,6 +96,11 @@
96 96 select CPU_V7
97 97 select SUPPORT_SPL
98 98  
  99 +config TARGET_MA5D4EVK
  100 + bool "DENX MA5D4EVK Evaluation Kit"
  101 + select CPU_V7
  102 + select SUPPORT_SPL
  103 +
99 104 config TARGET_MEESC
100 105 bool "Support meesc"
101 106 select CPU_ARM926EJS
... ... @@ -115,6 +120,11 @@
115 120 select CPU_ARM926EJS
116 121 select SUPPORT_SPL
117 122  
  123 +config TARGET_VINCO
  124 + bool "Support VINCO"
  125 + select CPU_V7
  126 + select SUPPORT_SPL
  127 +
118 128 endchoice
119 129  
120 130 config SYS_SOC
121 131  
... ... @@ -135,8 +145,10 @@
135 145 source "board/atmel/sama5d4ek/Kconfig"
136 146 source "board/bluewater/snapper9260/Kconfig"
137 147 source "board/calao/usb_a9263/Kconfig"
  148 +source "board/denx/ma5d4evk/Kconfig"
138 149 source "board/egnite/ethernut5/Kconfig"
139 150 source "board/esd/meesc/Kconfig"
  151 +source "board/l+g/vinco/Kconfig"
140 152 source "board/mini-box/picosam9g45/Kconfig"
141 153 source "board/ronetix/pm9261/Kconfig"
142 154 source "board/ronetix/pm9263/Kconfig"
arch/arm/mach-at91/Makefile
Diff comments   View file @ 20680b5
... ... @@ -15,6 +15,7 @@
15 15 obj-y += spl.o
16 16 endif
17 17  
  18 +obj-y += clock.o
18 19 obj-$(CONFIG_CPU_ARM920T) += arm920t/
19 20 obj-$(CONFIG_CPU_ARM926EJS) += arm926ejs/
20 21 obj-$(CONFIG_CPU_V7) += armv7/
arch/arm/mach-at91/arm920t/at91rm9200_devices.c
Diff comments   View file @ 20680b5
... ... @@ -14,7 +14,7 @@
14 14 #include <common.h>
15 15 #include <asm/io.h>
16 16 #include <asm/arch/at91_common.h>
17   -#include <asm/arch/at91_pmc.h>
  17 +#include <asm/arch/clk.h>
18 18 #include <asm/arch/gpio.h>
19 19  
20 20 /*
21 21  
22 22  
23 23  
24 24  
25 25  
... ... @@ -34,29 +34,23 @@
34 34  
35 35 void at91_serial0_hw_init(void)
36 36 {
37   - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
38   -
39 37 at91_set_a_periph(AT91_PIO_PORTA, 17, 1); /* TXD0 */
40 38 at91_set_a_periph(AT91_PIO_PORTA, 18, PUP); /* RXD0 */
41   - writel(1 << ATMEL_ID_USART0, &pmc->pcer);
  39 + at91_periph_clk_enable(ATMEL_ID_USART0);
42 40 }
43 41  
44 42 void at91_serial1_hw_init(void)
45 43 {
46   - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
47   -
48 44 at91_set_a_periph(AT91_PIO_PORTB, 20, PUP); /* RXD1 */
49 45 at91_set_a_periph(AT91_PIO_PORTB, 21, 1); /* TXD1 */
50   - writel(1 << ATMEL_ID_USART1, &pmc->pcer);
  46 + at91_periph_clk_enable(ATMEL_ID_USART1);
51 47 }
52 48  
53 49 void at91_serial2_hw_init(void)
54 50 {
55   - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
56   -
57 51 at91_set_a_periph(AT91_PIO_PORTA, 22, PUP); /* RXD2 */
58 52 at91_set_a_periph(AT91_PIO_PORTA, 23, 1); /* TXD2 */
59   - writel(1 << ATMEL_ID_USART2, &pmc->pcer);
  53 + at91_periph_clk_enable(ATMEL_ID_USART2);
60 54 }
61 55  
62 56 void at91_seriald_hw_init(void)
arch/arm/mach-at91/arm920t/clock.c
Diff comments   View file @ 20680b5
... ... @@ -18,6 +18,8 @@
18 18 # error You need to define CONFIG_AT91FAMILY in your board config!
19 19 #endif
20 20  
  21 +#define EN_PLLB_TIMEOUT 500
  22 +
21 23 DECLARE_GLOBAL_DATA_PTR;
22 24  
23 25 static unsigned long at91_css_to_rate(unsigned long css)
... ... @@ -152,6 +154,42 @@
152 154 gd->arch.mck_rate_hz = freq /
153 155 (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
154 156 gd->arch.cpu_clk_rate_hz = freq;
  157 +
  158 + return 0;
  159 +}
  160 +
  161 +int at91_pllb_clk_enable(u32 pllbr)
  162 +{
  163 + struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
  164 + ulong start_time, tmp_time;
  165 +
  166 + start_time = get_timer(0);
  167 + writel(pllbr, &pmc->pllbr);
  168 + while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) {
  169 + tmp_time = get_timer(0);
  170 + if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
  171 + printf("ERROR: failed to enable PLLB\n");
  172 + return -1;
  173 + }
  174 + }
  175 +
  176 + return 0;
  177 +}
  178 +
  179 +int at91_pllb_clk_disable(void)
  180 +{
  181 + struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
  182 + ulong start_time, tmp_time;
  183 +
  184 + start_time = get_timer(0);
  185 + writel(0, &pmc->pllbr);
  186 + while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) {
  187 + tmp_time = get_timer(0);
  188 + if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
  189 + printf("ERROR: failed to disable PLLB\n");
  190 + return -1;
  191 + }
  192 + }
155 193  
156 194 return 0;
157 195 }
arch/arm/mach-at91/arm920t/timer.c
Diff comments   View file @ 20680b5
... ... @@ -19,7 +19,7 @@
19 19 #include <asm/io.h>
20 20 #include <asm/arch/hardware.h>
21 21 #include <asm/arch/at91_tc.h>
22   -#include <asm/arch/at91_pmc.h>
  22 +#include <asm/arch/clk.h>
23 23  
24 24 DECLARE_GLOBAL_DATA_PTR;
25 25  
26 26  
... ... @@ -29,10 +29,8 @@
29 29 int timer_init(void)
30 30 {
31 31 at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
32   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
33 32  
34   - /* enables TC1.0 clock */
35   - writel(1 << ATMEL_ID_TC0, &pmc->pcer); /* enable clock */
  33 + at91_periph_clk_enable(ATMEL_ID_TC0);
36 34  
37 35 writel(0, &tc->bcr);
38 36 writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE |
arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c
Diff comments   View file @ 20680b5
... ... @@ -11,8 +11,8 @@
11 11 #include <asm/io.h>
12 12 #include <asm/arch/at91sam9260_matrix.h>
13 13 #include <asm/arch/at91_common.h>
14   -#include <asm/arch/at91_pmc.h>
15 14 #include <asm/arch/at91sam9_sdramc.h>
  15 +#include <asm/arch/clk.h>
16 16 #include <asm/arch/gpio.h>
17 17  
18 18 /*
19 19  
20 20  
21 21  
22 22  
23 23  
24 24  
25 25  
26 26  
27 27  
... ... @@ -32,51 +32,40 @@
32 32  
33 33 void at91_serial0_hw_init(void)
34 34 {
35   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
36   -
37 35 at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD0 */
38 36 at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD0 */
39   - writel(1 << ATMEL_ID_USART0, &pmc->pcer);
  37 + at91_periph_clk_enable(ATMEL_ID_USART0);
40 38 }
41 39  
42 40 void at91_serial1_hw_init(void)
43 41 {
44   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
45   -
46 42 at91_set_a_periph(AT91_PIO_PORTB, 6, 1); /* TXD1 */
47 43 at91_set_a_periph(AT91_PIO_PORTB, 7, PUP); /* RXD1 */
48   - writel(1 << ATMEL_ID_USART1, &pmc->pcer);
  44 + at91_periph_clk_enable(ATMEL_ID_USART1);
49 45 }
50 46  
51 47 void at91_serial2_hw_init(void)
52 48 {
53   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
54   -
55 49 at91_set_a_periph(AT91_PIO_PORTB, 8, 1); /* TXD2 */
56 50 at91_set_a_periph(AT91_PIO_PORTB, 9, PUP); /* RXD2 */
57   - writel(1 << ATMEL_ID_USART2, &pmc->pcer);
  51 + at91_periph_clk_enable(ATMEL_ID_USART2);
58 52 }
59 53  
60 54 void at91_seriald_hw_init(void)
61 55 {
62   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
63   -
64 56 at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* DRXD */
65 57 at91_set_a_periph(AT91_PIO_PORTB, 15, 1); /* DTXD */
66   - writel(1 << ATMEL_ID_SYS, &pmc->pcer);
  58 + at91_periph_clk_enable(ATMEL_ID_SYS);
67 59 }
68 60  
69 61 #if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
70 62 void at91_spi0_hw_init(unsigned long cs_mask)
71 63 {
72   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
73   -
74 64 at91_set_a_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */
75 65 at91_set_a_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */
76 66 at91_set_a_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */
77 67  
78   - /* Enable clock */
79   - writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
  68 + at91_periph_clk_enable(ATMEL_ID_SPI0);
80 69  
81 70 if (cs_mask & (1 << 0)) {
82 71 at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
83 72  
... ... @@ -106,14 +95,11 @@
106 95  
107 96 void at91_spi1_hw_init(unsigned long cs_mask)
108 97 {
109   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
110   -
111 98 at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI1_MISO */
112 99 at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI1_MOSI */
113 100 at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI1_SPCK */
114 101  
115   - /* Enable clock */
116   - writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
  102 + at91_periph_clk_enable(ATMEL_ID_SPI1);
117 103  
118 104 if (cs_mask & (1 << 0)) {
119 105 at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
... ... @@ -145,9 +131,7 @@
145 131 #ifdef CONFIG_MACB
146 132 void at91_macb_hw_init(void)
147 133 {
148   - /* Enable EMAC clock */
149   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
150   - writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
  134 + at91_periph_clk_enable(ATMEL_ID_EMAC0);
151 135  
152 136 at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* ETXCK_EREFCK */
153 137 at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* ERXDV */
... ... @@ -190,9 +174,7 @@
190 174 #if defined(CONFIG_GENERIC_ATMEL_MCI)
191 175 void at91_mci_hw_init(void)
192 176 {
193   - /* Enable mci clock */
194   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
195   - writel(1 << ATMEL_ID_MCI, &pmc->pcer);
  177 + at91_periph_clk_enable(ATMEL_ID_MCI);
196 178  
197 179 at91_set_a_periph(AT91_PIO_PORTA, 8, 1); /* MCCK */
198 180 #if defined(CONFIG_ATMEL_MCI_PORTB)
arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c
Diff comments   View file @ 20680b5
... ... @@ -9,7 +9,7 @@
9 9 #include <common.h>
10 10 #include <asm/io.h>
11 11 #include <asm/arch/at91_common.h>
12   -#include <asm/arch/at91_pmc.h>
  12 +#include <asm/arch/clk.h>
13 13 #include <asm/arch/gpio.h>
14 14  
15 15 /*
16 16  
17 17  
18 18  
19 19  
20 20  
21 21  
22 22  
23 23  
24 24  
... ... @@ -29,51 +29,40 @@
29 29  
30 30 void at91_serial0_hw_init(void)
31 31 {
32   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
33   -
34 32 at91_set_a_periph(AT91_PIO_PORTC, 8, 1); /* TXD0 */
35 33 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* RXD0 */
36   - writel(1 << ATMEL_ID_USART0, &pmc->pcer);
  34 + at91_periph_clk_enable(ATMEL_ID_USART0);
37 35 }
38 36  
39 37 void at91_serial1_hw_init(void)
40 38 {
41   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
42   -
43 39 at91_set_a_periph(AT91_PIO_PORTC, 12, 1); /* TXD1 */
44 40 at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RXD1 */
45   - writel(1 << ATMEL_ID_USART1, &pmc->pcer);
  41 + at91_periph_clk_enable(ATMEL_ID_USART1);
46 42 }
47 43  
48 44 void at91_serial2_hw_init(void)
49 45 {
50   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
51   -
52 46 at91_set_a_periph(AT91_PIO_PORTC, 14, 1); /* TXD2 */
53 47 at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* RXD2 */
54   - writel(1 << ATMEL_ID_USART2, &pmc->pcer);
  48 + at91_periph_clk_enable(ATMEL_ID_USART2);
55 49 }
56 50  
57 51 void at91_seriald_hw_init(void)
58 52 {
59   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
60   -
61 53 at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
62 54 at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
63   - writel(1 << ATMEL_ID_SYS, &pmc->pcer);
  55 + at91_periph_clk_enable(ATMEL_ID_SYS);
64 56 }
65 57  
66 58 #if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
67 59 void at91_spi0_hw_init(unsigned long cs_mask)
68 60 {
69   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
70   -
71 61 at91_set_a_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */
72 62 at91_set_a_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */
73 63 at91_set_a_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */
74 64  
75   - /* Enable clock */
76   - writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
  65 + at91_periph_clk_enable(ATMEL_ID_SPI0);
77 66  
78 67 if (cs_mask & (1 << 0)) {
79 68 at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
80 69  
... ... @@ -103,14 +92,11 @@
103 92  
104 93 void at91_spi1_hw_init(unsigned long cs_mask)
105 94 {
106   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
107   -
108 95 at91_set_a_periph(AT91_PIO_PORTB, 30, PUP); /* SPI1_MISO */
109 96 at91_set_a_periph(AT91_PIO_PORTB, 31, PUP); /* SPI1_MOSI */
110 97 at91_set_a_periph(AT91_PIO_PORTB, 29, PUP); /* SPI1_SPCK */
111 98  
112   - /* Enable clock */
113   - writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
  99 + at91_periph_clk_enable(ATMEL_ID_SPI1);
114 100  
115 101 if (cs_mask & (1 << 0)) {
116 102 at91_set_a_periph(AT91_PIO_PORTB, 28, 1);
arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c
Diff comments   View file @ 20680b5
... ... @@ -13,7 +13,7 @@
13 13 #include <common.h>
14 14 #include <asm/io.h>
15 15 #include <asm/arch/at91_common.h>
16   -#include <asm/arch/at91_pmc.h>
  16 +#include <asm/arch/clk.h>
17 17 #include <asm/arch/gpio.h>
18 18  
19 19 /*
20 20  
21 21  
22 22  
23 23  
24 24  
25 25  
26 26  
27 27  
28 28  
... ... @@ -33,51 +33,40 @@
33 33  
34 34 void at91_serial0_hw_init(void)
35 35 {
36   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
37   -
38 36 at91_set_a_periph(AT91_PIO_PORTA, 26, 1); /* TXD0 */
39 37 at91_set_a_periph(AT91_PIO_PORTA, 27, PUP); /* RXD0 */
40   - writel(1 << ATMEL_ID_USART0, &pmc->pcer);
  38 + at91_periph_clk_enable(ATMEL_ID_USART0);
41 39 }
42 40  
43 41 void at91_serial1_hw_init(void)
44 42 {
45   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
46   -
47 43 at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* TXD1 */
48 44 at91_set_a_periph(AT91_PIO_PORTD, 1, PUP); /* RXD1 */
49   - writel(1 << ATMEL_ID_USART1, &pmc->pcer);
  45 + at91_periph_clk_enable(ATMEL_ID_USART1);
50 46 }
51 47  
52 48 void at91_serial2_hw_init(void)
53 49 {
54   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
55   -
56 50 at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* TXD2 */
57 51 at91_set_a_periph(AT91_PIO_PORTD, 3, PUP); /* RXD2 */
58   - writel(1 << ATMEL_ID_USART2, &pmc->pcer);
  52 + at91_periph_clk_enable(ATMEL_ID_USART2);
59 53 }
60 54  
61 55 void at91_seriald_hw_init(void)
62 56 {
63   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
64   -
65 57 at91_set_a_periph(AT91_PIO_PORTC, 30, PUP); /* DRXD */
66 58 at91_set_a_periph(AT91_PIO_PORTC, 31, 1); /* DTXD */
67   - writel(1 << ATMEL_ID_SYS, &pmc->pcer);
  59 + at91_periph_clk_enable(ATMEL_ID_SYS);
68 60 }
69 61  
70 62 #if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
71 63 void at91_spi0_hw_init(unsigned long cs_mask)
72 64 {
73   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
74   -
75 65 at91_set_b_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */
76 66 at91_set_b_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */
77 67 at91_set_b_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */
78 68  
79   - /* Enable clock */
80   - writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
  69 + at91_periph_clk_enable(ATMEL_ID_SPI0);
81 70  
82 71 if (cs_mask & (1 << 0)) {
83 72 at91_set_b_periph(AT91_PIO_PORTA, 5, 1);
84 73  
... ... @@ -107,14 +96,11 @@
107 96  
108 97 void at91_spi1_hw_init(unsigned long cs_mask)
109 98 {
110   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
111   -
112 99 at91_set_a_periph(AT91_PIO_PORTB, 12, PUP); /* SPI1_MISO */
113 100 at91_set_a_periph(AT91_PIO_PORTB, 13, PUP); /* SPI1_MOSI */
114 101 at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* SPI1_SPCK */
115 102  
116   - /* Enable clock */
117   - writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
  103 + at91_periph_clk_enable(ATMEL_ID_SPI1);
118 104  
119 105 if (cs_mask & (1 << 0)) {
120 106 at91_set_a_periph(AT91_PIO_PORTB, 15, 1);
... ... @@ -146,9 +132,7 @@
146 132 #if defined(CONFIG_GENERIC_ATMEL_MCI)
147 133 void at91_mci_hw_init(void)
148 134 {
149   - /* Enable mci clock */
150   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
151   - writel(1 << ATMEL_ID_MCI1, &pmc->pcer);
  135 + at91_periph_clk_enable(ATMEL_ID_MCI1);
152 136  
153 137 at91_set_a_periph(AT91_PIO_PORTA, 6, PUP); /* MCI1_CK */
154 138  
155 139  
... ... @@ -207,13 +191,10 @@
207 191 #ifdef CONFIG_AT91_CAN
208 192 void at91_can_hw_init(void)
209 193 {
210   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
211   -
212 194 at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CAN_TX */
213 195 at91_set_a_periph(AT91_PIO_PORTA, 14, 1); /* CAN_RX */
214 196  
215   - /* Enable clock */
216   - writel(1 << ATMEL_ID_CAN, &pmc->pcer);
  197 + at91_periph_clk_enable(ATMEL_ID_CAN);
217 198 }
218 199 #endif
arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c
Diff comments   View file @ 20680b5
... ... @@ -8,7 +8,7 @@
8 8  
9 9 #include <common.h>
10 10 #include <asm/arch/at91_common.h>
11   -#include <asm/arch/at91_pmc.h>
  11 +#include <asm/arch/clk.h>
12 12 #include <asm/arch/gpio.h>
13 13 #include <asm/io.h>
14 14  
15 15  
16 16  
17 17  
18 18  
19 19  
20 20  
21 21  
22 22  
23 23  
... ... @@ -29,51 +29,40 @@
29 29  
30 30 void at91_serial0_hw_init(void)
31 31 {
32   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
33   -
34 32 at91_set_a_periph(AT91_PIO_PORTB, 19, 1); /* TXD0 */
35 33 at91_set_a_periph(AT91_PIO_PORTB, 18, PUP); /* RXD0 */
36   - writel(1 << ATMEL_ID_USART0, &pmc->pcer);
  34 + at91_periph_clk_enable(ATMEL_ID_USART0);
37 35 }
38 36  
39 37 void at91_serial1_hw_init(void)
40 38 {
41   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
42   -
43 39 at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD1 */
44 40 at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD1 */
45   - writel(1 << ATMEL_ID_USART1, &pmc->pcer);
  41 + at91_periph_clk_enable(ATMEL_ID_USART1);
46 42 }
47 43  
48 44 void at91_serial2_hw_init(void)
49 45 {
50   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
51   -
52 46 at91_set_a_periph(AT91_PIO_PORTD, 6, 1); /* TXD2 */
53 47 at91_set_a_periph(AT91_PIO_PORTD, 7, PUP); /* RXD2 */
54   - writel(1 << ATMEL_ID_USART2, &pmc->pcer);
  48 + at91_periph_clk_enable(ATMEL_ID_USART2);
55 49 }
56 50  
57 51 void at91_seriald_hw_init(void)
58 52 {
59   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
60   -
61 53 at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* DRXD */
62 54 at91_set_a_periph(AT91_PIO_PORTB, 13, 1); /* DTXD */
63   - writel(1 << ATMEL_ID_SYS, &pmc->pcer);
  55 + at91_periph_clk_enable(ATMEL_ID_SYS);
64 56 }
65 57  
66 58 #if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
67 59 void at91_spi0_hw_init(unsigned long cs_mask)
68 60 {
69   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
70   -
71 61 at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI0_MISO */
72 62 at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI0_MOSI */
73 63 at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI0_SPCK */
74 64  
75   - /* Enable clock */
76   - writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
  65 + at91_periph_clk_enable(ATMEL_ID_SPI0);
77 66  
78 67 if (cs_mask & (1 << 0)) {
79 68 at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
80 69  
... ... @@ -103,14 +92,11 @@
103 92  
104 93 void at91_spi1_hw_init(unsigned long cs_mask)
105 94 {
106   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
107   -
108 95 at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* SPI1_MISO */
109 96 at91_set_a_periph(AT91_PIO_PORTB, 15, PUP); /* SPI1_MOSI */
110 97 at91_set_a_periph(AT91_PIO_PORTB, 16, PUP); /* SPI1_SPCK */
111 98  
112   - /* Enable clock */
113   - writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
  99 + at91_periph_clk_enable(ATMEL_ID_SPI1);
114 100  
115 101 if (cs_mask & (1 << 0)) {
116 102 at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
... ... @@ -169,8 +155,6 @@
169 155 #ifdef CONFIG_GENERIC_ATMEL_MCI
170 156 void at91_mci_hw_init(void)
171 157 {
172   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
173   -
174 158 at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* MCI0 CLK */
175 159 at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* MCI0 CDA */
176 160 at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* MCI0 DA0 */
... ... @@ -178,8 +162,7 @@
178 162 at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* MCI0 DA2 */
179 163 at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* MCI0 DA3 */
180 164  
181   - /* Enable clock */
182   - writel(1 << ATMEL_ID_MCI0, &pmc->pcer);
  165 + at91_periph_clk_enable(ATMEL_ID_MCI0);
183 166 }
184 167 #endif
arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c
Diff comments   View file @ 20680b5
... ... @@ -8,8 +8,8 @@
8 8 #include <common.h>
9 9 #include <asm/io.h>
10 10 #include <asm/arch/at91_common.h>
11   -#include <asm/arch/at91_pmc.h>
12 11 #include <asm/arch/at91_pio.h>
  12 +#include <asm/arch/clk.h>
13 13  
14 14 unsigned int has_lcdc()
15 15 {
16 16  
17 17  
18 18  
19 19  
20 20  
21 21  
22 22  
23 23  
24 24  
25 25  
26 26  
... ... @@ -18,60 +18,47 @@
18 18  
19 19 void at91_serial0_hw_init(void)
20 20 {
21   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
22   -
23 21 at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD0 */
24 22 at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD0 */
25   - writel(1 << ATMEL_ID_USART0, &pmc->pcer);
  23 + at91_periph_clk_enable(ATMEL_ID_USART0);
26 24 }
27 25  
28 26 void at91_serial1_hw_init(void)
29 27 {
30   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
31   -
32 28 at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD1 */
33 29 at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD1 */
34   - writel(1 << ATMEL_ID_USART1, &pmc->pcer);
  30 + at91_periph_clk_enable(ATMEL_ID_USART1);
35 31 }
36 32  
37 33 void at91_serial2_hw_init(void)
38 34 {
39   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
40   -
41 35 at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD2 */
42 36 at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD2 */
43   - writel(1 << ATMEL_ID_USART2, &pmc->pcer);
  37 + at91_periph_clk_enable(ATMEL_ID_USART2);
44 38 }
45 39  
46 40 void at91_serial3_hw_init(void)
47 41 {
48   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
49   -
50 42 at91_set_b_periph(AT91_PIO_PORTC, 22, 1); /* TXD3 */
51 43 at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* RXD3 */
52   - writel(1 << ATMEL_ID_USART3, &pmc->pcer);
  44 + at91_periph_clk_enable(ATMEL_ID_USART3);
53 45 }
54 46  
55 47 void at91_seriald_hw_init(void)
56 48 {
57   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
58   -
59 49 at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
60 50 at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
61   - writel(1 << ATMEL_ID_SYS, &pmc->pcer);
  51 + at91_periph_clk_enable(ATMEL_ID_SYS);
62 52 }
63 53  
64 54 #ifdef CONFIG_ATMEL_SPI
65 55 void at91_spi0_hw_init(unsigned long cs_mask)
66 56 {
67   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
68   -
69 57 at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */
70 58 at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */
71 59 at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */
72 60  
73   - /* Enable clock */
74   - writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
  61 + at91_periph_clk_enable(ATMEL_ID_SPI0);
75 62  
76 63 if (cs_mask & (1 << 0))
77 64 at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
78 65  
... ... @@ -85,14 +72,11 @@
85 72  
86 73 void at91_spi1_hw_init(unsigned long cs_mask)
87 74 {
88   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
89   -
90 75 at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */
91 76 at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */
92 77 at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */
93 78  
94   - /* Enable clock */
95   - writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
  79 + at91_periph_clk_enable(ATMEL_ID_SPI1);
96 80  
97 81 if (cs_mask & (1 << 0))
98 82 at91_set_pio_output(AT91_PIO_PORTA, 8, 1);
... ... @@ -107,8 +91,6 @@
107 91  
108 92 void at91_mci_hw_init(void)
109 93 {
110   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
111   -
112 94 at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* MCCK */
113 95 at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* MCCDA */
114 96 at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* MCDA0 */
115 97  
... ... @@ -116,14 +98,12 @@
116 98 at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* MCDA2 */
117 99 at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* MCDA3 */
118 100  
119   - writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer);
  101 + at91_periph_clk_enable(ATMEL_ID_HSMCI0);
120 102 }
121 103  
122 104 #ifdef CONFIG_LCD
123 105 void at91_lcd_hw_init(void)
124 106 {
125   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
126   -
127 107 at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDPWR */
128 108 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDVSYNC */
129 109 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDHSYNC */
... ... @@ -156,7 +136,7 @@
156 136 at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */
157 137 at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */
158 138  
159   - writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
  139 + at91_periph_clk_enable(ATMEL_ID_LCDC);
160 140 }
161 141 #endif
arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c
Diff comments   View file @ 20680b5
... ... @@ -9,7 +9,7 @@
9 9 #include <common.h>
10 10 #include <asm/io.h>
11 11 #include <asm/arch/at91_common.h>
12   -#include <asm/arch/at91_pmc.h>
  12 +#include <asm/arch/clk.h>
13 13 #include <asm/arch/gpio.h>
14 14  
15 15 /*
16 16  
17 17  
18 18  
19 19  
20 20  
21 21  
22 22  
23 23  
24 24  
... ... @@ -29,51 +29,40 @@
29 29  
30 30 void at91_serial0_hw_init(void)
31 31 {
32   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
33   -
34 32 at91_set_a_periph(AT91_PIO_PORTA, 6, 1); /* TXD0 */
35 33 at91_set_a_periph(AT91_PIO_PORTA, 7, PUP); /* RXD0 */
36   - writel(1 << ATMEL_ID_USART0, &pmc->pcer);
  34 + at91_periph_clk_enable(ATMEL_ID_USART0);
37 35 }
38 36  
39 37 void at91_serial1_hw_init(void)
40 38 {
41   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
42   -
43 39 at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* TXD1 */
44 40 at91_set_a_periph(AT91_PIO_PORTA, 12, PUP); /* RXD1 */
45   - writel(1 << ATMEL_ID_USART1, &pmc->pcer);
  41 + at91_periph_clk_enable(ATMEL_ID_USART1);
46 42 }
47 43  
48 44 void at91_serial2_hw_init(void)
49 45 {
50   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
51   -
52 46 at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* TXD2 */
53 47 at91_set_a_periph(AT91_PIO_PORTA, 14, PUP); /* RXD2 */
54   - writel(1 << ATMEL_ID_USART2, &pmc->pcer);
  48 + at91_periph_clk_enable(ATMEL_ID_USART2);
55 49 }
56 50  
57 51 void at91_seriald_hw_init(void)
58 52 {
59   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
60   -
61 53 at91_set_a_periph(AT91_PIO_PORTA, 21, PUP); /* DRXD */
62 54 at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* DTXD */
63   - writel(1 << ATMEL_ID_SYS, &pmc->pcer);
  55 + at91_periph_clk_enable(ATMEL_ID_SYS);
64 56 }
65 57  
66 58 #if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
67 59 void at91_spi0_hw_init(unsigned long cs_mask)
68 60 {
69   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
70   -
71 61 at91_set_a_periph(AT91_PIO_PORTA, 25, PUP); /* SPI0_MISO */
72 62 at91_set_a_periph(AT91_PIO_PORTA, 26, PUP); /* SPI0_MOSI */
73 63 at91_set_a_periph(AT91_PIO_PORTA, 27, PUP); /* SPI0_SPCK */
74 64  
75   - /* Enable clock */
76   - writel(1 << ATMEL_ID_SPI, &pmc->pcer);
  65 + at91_periph_clk_enable(ATMEL_ID_SPI);
77 66  
78 67 if (cs_mask & (1 << 0)) {
79 68 at91_set_a_periph(AT91_PIO_PORTA, 28, 1);
... ... @@ -105,8 +94,6 @@
105 94 #ifdef CONFIG_GENERIC_ATMEL_MCI
106 95 void at91_mci_hw_init(void)
107 96 {
108   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
109   -
110 97 at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* MCI CLK */
111 98 at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* MCI CDA */
112 99 at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* MCI DA0 */
... ... @@ -114,8 +101,7 @@
114 101 at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* MCI DA2 */
115 102 at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* MCI DA3 */
116 103  
117   - /* Enable clock */
118   - writel(1 << ATMEL_ID_MCI, &pmc->pcer);
  104 + at91_periph_clk_enable(ATMEL_ID_MCI);
119 105 }
120 106 #endif
arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c
Diff comments   View file @ 20680b5
... ... @@ -6,7 +6,7 @@
6 6  
7 7 #include <common.h>
8 8 #include <asm/arch/at91_common.h>
9   -#include <asm/arch/at91_pmc.h>
  9 +#include <asm/arch/clk.h>
10 10 #include <asm/arch/gpio.h>
11 11 #include <asm/io.h>
12 12  
13 13  
14 14  
15 15  
16 16  
17 17  
18 18  
19 19  
... ... @@ -64,42 +64,34 @@
64 64  
65 65 void at91_seriald_hw_init(void)
66 66 {
67   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
68   -
69 67 at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
70 68 at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
71 69  
72   - writel(1 << ATMEL_ID_SYS, &pmc->pcer);
  70 + at91_periph_clk_enable(ATMEL_ID_SYS);
73 71 }
74 72  
75 73 void at91_serial0_hw_init(void)
76 74 {
77   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
78   -
79 75 at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD */
80 76 at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD */
81 77  
82   - writel(1 << ATMEL_ID_USART0, &pmc->pcer);
  78 + at91_periph_clk_enable(ATMEL_ID_USART0);
83 79 }
84 80  
85 81 void at91_serial1_hw_init(void)
86 82 {
87   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
88   -
89 83 at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD */
90 84 at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD */
91 85  
92   - writel(1 << ATMEL_ID_USART1, &pmc->pcer);
  86 + at91_periph_clk_enable(ATMEL_ID_USART1);
93 87 }
94 88  
95 89 void at91_serial2_hw_init(void)
96 90 {
97   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
98   -
99 91 at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD */
100 92 at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD */
101 93  
102   - writel(1 << ATMEL_ID_USART2, &pmc->pcer);
  94 + at91_periph_clk_enable(ATMEL_ID_USART2);
103 95 }
104 96  
105 97 void at91_mci_hw_init(void)
106 98  
107 99  
... ... @@ -112,22 +104,17 @@
112 104 at91_set_a_periph(AT91_PIO_PORTA, 19, 1); /* MCDA2 */
113 105 at91_set_a_periph(AT91_PIO_PORTA, 20, 1); /* MCDA3 */
114 106  
115   - /* Enable clock for MCI0 */
116   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
117   - writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer);
  107 + at91_periph_clk_enable(ATMEL_ID_HSMCI0);
118 108 }
119 109  
120 110 #ifdef CONFIG_ATMEL_SPI
121 111 void at91_spi0_hw_init(unsigned long cs_mask)
122 112 {
123   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
124   -
125 113 at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */
126 114 at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */
127 115 at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */
128 116  
129   - /* Enable clock */
130   - writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
  117 + at91_periph_clk_enable(ATMEL_ID_SPI0);
131 118  
132 119 if (cs_mask & (1 << 0))
133 120 at91_set_a_periph(AT91_PIO_PORTA, 14, 0);
134 121  
... ... @@ -149,14 +136,11 @@
149 136  
150 137 void at91_spi1_hw_init(unsigned long cs_mask)
151 138 {
152   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
153   -
154 139 at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */
155 140 at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */
156 141 at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */
157 142  
158   - /* Enable clock */
159   - writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
  143 + at91_periph_clk_enable(ATMEL_ID_SPI1);
160 144  
161 145 if (cs_mask & (1 << 0))
162 146 at91_set_b_periph(AT91_PIO_PORTA, 8, 0);
163 147  
... ... @@ -193,11 +177,9 @@
193 177 #ifdef CONFIG_MACB
194 178 void at91_macb_hw_init(void)
195 179 {
196   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
197   -
198 180 if (has_emac0()) {
199 181 /* Enable EMAC0 clock */
200   - writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
  182 + at91_periph_clk_enable(ATMEL_ID_EMAC0);
201 183 /* EMAC0 pins setup */
202 184 at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* ETXCK */
203 185 at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* ERXDV */
... ... @@ -213,7 +195,7 @@
213 195  
214 196 if (has_emac1()) {
215 197 /* Enable EMAC1 clock */
216   - writel(1 << ATMEL_ID_EMAC1, &pmc->pcer);
  198 + at91_periph_clk_enable(ATMEL_ID_EMAC1);
217 199 /* EMAC1 pins setup */
218 200 at91_set_b_periph(AT91_PIO_PORTC, 29, 0); /* ETXCK */
219 201 at91_set_b_periph(AT91_PIO_PORTC, 28, 0); /* ECRSDV */
arch/arm/mach-at91/arm926ejs/clock.c
Diff comments   View file @ 20680b5
... ... @@ -18,6 +18,8 @@
18 18 # error You need to define CONFIG_AT91FAMILY in your board config!
19 19 #endif
20 20  
  21 +#define EN_PLLB_TIMEOUT 500
  22 +
21 23 DECLARE_GLOBAL_DATA_PTR;
22 24  
23 25 static unsigned long at91_css_to_rate(unsigned long css)
24 26  
25 27  
... ... @@ -243,10 +245,39 @@
243 245 ;
244 246 }
245 247  
246   -void at91_periph_clk_enable(int id)
  248 +int at91_pllb_clk_enable(u32 pllbr)
247 249 {
248   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  250 + struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
  251 + ulong start_time, tmp_time;
249 252  
250   - writel(1 << id, &pmc->pcer);
  253 + start_time = get_timer(0);
  254 + writel(pllbr, &pmc->pllbr);
  255 + while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) {
  256 + tmp_time = get_timer(0);
  257 + if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
  258 + printf("ERROR: failed to enable PLLB\n");
  259 + return -1;
  260 + }
  261 + }
  262 +
  263 + return 0;
  264 +}
  265 +
  266 +int at91_pllb_clk_disable(void)
  267 +{
  268 + struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
  269 + ulong start_time, tmp_time;
  270 +
  271 + start_time = get_timer(0);
  272 + writel(0, &pmc->pllbr);
  273 + while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) {
  274 + tmp_time = get_timer(0);
  275 + if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
  276 + printf("ERROR: failed to disable PLLB\n");
  277 + return -1;
  278 + }
  279 + }
  280 +
  281 + return 0;
251 282 }
arch/arm/mach-at91/arm926ejs/cpu.c
Diff comments   View file @ 20680b5
... ... @@ -10,7 +10,6 @@
10 10 #include <common.h>
11 11 #include <asm/io.h>
12 12 #include <asm/arch/hardware.h>
13   -#include <asm/arch/at91_pmc.h>
14 13 #include <asm/arch/at91_pit.h>
15 14 #include <asm/arch/at91_gpbr.h>
16 15 #include <asm/arch/clk.h>
arch/arm/mach-at91/arm926ejs/timer.c
Diff comments   View file @ 20680b5
... ... @@ -10,7 +10,6 @@
10 10 #include <asm/io.h>
11 11 #include <asm/arch/hardware.h>
12 12 #include <asm/arch/at91_pit.h>
13   -#include <asm/arch/at91_pmc.h>
14 13 #include <asm/arch/clk.h>
15 14 #include <div64.h>
16 15  
17 16  
... ... @@ -38,11 +37,9 @@
38 37 */
39 38 int timer_init(void)
40 39 {
41   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
42 40 at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT;
43 41  
44   - /* Enable PITC Clock */
45   - writel(1 << ATMEL_ID_SYS, &pmc->pcer);
  42 + at91_periph_clk_enable(ATMEL_ID_SYS);
46 43  
47 44 /* Enable PITC */
48 45 writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
arch/arm/mach-at91/armv7/clock.c
Diff comments   View file @ 20680b5
... ... @@ -150,32 +150,6 @@
150 150 ;
151 151 }
152 152  
153   -void at91_periph_clk_enable(int id)
154   -{
155   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
156   - u32 regval;
157   -
158   - if (id > AT91_PMC_PCR_PID_MASK)
159   - return;
160   -
161   - regval = AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD_WRITE | id;
162   -
163   - writel(regval, &pmc->pcr);
164   -}
165   -
166   -void at91_periph_clk_disable(int id)
167   -{
168   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
169   - u32 regval;
170   -
171   - if (id > AT91_PMC_PCR_PID_MASK)
172   - return;
173   -
174   - regval = AT91_PMC_PCR_CMD_WRITE | id;
175   -
176   - writel(regval, &pmc->pcr);
177   -}
178   -
179 153 int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div)
180 154 {
181 155 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
arch/arm/mach-at91/armv7/cpu.c
Diff comments   View file @ 20680b5
... ... @@ -12,7 +12,6 @@
12 12 #include <common.h>
13 13 #include <asm/io.h>
14 14 #include <asm/arch/hardware.h>
15   -#include <asm/arch/at91_pmc.h>
16 15 #include <asm/arch/at91_pit.h>
17 16 #include <asm/arch/at91_gpbr.h>
18 17 #include <asm/arch/clk.h>
arch/arm/mach-at91/armv7/sama5d2_devices.c
Diff comments   View file @ 20680b5
... ... @@ -7,7 +7,6 @@
7 7  
8 8 #include <common.h>
9 9 #include <asm/io.h>
10   -#include <asm/arch/at91_pmc.h>
11 10 #include <asm/arch/clk.h>
12 11 #include <asm/arch/sama5d2.h>
13 12  
... ... @@ -48,9 +47,7 @@
48 47 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
49 48 void at91_udp_hw_init(void)
50 49 {
51   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
52   -
53   - writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
  50 + at91_upll_clk_enable();
54 51  
55 52 at91_periph_clk_enable(ATMEL_ID_UDPHS);
56 53 }
arch/arm/mach-at91/armv7/sama5d3_devices.c
Diff comments   View file @ 20680b5
... ... @@ -8,7 +8,6 @@
8 8 #include <common.h>
9 9 #include <asm/arch/sama5d3.h>
10 10 #include <asm/arch/at91_common.h>
11   -#include <asm/arch/at91_pmc.h>
12 11 #include <asm/arch/clk.h>
13 12 #include <asm/arch/gpio.h>
14 13 #include <asm/io.h>
15 14  
... ... @@ -208,10 +207,8 @@
208 207 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
209 208 void at91_udp_hw_init(void)
210 209 {
211   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
212   -
213 210 /* Enable UPLL clock */
214   - writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
  211 + at91_upll_clk_enable();
215 212 /* Enable UDPHS clock */
216 213 at91_periph_clk_enable(ATMEL_ID_UDPHS);
217 214 }
arch/arm/mach-at91/armv7/sama5d4_devices.c
Diff comments   View file @ 20680b5
... ... @@ -8,7 +8,6 @@
8 8 #include <common.h>
9 9 #include <asm/io.h>
10 10 #include <asm/arch/at91_common.h>
11   -#include <asm/arch/at91_pmc.h>
12 11 #include <asm/arch/clk.h>
13 12 #include <asm/arch/sama5_sfr.h>
14 13 #include <asm/arch/sama5d4.h>
15 14  
... ... @@ -37,10 +36,8 @@
37 36 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
38 37 void at91_udp_hw_init(void)
39 38 {
40   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
41   -
42 39 /* Enable UPLL clock */
43   - writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
  40 + at91_upll_clk_enable();
44 41 /* Enable UDPHS clock */
45 42 at91_periph_clk_enable(ATMEL_ID_UDPHS);
46 43 }
arch/arm/mach-at91/armv7/timer.c
Diff comments   View file @ 20680b5
... ... @@ -13,7 +13,6 @@
13 13 #include <asm/io.h>
14 14 #include <asm/arch/hardware.h>
15 15 #include <asm/arch/at91_pit.h>
16   -#include <asm/arch/at91_pmc.h>
17 16 #include <asm/arch/clk.h>
18 17 #include <div64.h>
19 18  
arch/arm/mach-at91/atmel_sfr.c
Diff comments   View file @ 20680b5
... ... @@ -19,4 +19,11 @@
19 19 writel((key32 | ATMEL_SFR_AICREDIR_NSAIC), &sfr->aicredir);
20 20 }
21 21 }
  22 +
  23 +void configure_2nd_sram_as_l2_cache(void)
  24 +{
  25 + struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
  26 +
  27 + writel(1, &sfr->l2cc_hramc);
  28 +}
arch/arm/mach-at91/clock.c
Diff comments   View file @ 20680b5
  1 +/*
  2 + * Copyright (C) 2015 Atmel Corporation
  3 + * Wenyou Yang <wenyou.yang@atmel.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <asm/io.h>
  10 +#include <asm/arch/hardware.h>
  11 +#include <asm/arch/at91_pmc.h>
  12 +
  13 +#define EN_UPLL_TIMEOUT 500
  14 +
  15 +void at91_periph_clk_enable(int id)
  16 +{
  17 + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  18 +
  19 +#ifdef CPU_HAS_PCR
  20 + u32 regval;
  21 + u32 div_value;
  22 +
  23 + if (id > AT91_PMC_PCR_PID_MASK)
  24 + return;
  25 +
  26 + writel(id, &pmc->pcr);
  27 +
  28 + div_value = readl(&pmc->pcr) & AT91_PMC_PCR_DIV;
  29 +
  30 + regval = AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD_WRITE | id | div_value;
  31 +
  32 + writel(regval, &pmc->pcr);
  33 +#else
  34 + writel(0x01 << id, &pmc->pcer);
  35 +#endif
  36 +}
  37 +
  38 +void at91_periph_clk_disable(int id)
  39 +{
  40 + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  41 +
  42 +#ifdef CPU_HAS_PCR
  43 + u32 regval;
  44 +
  45 + if (id > AT91_PMC_PCR_PID_MASK)
  46 + return;
  47 +
  48 + regval = AT91_PMC_PCR_CMD_WRITE | id;
  49 +
  50 + writel(regval, &pmc->pcr);
  51 +#else
  52 + writel(0x01 << id, &pmc->pcdr);
  53 +#endif
  54 +}
  55 +
  56 +void at91_system_clk_enable(int sys_clk)
  57 +{
  58 + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  59 +
  60 + writel(sys_clk, &pmc->scer);
  61 +}
  62 +
  63 +void at91_system_clk_disable(int sys_clk)
  64 +{
  65 + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  66 +
  67 + writel(sys_clk, &pmc->scdr);
  68 +}
  69 +
  70 +int at91_upll_clk_enable(void)
  71 +{
  72 + struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
  73 + ulong start_time, tmp_time;
  74 +
  75 + if ((readl(&pmc->uckr) & AT91_PMC_UPLLEN) == AT91_PMC_UPLLEN)
  76 + return 0;
  77 +
  78 + start_time = get_timer(0);
  79 + writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
  80 + while ((readl(&pmc->sr) & AT91_PMC_LOCKU) != AT91_PMC_LOCKU) {
  81 + tmp_time = get_timer(0);
  82 + if ((tmp_time - start_time) > EN_UPLL_TIMEOUT) {
  83 + printf("ERROR: failed to enable UPLL\n");
  84 + return -1;
  85 + }
  86 + }
  87 +
  88 + return 0;
  89 +}
  90 +
  91 +int at91_upll_clk_disable(void)
  92 +{
  93 + struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
  94 + ulong start_time, tmp_time;
  95 +
  96 + start_time = get_timer(0);
  97 + writel(readl(&pmc->uckr) & ~AT91_PMC_UPLLEN, &pmc->uckr);
  98 + while ((readl(&pmc->sr) & AT91_PMC_LOCKU) == AT91_PMC_LOCKU) {
  99 + tmp_time = get_timer(0);
  100 + if ((tmp_time - start_time) > EN_UPLL_TIMEOUT) {
  101 + printf("ERROR: failed to stop UPLL\n");
  102 + return -1;
  103 + }
  104 + }
  105 +
  106 + return 0;
  107 +}
  108 +
  109 +void at91_usb_clk_init(u32 value)
  110 +{
  111 + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  112 +
  113 + writel(value, &pmc->usb);
  114 +}
  115 +
  116 +void at91_pllicpr_init(u32 icpr)
  117 +{
  118 + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  119 +
  120 + writel(icpr, &pmc->pllicpr);
  121 +}
arch/arm/mach-at91/include/mach/at91_common.h
Diff comments   View file @ 20680b5
... ... @@ -34,6 +34,7 @@
34 34 void at91_disable_wdt(void);
35 35 void matrix_init(void);
36 36 void redirect_int_from_saic_to_aic(void);
  37 +void configure_2nd_sram_as_l2_cache(void);
37 38  
38 39 #endif /* AT91_COMMON_H */
arch/arm/mach-at91/include/mach/at91_pmc.h
Diff comments   View file @ 20680b5
... ... @@ -51,19 +51,15 @@
51 51 u32 imr; /* 0x6C Interrupt Mask Register */
52 52 u32 reserved4[4];
53 53 u32 pllicpr; /* 0x80 Change Pump Current Register (SAM9) */
54   - u32 reserved5[21];
  54 + u32 reserved5[24];
55 55 u32 wpmr; /* 0xE4 Write Protect Mode Register (CAP0) */
56 56 u32 wpsr; /* 0xE8 Write Protect Status Register (CAP0) */
57   -#ifdef CPU_HAS_PCR
58   - u32 reserved6[8];
  57 + u32 reserved6[5];
59 58 u32 pcer1; /* 0x100 Periperial Clock Enable Register 1 */
60 59 u32 pcdr1; /* 0x104 Periperial Clock Disable Register 1 */
61 60 u32 pcsr1; /* 0x108 Periperial Clock Status Register 1 */
62 61 u32 pcr; /* 0x10c Periperial Control Register */
63 62 u32 ocr; /* 0x110 Oscillator Calibration Register */
64   -#else
65   - u32 reserved8[5];
66   -#endif
67 63 } at91_pmc_t;
68 64  
69 65 #endif /* end not assembly */
... ... @@ -250,5 +246,12 @@
250 246 #define AT91_PMC_GCKRDY (1 << 24)
251 247  
252 248 #define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
  249 +
  250 +/* PLL Charge Pump Current Register (PMC_PLLICPR) */
  251 +#define AT91_PMC_ICP_PLLA(x) (((x) & 0x3) << 0)
  252 +#define AT91_PMC_IPLL_PLLA(x) (((x) & 0x7) << 8)
  253 +#define AT91_PMC_ICP_PLLU(x) (((x) & 0x3) << 16)
  254 +#define AT91_PMC_IVCO_PLLU(x) (((x) & 0x3) << 24)
  255 +
253 256 #endif
arch/arm/mach-at91/include/mach/clk.h
Diff comments   View file @ 20680b5
... ... @@ -128,6 +128,14 @@
128 128 void at91_periph_clk_disable(int id);
129 129 int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div);
130 130 u32 at91_get_periph_generated_clk(u32 id);
  131 +void at91_system_clk_enable(int sys_clk);
  132 +void at91_system_clk_disable(int sys_clk);
  133 +int at91_upll_clk_enable(void);
  134 +int at91_upll_clk_disable(void);
  135 +void at91_usb_clk_init(u32 value);
  136 +int at91_pllb_clk_enable(u32 pllbr);
  137 +int at91_pllb_clk_disable(void);
  138 +void at91_pllicpr_init(u32 icpr);
131 139  
132 140 #endif /* __ASM_ARM_ARCH_CLK_H__ */
arch/arm/mach-at91/include/mach/sama5_sfr.h
Diff comments   View file @ 20680b5
... ... @@ -25,6 +25,7 @@
25 25 u32 sn0; /* 0x4c */
26 26 u32 sn1; /* 0x50 */
27 27 u32 aicredir; /* 0x54 */
  28 + u32 l2cc_hramc; /* 0x58 */
28 29 };
29 30  
30 31 /* Bit field in DDRCFG */
arch/arm/mach-at91/phy.c
Diff comments   View file @ 20680b5
... ... @@ -15,7 +15,6 @@
15 15 #include <common.h>
16 16 #include <asm/io.h>
17 17 #include <linux/sizes.h>
18   -#include <asm/arch/at91_pmc.h>
19 18 #include <asm/arch/at91_rstc.h>
20 19 #include <watchdog.h>
21 20  
arch/arm/mach-at91/sdram.c
Diff comments   View file @ 20680b5
... ... @@ -13,7 +13,6 @@
13 13 #include <common.h>
14 14 #include <asm/io.h>
15 15 #include <asm/arch/at91_common.h>
16   -#include <asm/arch/at91_pmc.h>
17 16 #include <asm/arch/at91sam9_sdramc.h>
18 17 #include <asm/arch/gpio.h>
19 18  
arch/arm/mach-at91/spl_at91.c
Diff comments   View file @ 20680b5
... ... @@ -14,7 +14,6 @@
14 14 #include <asm/arch/at91_common.h>
15 15 #include <asm/arch/at91sam9_matrix.h>
16 16 #include <asm/arch/at91_pit.h>
17   -#include <asm/arch/at91_pmc.h>
18 17 #include <asm/arch/at91_rstc.h>
19 18 #include <asm/arch/at91_wdt.h>
20 19 #include <asm/arch/clk.h>
... ... @@ -77,8 +76,6 @@
77 76  
78 77 void board_init_f(ulong dummy)
79 78 {
80   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
81   -
82 79 lowlevel_clock_init();
83 80 at91_disable_wdt();
84 81  
... ... @@ -86,7 +83,7 @@
86 83 * At this stage the main oscillator is supposed to be enabled
87 84 * PCK = MCK = MOSC
88 85 */
89   - writel(0x00, &pmc->pllicpr);
  86 + at91_pllicpr_init(0x00);
90 87  
91 88 /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
92 89 at91_plla_init(CONFIG_SYS_AT91_PLLA);
arch/arm/mach-at91/spl_atmel.c
Diff comments   View file @ 20680b5
... ... @@ -79,6 +79,10 @@
79 79 {
80 80 switch_to_main_crystal_osc();
81 81  
  82 +#ifdef CONFIG_SAMA5D2
  83 + configure_2nd_sram_as_l2_cache();
  84 +#endif
  85 +
82 86 /* disable watchdog */
83 87 at91_disable_wdt();
84 88  
board/atmel/at91rm9200ek/at91rm9200ek.c
Diff comments   View file @ 20680b5
... ... @@ -14,7 +14,6 @@
14 14 #include <netdev.h>
15 15 #include <asm/arch/hardware.h>
16 16 #include <asm/arch/at91_pio.h>
17   -#include <asm/arch/at91_pmc.h>
18 17 #include <asm/arch/at91_common.h>
19 18 #include <asm/io.h>
20 19  
board/atmel/at91rm9200ek/led.c
Diff comments   View file @ 20680b5
... ... @@ -12,7 +12,7 @@
12 12 #include <common.h>
13 13 #include <asm/io.h>
14 14 #include <asm/arch/hardware.h>
15   -#include <asm/arch/at91_pmc.h>
  15 +#include <asm/arch/clk.h>
16 16 #include <asm/arch/at91_pio.h>
17 17 #include <status_led.h>
18 18  
19 19  
... ... @@ -59,11 +59,9 @@
59 59  
60 60 void coloured_LED_init (void)
61 61 {
62   - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
63 62 at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
64 63  
65   - /* Enable PIOB clock */
66   - writel(1 << ATMEL_ID_PIOB, &pmc->pcer);
  64 + at91_periph_clk_enable(ATMEL_ID_PIOB);
67 65  
68 66 /* Disable peripherals on LEDs */
69 67 writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.per);
board/atmel/at91sam9260ek/at91sam9260ek.c
Diff comments   View file @ 20680b5
... ... @@ -11,7 +11,7 @@
11 11 #include <asm/arch/at91sam9260_matrix.h>
12 12 #include <asm/arch/at91sam9_smc.h>
13 13 #include <asm/arch/at91_common.h>
14   -#include <asm/arch/at91_pmc.h>
  14 +#include <asm/arch/clk.h>
15 15 #include <asm/arch/gpio.h>
16 16 #include <atmel_mci.h>
17 17  
18 18  
... ... @@ -70,11 +70,9 @@
70 70 #ifdef CONFIG_MACB
71 71 static void at91sam9260ek_macb_hw_init(void)
72 72 {
73   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
74 73 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
75 74  
76   - /* Enable EMAC clock */
77   - writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
  75 + at91_periph_clk_enable(ATMEL_ID_EMAC0);
78 76  
79 77 /*
80 78 * Disable pull-up on:
... ... @@ -122,12 +120,9 @@
122 120  
123 121 int board_early_init_f(void)
124 122 {
125   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
126   -
127   - /* Enable clocks for all PIOs */
128   - writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
129   - (1 << ATMEL_ID_PIOC),
130   - &pmc->pcer);
  123 + at91_periph_clk_enable(ATMEL_ID_PIOA);
  124 + at91_periph_clk_enable(ATMEL_ID_PIOB);
  125 + at91_periph_clk_enable(ATMEL_ID_PIOC);
131 126  
132 127 return 0;
133 128 }
board/atmel/at91sam9261ek/at91sam9261ek.c
Diff comments   View file @ 20680b5
... ... @@ -12,7 +12,6 @@
12 12 #include <asm/arch/at91sam9261_matrix.h>
13 13 #include <asm/arch/at91sam9_smc.h>
14 14 #include <asm/arch/at91_common.h>
15   -#include <asm/arch/at91_pmc.h>
16 15 #include <asm/arch/at91_rstc.h>
17 16 #include <asm/arch/clk.h>
18 17 #include <asm/arch/gpio.h>
... ... @@ -35,7 +34,6 @@
35 34 {
36 35 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
37 36 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
38   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
39 37 unsigned long csa;
40 38  
41 39 /* Enable CS3 */
... ... @@ -74,7 +72,7 @@
74 72 AT91_SMC_MODE_TDF_CYCLE(2),
75 73 &smc->cs[3].mode);
76 74  
77   - writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
  75 + at91_periph_clk_enable(ATMEL_ID_PIOC);
78 76  
79 77 /* Configure RDY/BSY */
80 78 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
... ... @@ -161,8 +159,6 @@
161 159  
162 160 static void at91sam9261ek_lcd_hw_init(void)
163 161 {
164   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
165   -
166 162 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
167 163 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
168 164 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
... ... @@ -186,7 +182,7 @@
186 182 at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
187 183 at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
188 184  
189   - writel(AT91_PMC_HCK1, &pmc->scer);
  185 + at91_system_clk_enable(AT91_PMC_HCK1);
190 186  
191 187 /* For 9G10EK, let U-Boot allocate the framebuffer in SDRAM */
192 188 #ifdef CONFIG_AT91SAM9261EK
board/atmel/at91sam9261ek/led.c
Diff comments   View file @ 20680b5
... ... @@ -8,17 +8,15 @@
8 8  
9 9 #include <common.h>
10 10 #include <asm/arch/at91sam9261.h>
11   -#include <asm/arch/at91_pmc.h>
12 11 #include <asm/arch/gpio.h>
13 12 #include <asm/arch/at91_pio.h>
  13 +#include <asm/arch/clk.h>
14 14 #include <asm/io.h>
15 15  
16 16 void coloured_LED_init(void)
17 17 {
18   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
19   -
20 18 /* Enable clock */
21   - writel(ATMEL_ID_PIOA, &pmc->pcer);
  19 + at91_periph_clk_enable(ATMEL_ID_PIOA);
22 20  
23 21 at91_set_gpio_output(CONFIG_RED_LED, 1);
24 22 at91_set_gpio_output(CONFIG_GREEN_LED, 1);
board/atmel/at91sam9263ek/at91sam9263ek.c
Diff comments   View file @ 20680b5
... ... @@ -11,7 +11,6 @@
11 11 #include <asm/arch/at91sam9263.h>
12 12 #include <asm/arch/at91sam9_smc.h>
13 13 #include <asm/arch/at91_common.h>
14   -#include <asm/arch/at91_pmc.h>
15 14 #include <asm/arch/at91_matrix.h>
16 15 #include <asm/arch/at91_pio.h>
17 16 #include <asm/arch/clk.h>
... ... @@ -39,7 +38,6 @@
39 38 unsigned long csa;
40 39 at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
41 40 at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
42   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
43 41  
44 42 /* Enable CS3 */
45 43 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
... ... @@ -68,8 +66,8 @@
68 66 AT91_SMC_MODE_TDF_CYCLE(2),
69 67 &smc->cs[3].mode);
70 68  
71   - writel(1 << ATMEL_ID_PIOA | 1 << ATMEL_ID_PIOCDE,
72   - &pmc->pcer);
  69 + at91_periph_clk_enable(ATMEL_ID_PIOA);
  70 + at91_periph_clk_enable(ATMEL_ID_PIOCDE);
73 71  
74 72 /* Configure RDY/BSY */
75 73 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
76 74  
... ... @@ -82,11 +80,9 @@
82 80 #ifdef CONFIG_MACB
83 81 static void at91sam9263ek_macb_hw_init(void)
84 82 {
85   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
86 83 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
87 84  
88   - /* Enable clock */
89   - writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
  85 + at91_periph_clk_enable(ATMEL_ID_EMAC);
90 86  
91 87 /*
92 88 * Disable pull-up on:
... ... @@ -139,8 +135,6 @@
139 135  
140 136 static void at91sam9263ek_lcd_hw_init(void)
141 137 {
142   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
143   -
144 138 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
145 139 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
146 140 at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
... ... @@ -164,7 +158,7 @@
164 158 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
165 159 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
166 160  
167   - writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
  161 + at91_periph_clk_enable(ATMEL_ID_LCDC);
168 162 gd->fb_base = ATMEL_BASE_SRAM0;
169 163 }
170 164  
... ... @@ -226,12 +220,9 @@
226 220  
227 221 int board_early_init_f(void)
228 222 {
229   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
230   -
231   - /* Enable clocks for all PIOs */
232   - writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
233   - (1 << ATMEL_ID_PIOCDE),
234   - &pmc->pcer);
  223 + at91_periph_clk_enable(ATMEL_ID_PIOA);
  224 + at91_periph_clk_enable(ATMEL_ID_PIOB);
  225 + at91_periph_clk_enable(ATMEL_ID_PIOCDE);
235 226  
236 227 at91_seriald_hw_init();
237 228 return 0;
board/atmel/at91sam9263ek/led.c
Diff comments   View file @ 20680b5
... ... @@ -9,16 +9,13 @@
9 9 #include <common.h>
10 10 #include <asm/io.h>
11 11 #include <asm/arch/gpio.h>
12   -#include <asm/arch/at91_pmc.h>
13 12 #include <asm/arch/at91sam9263.h>
  13 +#include <asm/arch/clk.h>
14 14  
15 15 void coloured_LED_init(void)
16 16 {
17   - /* Enable clock */
18   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
19   -
20   - writel(1 << ATMEL_ID_PIOB | 1 << ATMEL_ID_PIOCDE,
21   - &pmc->pcer);
  17 + at91_periph_clk_enable(ATMEL_ID_PIOB);
  18 + at91_periph_clk_enable(ATMEL_ID_PIOB);
22 19  
23 20 at91_set_gpio_output(CONFIG_RED_LED, 1);
24 21 at91_set_gpio_output(CONFIG_GREEN_LED, 1);
board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
Diff comments   View file @ 20680b5
... ... @@ -12,7 +12,6 @@
12 12 #include <asm/arch/at91sam9g45_matrix.h>
13 13 #include <asm/arch/at91sam9_smc.h>
14 14 #include <asm/arch/at91_common.h>
15   -#include <asm/arch/at91_pmc.h>
16 15 #include <asm/arch/gpio.h>
17 16 #include <asm/arch/clk.h>
18 17 #include <lcd.h>
... ... @@ -36,7 +35,6 @@
36 35 {
37 36 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
38 37 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
39   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
40 38 unsigned long csa;
41 39  
42 40 /* Enable CS3 */
... ... @@ -63,7 +61,7 @@
63 61 AT91_SMC_MODE_TDF_CYCLE(3),
64 62 &smc->cs[3].mode);
65 63  
66   - writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
  64 + at91_periph_clk_enable(ATMEL_ID_PIOC);
67 65  
68 66 /* Configure RDY/BSY */
69 67 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
70 68  
... ... @@ -130,13 +128,11 @@
130 128  
131 129 void mem_init(void)
132 130 {
133   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
134 131 struct atmel_mpddrc_config ddr2;
135 132  
136 133 ddr2_conf(&ddr2);
137 134  
138   - /* enable DDR2 clock */
139   - writel(AT91_PMC_DDR, &pmc->scer);
  135 + at91_system_clk_enable(AT91_PMC_DDR);
140 136  
141 137 /* DDRAM2 Controller initialize */
142 138 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
143 139  
... ... @@ -146,10 +142,8 @@
146 142 #ifdef CONFIG_CMD_USB
147 143 static void at91sam9m10g45ek_usb_hw_init(void)
148 144 {
149   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  145 + at91_periph_clk_enable(ATMEL_ID_PIODE);
150 146  
151   - writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
152   -
153 147 at91_set_gpio_output(AT91_PIN_PD1, 0);
154 148 at91_set_gpio_output(AT91_PIN_PD3, 0);
155 149 }
156 150  
... ... @@ -158,11 +152,9 @@
158 152 #ifdef CONFIG_MACB
159 153 static void at91sam9m10g45ek_macb_hw_init(void)
160 154 {
161   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
162 155 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
163 156  
164   - /* Enable clock */
165   - writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
  157 + at91_periph_clk_enable(ATMEL_ID_EMAC);
166 158  
167 159 /*
168 160 * Disable pull-up on:
... ... @@ -222,8 +214,6 @@
222 214  
223 215 static void at91sam9m10g45ek_lcd_hw_init(void)
224 216 {
225   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
226   -
227 217 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
228 218 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
229 219 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
... ... @@ -255,7 +245,7 @@
255 245 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
256 246 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
257 247  
258   - writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
  248 + at91_periph_clk_enable(ATMEL_ID_LCDC);
259 249  
260 250 gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
261 251 }
board/atmel/at91sam9m10g45ek/led.c
Diff comments   View file @ 20680b5
... ... @@ -9,15 +9,12 @@
9 9 #include <common.h>
10 10 #include <asm/io.h>
11 11 #include <asm/arch/at91sam9g45.h>
12   -#include <asm/arch/at91_pmc.h>
  12 +#include <asm/arch/clk.h>
13 13 #include <asm/arch/gpio.h>
14 14  
15 15 void coloured_LED_init(void)
16 16 {
17   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
18   -
19   - /* Enable clock */
20   - writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
  17 + at91_periph_clk_enable(ATMEL_ID_PIODE);
21 18  
22 19 at91_set_gpio_output(CONFIG_RED_LED, 1);
23 20 at91_set_gpio_output(CONFIG_GREEN_LED, 1);
board/atmel/at91sam9n12ek/at91sam9n12ek.c
Diff comments   View file @ 20680b5
... ... @@ -10,7 +10,6 @@
10 10 #include <asm/arch/at91sam9x5_matrix.h>
11 11 #include <asm/arch/at91sam9_smc.h>
12 12 #include <asm/arch/at91_common.h>
13   -#include <asm/arch/at91_pmc.h>
14 13 #include <asm/arch/at91_rstc.h>
15 14 #include <asm/arch/at91_pio.h>
16 15 #include <asm/arch/clk.h>
... ... @@ -208,9 +207,8 @@
208 207  
209 208 int board_early_init_f(void)
210 209 {
211   - /* Enable clocks for all PIOs */
212   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
213   - writel((1 << ATMEL_ID_PIOAB) | (1 << ATMEL_ID_PIOCD), &pmc->pcer);
  210 + at91_periph_clk_enable(ATMEL_ID_PIOAB);
  211 + at91_periph_clk_enable(ATMEL_ID_PIOCD);
214 212  
215 213 at91_seriald_hw_init();
216 214 return 0;
board/atmel/at91sam9rlek/at91sam9rlek.c
Diff comments   View file @ 20680b5
... ... @@ -12,7 +12,6 @@
12 12 #include <asm/arch/at91sam9rl_matrix.h>
13 13 #include <asm/arch/at91sam9_smc.h>
14 14 #include <asm/arch/at91_common.h>
15   -#include <asm/arch/at91_pmc.h>
16 15 #include <asm/arch/at91_rstc.h>
17 16 #include <asm/arch/clk.h>
18 17 #include <asm/arch/gpio.h>
... ... @@ -36,7 +35,6 @@
36 35 {
37 36 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
38 37 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
39   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
40 38 unsigned long csa;
41 39  
42 40 /* Enable CS3 */
... ... @@ -64,7 +62,7 @@
64 62 AT91_SMC_MODE_TDF_CYCLE(2),
65 63 &smc->cs[3].mode);
66 64  
67   - writel(1 << ATMEL_ID_PIOD, &pmc->pcer);
  65 + at91_periph_clk_enable(ATMEL_ID_PIOD);
68 66  
69 67 /* Configure RDY/BSY */
70 68 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
... ... @@ -106,8 +104,6 @@
106 104 }
107 105 static void at91sam9rlek_lcd_hw_init(void)
108 106 {
109   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
110   -
111 107 at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
112 108 at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
113 109 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
... ... @@ -130,7 +126,7 @@
130 126 at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */
131 127 at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */
132 128  
133   - writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
  129 + at91_periph_clk_enable(ATMEL_ID_LCDC);
134 130 }
135 131  
136 132 #ifdef CONFIG_LCD_INFO
... ... @@ -174,12 +170,10 @@
174 170  
175 171 int board_early_init_f(void)
176 172 {
177   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
178   -
179   - /* Enable clocks for all PIOs */
180   - writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
181   - (1 << ATMEL_ID_PIOC) | (1 << ATMEL_ID_PIOD),
182   - &pmc->pcer);
  173 + at91_periph_clk_enable(ATMEL_ID_PIOA);
  174 + at91_periph_clk_enable(ATMEL_ID_PIOB);
  175 + at91_periph_clk_enable(ATMEL_ID_PIOC);
  176 + at91_periph_clk_enable(ATMEL_ID_PIOD);
183 177  
184 178 return 0;
185 179 }
board/atmel/at91sam9rlek/led.c
Diff comments   View file @ 20680b5
... ... @@ -8,16 +8,13 @@
8 8  
9 9 #include <common.h>
10 10 #include <asm/arch/at91sam9rl.h>
11   -#include <asm/arch/at91_pmc.h>
  11 +#include <asm/arch/clk.h>
12 12 #include <asm/arch/gpio.h>
13 13 #include <asm/io.h>
14 14  
15 15 void coloured_LED_init(void)
16 16 {
17   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
18   -
19   - /* Enable clock */
20   - writel(ATMEL_ID_PIOD, &pmc->pcer);
  17 + at91_periph_clk_enable(ATMEL_ID_PIOD);
21 18  
22 19 at91_set_gpio_output(CONFIG_RED_LED, 1);
23 20 at91_set_gpio_output(CONFIG_GREEN_LED, 1);
board/atmel/at91sam9x5ek/at91sam9x5ek.c
Diff comments   View file @ 20680b5
... ... @@ -9,10 +9,9 @@
9 9 #include <asm/arch/at91sam9x5_matrix.h>
10 10 #include <asm/arch/at91sam9_smc.h>
11 11 #include <asm/arch/at91_common.h>
12   -#include <asm/arch/at91_pmc.h>
13 12 #include <asm/arch/at91_rstc.h>
14   -#include <asm/arch/gpio.h>
15 13 #include <asm/arch/clk.h>
  14 +#include <asm/arch/gpio.h>
16 15 #include <lcd.h>
17 16 #include <atmel_hlcdc.h>
18 17 #include <atmel_mci.h>
... ... @@ -39,7 +38,6 @@
39 38 {
40 39 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
41 40 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
42   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
43 41 unsigned long csa;
44 42  
45 43 /* Enable CS3 */
... ... @@ -72,7 +70,7 @@
72 70 AT91_SMC_MODE_TDF_CYCLE(1),
73 71 &smc->cs[3].mode);
74 72  
75   - writel(1 << ATMEL_ID_PIOCD, &pmc->pcer);
  73 + at91_periph_clk_enable(ATMEL_ID_PIOCD);
76 74  
77 75 /* Configure RDY/BSY */
78 76 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
... ... @@ -141,8 +139,6 @@
141 139  
142 140 static void at91sam9x5ek_lcd_hw_init(void)
143 141 {
144   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
145   -
146 142 if (has_lcdc()) {
147 143 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDPWM */
148 144 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDVSYNC */
... ... @@ -176,7 +172,7 @@
176 172 at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */
177 173 at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */
178 174  
179   - writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
  175 + at91_periph_clk_enable(ATMEL_ID_LCDC);
180 176 }
181 177 }
182 178  
board/atmel/sama5d2_xplained/sama5d2_xplained.c
Diff comments   View file @ 20680b5
... ... @@ -15,7 +15,6 @@
15 15 #include <version.h>
16 16 #include <asm/io.h>
17 17 #include <asm/arch/at91_common.h>
18   -#include <asm/arch/at91_pmc.h>
19 18 #include <asm/arch/atmel_pio4.h>
20 19 #include <asm/arch/atmel_mpddrc.h>
21 20 #include <asm/arch/atmel_usba_udc.h>
board/atmel/sama5d3_xplained/sama5d3_xplained.c
Diff comments   View file @ 20680b5
... ... @@ -10,7 +10,6 @@
10 10 #include <asm/io.h>
11 11 #include <asm/arch/sama5d3_smc.h>
12 12 #include <asm/arch/at91_common.h>
13   -#include <asm/arch/at91_pmc.h>
14 13 #include <asm/arch/at91_rstc.h>
15 14 #include <asm/arch/gpio.h>
16 15 #include <asm/arch/clk.h>
17 16  
18 17  
... ... @@ -184,14 +183,13 @@
184 183  
185 184 void mem_init(void)
186 185 {
187   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
188 186 struct atmel_mpddrc_config ddr2;
189 187  
190 188 ddr2_conf(&ddr2);
191 189  
192   - /* enable MPDDR clock */
  190 + /* Enable MPDDR clock */
193 191 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
194   - writel(AT91_PMC_DDR, &pmc->scer);
  192 + at91_system_clk_enable(AT91_PMC_DDR);
195 193  
196 194 /* DDRAM2 Controller initialize */
197 195 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
... ... @@ -199,7 +197,6 @@
199 197  
200 198 void at91_pmc_init(void)
201 199 {
202   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
203 200 u32 tmp;
204 201  
205 202 tmp = AT91_PMC_PLLAR_29 |
... ... @@ -208,7 +205,7 @@
208 205 AT91_PMC_PLLXR_DIV(1);
209 206 at91_plla_init(tmp);
210 207  
211   - writel(0x3 << 8, &pmc->pllicpr);
  208 + at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
212 209  
213 210 tmp = AT91_PMC_MCKR_MDIV_4 |
214 211 AT91_PMC_MCKR_CSS_PLLA;
board/atmel/sama5d3xek/sama5d3xek.c
Diff comments   View file @ 20680b5
... ... @@ -10,7 +10,6 @@
10 10 #include <asm/io.h>
11 11 #include <asm/arch/sama5d3_smc.h>
12 12 #include <asm/arch/at91_common.h>
13   -#include <asm/arch/at91_pmc.h>
14 13 #include <asm/arch/at91_rstc.h>
15 14 #include <asm/arch/gpio.h>
16 15 #include <asm/arch/clk.h>
17 16  
18 17  
... ... @@ -443,14 +442,13 @@
443 442  
444 443 void mem_init(void)
445 444 {
446   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
447 445 struct atmel_mpddrc_config ddr2;
448 446  
449 447 ddr2_conf(&ddr2);
450 448  
451   - /* enable MPDDR clock */
  449 + /* Enable MPDDR clock */
452 450 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
453   - writel(AT91_PMC_DDR, &pmc->scer);
  451 + at91_system_clk_enable(AT91_PMC_DDR);
454 452  
455 453 /* DDRAM2 Controller initialize */
456 454 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
... ... @@ -458,7 +456,6 @@
458 456  
459 457 void at91_pmc_init(void)
460 458 {
461   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
462 459 u32 tmp;
463 460  
464 461 tmp = AT91_PMC_PLLAR_29 |
... ... @@ -467,7 +464,7 @@
467 464 AT91_PMC_PLLXR_DIV(1);
468 465 at91_plla_init(tmp);
469 466  
470   - writel(0x3 << 8, &pmc->pllicpr);
  467 + at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
471 468  
472 469 tmp = AT91_PMC_MCKR_MDIV_4 |
473 470 AT91_PMC_MCKR_CSS_PLLA;
board/atmel/sama5d4_xplained/sama5d4_xplained.c
Diff comments   View file @ 20680b5
... ... @@ -8,7 +8,6 @@
8 8 #include <common.h>
9 9 #include <asm/io.h>
10 10 #include <asm/arch/at91_common.h>
11   -#include <asm/arch/at91_pmc.h>
12 11 #include <asm/arch/at91_rstc.h>
13 12 #include <asm/arch/atmel_mpddrc.h>
14 13 #include <asm/arch/atmel_usba_udc.h>
15 14  
16 15  
... ... @@ -383,14 +382,13 @@
383 382  
384 383 void mem_init(void)
385 384 {
386   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
387 385 struct atmel_mpddrc_config ddr2;
388 386  
389 387 ddr2_conf(&ddr2);
390 388  
391   - /* enable MPDDR clock */
  389 + /* Enable MPDDR clock */
392 390 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
393   - writel(AT91_PMC_DDR, &pmc->scer);
  391 + at91_system_clk_enable(AT91_PMC_DDR);
394 392  
395 393 /* DDRAM2 Controller initialize */
396 394 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
... ... @@ -398,7 +396,6 @@
398 396  
399 397 void at91_pmc_init(void)
400 398 {
401   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
402 399 u32 tmp;
403 400  
404 401 tmp = AT91_PMC_PLLAR_29 |
... ... @@ -407,7 +404,7 @@
407 404 AT91_PMC_PLLXR_DIV(1);
408 405 at91_plla_init(tmp);
409 406  
410   - writel(0x0 << 8, &pmc->pllicpr);
  407 + at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0));
411 408  
412 409 tmp = AT91_PMC_MCKR_H32MXDIV |
413 410 AT91_PMC_MCKR_PLLADIV_2 |
board/atmel/sama5d4ek/sama5d4ek.c
Diff comments   View file @ 20680b5
... ... @@ -8,7 +8,6 @@
8 8 #include <common.h>
9 9 #include <asm/io.h>
10 10 #include <asm/arch/at91_common.h>
11   -#include <asm/arch/at91_pmc.h>
12 11 #include <asm/arch/at91_rstc.h>
13 12 #include <asm/arch/atmel_mpddrc.h>
14 13 #include <asm/arch/atmel_usba_udc.h>
15 14  
16 15  
... ... @@ -379,14 +378,13 @@
379 378  
380 379 void mem_init(void)
381 380 {
382   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
383 381 struct atmel_mpddrc_config ddr2;
384 382  
385 383 ddr2_conf(&ddr2);
386 384  
387   - /* enable MPDDR clock */
  385 + /* Enable MPDDR clock */
388 386 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
389   - writel(AT91_PMC_DDR, &pmc->scer);
  387 + at91_system_clk_enable(AT91_PMC_DDR);
390 388  
391 389 /* DDRAM2 Controller initialize */
392 390 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
... ... @@ -394,7 +392,6 @@
394 392  
395 393 void at91_pmc_init(void)
396 394 {
397   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
398 395 u32 tmp;
399 396  
400 397 tmp = AT91_PMC_PLLAR_29 |
... ... @@ -403,7 +400,7 @@
403 400 AT91_PMC_PLLXR_DIV(1);
404 401 at91_plla_init(tmp);
405 402  
406   - writel(0x0 << 8, &pmc->pllicpr);
  403 + at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0));
407 404  
408 405 tmp = AT91_PMC_MCKR_H32MXDIV |
409 406 AT91_PMC_MCKR_PLLADIV_2 |
board/bluewater/snapper9260/snapper9260.c
Diff comments   View file @ 20680b5
... ... @@ -15,7 +15,7 @@
15 15 #include <asm/arch/at91sam9260_matrix.h>
16 16 #include <asm/arch/at91sam9_smc.h>
17 17 #include <asm/arch/at91_common.h>
18   -#include <asm/arch/at91_pmc.h>
  18 +#include <asm/arch/clk.h>
19 19 #include <asm/arch/gpio.h>
20 20 #include <asm/arch/atmel_serial.h>
21 21 #include <net.h>
22 22  
... ... @@ -31,11 +31,9 @@
31 31  
32 32 static void macb_hw_init(void)
33 33 {
34   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
35 34 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
36 35  
37   - /* Enable clock */
38   - writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
  36 + at91_periph_clk_enable(ATMEL_ID_EMAC0);
39 37  
40 38 /* Disable pull-ups to prevent PHY going into test mode */
41 39 writel(pin_to_mask(AT91_PIN_PA14) |
... ... @@ -108,12 +106,9 @@
108 106  
109 107 int board_init(void)
110 108 {
111   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
112   -
113   - /* Enable PIO clocks */
114   - writel((1 << ATMEL_ID_PIOA) |
115   - (1 << ATMEL_ID_PIOB) |
116   - (1 << ATMEL_ID_PIOC), &pmc->pcer);
  109 + at91_periph_clk_enable(ATMEL_ID_PIOA);
  110 + at91_periph_clk_enable(ATMEL_ID_PIOB);
  111 + at91_periph_clk_enable(ATMEL_ID_PIOC);
117 112  
118 113 /* The mach-type is the same for both Snapper 9260 and 9G20 */
119 114 gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;
board/calao/usb_a9263/usb_a9263.c
Diff comments   View file @ 20680b5
... ... @@ -12,7 +12,7 @@
12 12 #include <asm/arch/at91sam9_smc.h>
13 13 #include <asm/arch/at91_common.h>
14 14 #include <asm/arch/at91_matrix.h>
15   -#include <asm/arch/at91_pmc.h>
  15 +#include <asm/arch/clk.h>
16 16 #include <asm/arch/gpio.h>
17 17 #include <asm-generic/gpio.h>
18 18 #include <asm/io.h>
... ... @@ -43,7 +43,6 @@
43 43 unsigned long csa;
44 44 at91_smc_t *smc = (at91_smc_t *)ATMEL_BASE_SMC0;
45 45 at91_matrix_t *matrix = (at91_matrix_t *)ATMEL_BASE_MATRIX;
46   - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
47 46  
48 47 /* Enable CS3 */
49 48 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
... ... @@ -66,7 +65,8 @@
66 65 AT91_SMC_MODE_DBW_8 |
67 66 AT91_SMC_MODE_TDF_CYCLE(2), &smc->cs[3].mode);
68 67  
69   - writel(1 << ATMEL_ID_PIOA | 1 << ATMEL_ID_PIOCDE, &pmc->pcer);
  68 + at91_periph_clk_enable(ATMEL_ID_PIOA);
  69 + at91_periph_clk_enable(ATMEL_ID_PIOCDE);
70 70  
71 71 /* Configure RDY/BSY */
72 72 gpio_request(CONFIG_SYS_NAND_READY_PIN, "NAND ready/busy");
... ... @@ -81,10 +81,7 @@
81 81 #ifdef CONFIG_MACB
82 82 static void usb_a9263_macb_hw_init(void)
83 83 {
84   - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
85   -
86   - /* Enable clock */
87   - writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
  84 + at91_periph_clk_enable(ATMEL_ID_EMAC);
88 85  
89 86 /*
90 87 * Disable pull-up on:
board/denx/ma5d4evk/Kconfig
Diff comments   View file @ 20680b5
  1 +if TARGET_MA5D4EVK
  2 +
  3 +config SYS_BOARD
  4 + default "ma5d4evk"
  5 +
  6 +config SYS_VENDOR
  7 + default "denx"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "ma5d4evk"
  11 +
  12 +endif
board/denx/ma5d4evk/MAINTAINERS
Diff comments   View file @ 20680b5
  1 +DENX MA5D4EVK BOARD
  2 +M: Marek Vasut <marek.vasut@gmail.com>
  3 +S: Maintained
  4 +F: board/denx/ma5d4evk/
  5 +F: include/configs/ma5d4evk.h
  6 +F: configs/ma5d4evk_defconfig
board/denx/ma5d4evk/Makefile
Diff comments   View file @ 20680b5
  1 +#
  2 +# Copyright (C) 2015 Marek Vasut <marex@denx.de>
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +
  7 +obj-y += ma5d4evk.o
board/denx/ma5d4evk/ma5d4evk.c
Diff comments   View file @ 20680b5
  1 +/*
  2 + * Copyright (C) 2015 Marek Vasut <marex@denx.de>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <asm/io.h>
  9 +#include <asm/arch/at91_common.h>
  10 +#include <asm/arch/at91_pmc.h>
  11 +#include <asm/arch/at91_rstc.h>
  12 +#include <asm/arch/atmel_mpddrc.h>
  13 +#include <asm/arch/atmel_usba_udc.h>
  14 +#include <asm/arch/gpio.h>
  15 +#include <asm/arch/clk.h>
  16 +#include <asm/arch/sama5d3_smc.h>
  17 +#include <asm/arch/sama5d4.h>
  18 +#include <atmel_hlcdc.h>
  19 +#include <atmel_mci.h>
  20 +#include <lcd.h>
  21 +#include <mmc.h>
  22 +#include <net.h>
  23 +#include <netdev.h>
  24 +#include <spi.h>
  25 +#include <version.h>
  26 +
  27 +DECLARE_GLOBAL_DATA_PTR;
  28 +
  29 +#ifdef CONFIG_ATMEL_SPI
  30 +int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  31 +{
  32 + return bus == 0 && cs == 0;
  33 +}
  34 +
  35 +void spi_cs_activate(struct spi_slave *slave)
  36 +{
  37 + at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
  38 +}
  39 +
  40 +void spi_cs_deactivate(struct spi_slave *slave)
  41 +{
  42 + at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
  43 +}
  44 +
  45 +static void ma5d4evk_spi0_hw_init(void)
  46 +{
  47 + at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */
  48 + at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */
  49 + at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */
  50 +
  51 + at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */
  52 +
  53 + /* Enable clock */
  54 + at91_periph_clk_enable(ATMEL_ID_SPI0);
  55 +}
  56 +#endif /* CONFIG_ATMEL_SPI */
  57 +
  58 +#ifdef CONFIG_CMD_USB
  59 +static void ma5d4evk_usb_hw_init(void)
  60 +{
  61 + at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
  62 + at91_set_pio_output(AT91_PIO_PORTE, 14, 0);
  63 +}
  64 +#endif
  65 +
  66 +#ifdef CONFIG_LCD
  67 +vidinfo_t panel_info = {
  68 + .vl_col = 800,
  69 + .vl_row = 480,
  70 + .vl_clk = 33500000,
  71 + .vl_bpix = LCD_BPP,
  72 + .vl_tft = 1,
  73 + .vl_hsync_len = 10,
  74 + .vl_left_margin = 89,
  75 + .vl_right_margin = 164,
  76 + .vl_vsync_len = 10,
  77 + .vl_upper_margin = 23,
  78 + .vl_lower_margin = 10,
  79 + .mmio = ATMEL_BASE_LCDC,
  80 +};
  81 +
  82 +/* No power up/down pin for the LCD pannel */
  83 +void lcd_enable(void) { /* Empty! */ }
  84 +void lcd_disable(void) { /* Empty! */ }
  85 +
  86 +unsigned int has_lcdc(void)
  87 +{
  88 + return 1;
  89 +}
  90 +
  91 +static void ma5d4evk_lcd_hw_init(void)
  92 +{
  93 + at91_set_a_periph(AT91_PIO_PORTA, 24, 1); /* LCDPWM */
  94 + at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
  95 + at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
  96 + at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
  97 + at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
  98 + at91_set_a_periph(AT91_PIO_PORTA, 29, 1); /* LCDDEN */
  99 +
  100 + at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */
  101 + at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */
  102 + at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
  103 + at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
  104 + at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
  105 + at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
  106 + at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
  107 + at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
  108 +
  109 + at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */
  110 + at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */
  111 + at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
  112 + at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
  113 + at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
  114 + at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
  115 + at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
  116 + at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
  117 +
  118 + at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */
  119 + at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */
  120 + at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */
  121 + at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */
  122 + at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */
  123 + at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */
  124 + at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */
  125 + at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */
  126 +
  127 + /* Enable clock */
  128 + at91_periph_clk_enable(ATMEL_ID_LCDC);
  129 +}
  130 +
  131 +#endif /* CONFIG_LCD */
  132 +
  133 +#ifdef CONFIG_GENERIC_ATMEL_MCI
  134 +/* On-SoM eMMC */
  135 +void ma5d4evk_mci0_hw_init(void)
  136 +{
  137 + at91_set_b_periph(AT91_PIO_PORTC, 5, 1); /* MCI1 CDA */
  138 + at91_set_b_periph(AT91_PIO_PORTC, 6, 1); /* MCI1 DA0 */
  139 + at91_set_b_periph(AT91_PIO_PORTC, 7, 1); /* MCI1 DA1 */
  140 + at91_set_b_periph(AT91_PIO_PORTC, 8, 1); /* MCI1 DA2 */
  141 + at91_set_b_periph(AT91_PIO_PORTC, 9, 1); /* MCI1 DA3 */
  142 + at91_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI1 DA4 */
  143 + at91_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI1 DA5 */
  144 + at91_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI1 DA6 */
  145 + at91_set_b_periph(AT91_PIO_PORTC, 13, 1); /* MCI1 DA7 */
  146 + at91_set_b_periph(AT91_PIO_PORTC, 4, 0); /* MCI1 CLK */
  147 +
  148 + /*
  149 + * As the mci io internal pull down is too strong, so if the io needs
  150 + * external pull up, the pull up resistor will be very small, if so
  151 + * the power consumption will increase, so disable the internal pull
  152 + * down to save the power.
  153 + */
  154 + at91_set_pio_pulldown(AT91_PIO_PORTC, 5, 0);
  155 + at91_set_pio_pulldown(AT91_PIO_PORTC, 6, 0);
  156 + at91_set_pio_pulldown(AT91_PIO_PORTC, 7, 0);
  157 + at91_set_pio_pulldown(AT91_PIO_PORTC, 8, 0);
  158 + at91_set_pio_pulldown(AT91_PIO_PORTC, 9, 0);
  159 + at91_set_pio_pulldown(AT91_PIO_PORTC, 10, 0);
  160 + at91_set_pio_pulldown(AT91_PIO_PORTC, 11, 0);
  161 + at91_set_pio_pulldown(AT91_PIO_PORTC, 12, 0);
  162 + at91_set_pio_pulldown(AT91_PIO_PORTC, 13, 0);
  163 + at91_set_pio_pulldown(AT91_PIO_PORTC, 4, 0);
  164 +
  165 + /* Enable clock */
  166 + at91_periph_clk_enable(ATMEL_ID_MCI0);
  167 +}
  168 +
  169 +/* On-board MicroSD slot */
  170 +void ma5d4evk_mci1_hw_init(void)
  171 +{
  172 + at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */
  173 + at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */
  174 + at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */
  175 + at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */
  176 + at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */
  177 + at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */
  178 +
  179 + /*
  180 + * As the mci io internal pull down is too strong, so if the io needs
  181 + * external pull up, the pull up resistor will be very small, if so
  182 + * the power consumption will increase, so disable the internal pull
  183 + * down to save the power.
  184 + */
  185 + at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
  186 + at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
  187 + at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
  188 + at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
  189 + at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
  190 + at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
  191 +
  192 + /* Deal with WP pin on the microSD slot. */
  193 + at91_set_pio_output(AT91_PIO_PORTE, 16, 0);
  194 + at91_set_pio_pulldown(AT91_PIO_PORTE, 16, 1);
  195 +
  196 + /* Enable clock */
  197 + at91_periph_clk_enable(ATMEL_ID_MCI1);
  198 +}
  199 +
  200 +int board_mmc_init(bd_t *bis)
  201 +{
  202 + int ret;
  203 +
  204 + /* De-assert reset on On-SoM eMMC */
  205 + at91_set_pio_output(AT91_PIO_PORTE, 15, 1);
  206 + at91_set_pio_pulldown(AT91_PIO_PORTE, 15, 0);
  207 +
  208 + ret = atmel_mci_init((void *)ATMEL_BASE_MCI0);
  209 + if (ret) /* eMMC init failed, skip it. */
  210 + at91_set_pio_output(AT91_PIO_PORTE, 15, 0);
  211 +
  212 + /* Enable the power supply to On-board MicroSD */
  213 + at91_set_pio_output(AT91_PIO_PORTE, 17, 0);
  214 +
  215 + ret = atmel_mci_init((void *)ATMEL_BASE_MCI1);
  216 + if (ret) /* uSD init failed, power it down. */
  217 + at91_set_pio_output(AT91_PIO_PORTE, 17, 1);
  218 +
  219 + return 0;
  220 +}
  221 +#endif /* CONFIG_GENERIC_ATMEL_MCI */
  222 +
  223 +#ifdef CONFIG_MACB
  224 +void ma5d4evk_macb0_hw_init(void)
  225 +{
  226 + at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */
  227 + at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */
  228 + at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */
  229 + at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */
  230 + at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */
  231 + at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */
  232 + at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */
  233 + at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */
  234 + at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */
  235 + at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */
  236 +
  237 + /* Enable clock */
  238 + at91_periph_clk_enable(ATMEL_ID_GMAC0);
  239 +}
  240 +#endif
  241 +
  242 +static void ma5d4evk_serial_hw_init(void)
  243 +{
  244 + /* USART0 */
  245 + at91_set_a_periph(AT91_PIO_PORTD, 13, 1); /* TXD */
  246 + at91_set_a_periph(AT91_PIO_PORTD, 12, 0); /* RXD */
  247 + at91_set_a_periph(AT91_PIO_PORTD, 11, 0); /* RTS */
  248 + at91_set_a_periph(AT91_PIO_PORTD, 10, 0); /* CTS */
  249 + at91_periph_clk_enable(ATMEL_ID_USART0);
  250 +
  251 + /* USART1 */
  252 + at91_set_a_periph(AT91_PIO_PORTD, 17, 1); /* TXD */
  253 + at91_set_a_periph(AT91_PIO_PORTD, 16, 0); /* RXD */
  254 + at91_set_a_periph(AT91_PIO_PORTD, 15, 0); /* RTS */
  255 + at91_set_a_periph(AT91_PIO_PORTD, 14, 0); /* CTS */
  256 + at91_periph_clk_enable(ATMEL_ID_USART1);
  257 +}
  258 +
  259 +int board_early_init_f(void)
  260 +{
  261 + at91_periph_clk_enable(ATMEL_ID_PIOA);
  262 + at91_periph_clk_enable(ATMEL_ID_PIOB);
  263 + at91_periph_clk_enable(ATMEL_ID_PIOC);
  264 + at91_periph_clk_enable(ATMEL_ID_PIOD);
  265 + at91_periph_clk_enable(ATMEL_ID_PIOE);
  266 +
  267 + /* Configure LEDs as OFF */
  268 + at91_set_pio_output(AT91_PIO_PORTD, 28, 0);
  269 + at91_set_pio_output(AT91_PIO_PORTD, 29, 0);
  270 + at91_set_pio_output(AT91_PIO_PORTD, 30, 0);
  271 +
  272 + /* Reset CAN controllers */
  273 + at91_set_pio_output(AT91_PIO_PORTB, 21, 0);
  274 + udelay(100);
  275 + at91_set_pio_output(AT91_PIO_PORTB, 21, 1);
  276 + at91_set_pio_pulldown(AT91_PIO_PORTB, 21, 0);
  277 +
  278 + ma5d4evk_serial_hw_init();
  279 +
  280 + return 0;
  281 +}
  282 +
  283 +int board_init(void)
  284 +{
  285 + /* adress of boot parameters */
  286 + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  287 +
  288 +#ifdef CONFIG_ATMEL_SPI
  289 + ma5d4evk_spi0_hw_init();
  290 +#endif
  291 +#ifdef CONFIG_GENERIC_ATMEL_MCI
  292 + ma5d4evk_mci0_hw_init();
  293 + ma5d4evk_mci1_hw_init();
  294 +#endif
  295 +#ifdef CONFIG_MACB
  296 + ma5d4evk_macb0_hw_init();
  297 +#endif
  298 +#ifdef CONFIG_LCD
  299 + ma5d4evk_lcd_hw_init();
  300 +#endif
  301 +#ifdef CONFIG_CMD_USB
  302 + ma5d4evk_usb_hw_init();
  303 +#endif
  304 +#ifdef CONFIG_USB_GADGET_ATMEL_USBA
  305 + at91_udp_hw_init();
  306 +#endif
  307 +
  308 + return 0;
  309 +}
  310 +
  311 +int dram_init(void)
  312 +{
  313 + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  314 + CONFIG_SYS_SDRAM_SIZE);
  315 + return 0;
  316 +}
  317 +
  318 +int board_eth_init(bd_t *bis)
  319 +{
  320 + int rc = 0;
  321 +
  322 +#ifdef CONFIG_MACB
  323 + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);
  324 +#endif
  325 +
  326 +#ifdef CONFIG_USB_GADGET_ATMEL_USBA
  327 + usba_udc_probe(&pdata);
  328 +#ifdef CONFIG_USB_ETH_RNDIS
  329 + usb_eth_initialize(bis);
  330 +#endif
  331 +#endif
  332 +
  333 + return rc;
  334 +}
  335 +
  336 +/* SPL */
  337 +#ifdef CONFIG_SPL_BUILD
  338 +void spl_board_init(void)
  339 +{
  340 + ma5d4evk_spi0_hw_init();
  341 +}
  342 +
  343 +static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
  344 +{
  345 + ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
  346 +
  347 + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
  348 + ATMEL_MPDDRC_CR_NR_ROW_13 |
  349 + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
  350 + ATMEL_MPDDRC_CR_NB_8BANKS |
  351 + ATMEL_MPDDRC_CR_NDQS_DISABLED |
  352 + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
  353 + ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
  354 +
  355 + ddr2->rtr = 0x2b0;
  356 +
  357 + ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
  358 + 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
  359 + 3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
  360 + 10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
  361 + 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
  362 + 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
  363 + 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
  364 + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
  365 +
  366 + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
  367 + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
  368 + 25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
  369 + 23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
  370 +
  371 + ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
  372 + 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
  373 + 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
  374 + 2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
  375 + 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
  376 +}
  377 +
  378 +void mem_init(void)
  379 +{
  380 + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  381 + struct atmel_mpddrc_config ddr2;
  382 +
  383 + ddr2_conf(&ddr2);
  384 +
  385 + /* enable MPDDR clock */
  386 + at91_periph_clk_enable(ATMEL_ID_MPDDRC);
  387 + writel(AT91_PMC_DDR, &pmc->scer);
  388 +
  389 + /* DDRAM2 Controller initialize */
  390 + ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
  391 +}
  392 +
  393 +void at91_pmc_init(void)
  394 +{
  395 + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  396 + u32 tmp;
  397 +
  398 + tmp = AT91_PMC_PLLAR_29 |
  399 + AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
  400 + AT91_PMC_PLLXR_MUL(87) |
  401 + AT91_PMC_PLLXR_DIV(1);
  402 + at91_plla_init(tmp);
  403 +
  404 + writel(0x0 << 8, &pmc->pllicpr);
  405 +
  406 + tmp = AT91_PMC_MCKR_H32MXDIV |
  407 + AT91_PMC_MCKR_PLLADIV_2 |
  408 + AT91_PMC_MCKR_MDIV_3 |
  409 + AT91_PMC_MCKR_CSS_PLLA;
  410 + at91_mck_init(tmp);
  411 +}
  412 +#endif
board/egnite/ethernut5/ethernut5.c
Diff comments   View file @ 20680b5
... ... @@ -67,8 +67,8 @@
67 67 #include <asm/arch/at91sam9260_matrix.h>
68 68 #include <asm/arch/at91sam9_smc.h>
69 69 #include <asm/arch/at91_common.h>
70   -#include <asm/arch/at91_pmc.h>
71 70 #include <asm/arch/at91_spi.h>
  71 +#include <asm/arch/clk.h>
72 72 #include <asm/arch/gpio.h>
73 73 #include <asm/io.h>
74 74 #include <asm/gpio.h>
75 75  
... ... @@ -151,12 +151,10 @@
151 151 */
152 152 int board_init(void)
153 153 {
154   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  154 + at91_periph_clk_enable(ATMEL_ID_PIOA);
  155 + at91_periph_clk_enable(ATMEL_ID_PIOB);
  156 + at91_periph_clk_enable(ATMEL_ID_PIOC);
155 157  
156   - /* Enable clocks for all PIOs */
157   - writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
158   - (1 << ATMEL_ID_PIOC),
159   - &pmc->pcer);
160 158 /* Set adress of boot parameters. */
161 159 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
162 160 /* Initialize UARTs and power management. */
163 161  
... ... @@ -179,10 +177,9 @@
179 177 {
180 178 const char *devname;
181 179 unsigned short mode;
182   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
183 180  
184   - /* Enable on-chip EMAC clock. */
185   - writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
  181 + at91_periph_clk_enable(ATMEL_ID_EMAC0);
  182 +
186 183 /* Need to reset PHY via power management. */
187 184 ethernut5_phy_reset();
188 185 /* Set peripheral pins. */
189 186  
... ... @@ -211,10 +208,8 @@
211 208 #ifdef CONFIG_GENERIC_ATMEL_MCI
212 209 int board_mmc_init(bd_t *bd)
213 210 {
214   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  211 + at91_periph_clk_enable(ATMEL_ID_MCI);
215 212  
216   - /* Enable MCI clock. */
217   - writel(1 << ATMEL_ID_MCI, &pmc->pcer);
218 213 /* Initialize MCI hardware. */
219 214 at91_mci_hw_init();
220 215 /* Register the device. */
... ... @@ -229,6 +224,7 @@
229 224  
230 225 #ifdef CONFIG_ATMEL_SPI
231 226 /*
  227 +
232 228 * Note, that u-boot uses different code for SPI bus access. While
233 229 * memory routines use automatic chip select control, the serial
234 230 * flash support requires 'manual' GPIO control. Thus, we switch
board/esd/meesc/meesc.c
Diff comments   View file @ 20680b5
... ... @@ -87,9 +87,8 @@
87 87 #ifdef CONFIG_MACB
88 88 static void meesc_macb_hw_init(void)
89 89 {
90   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
91   - /* Enable clock */
92   - writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
  90 + at91_periph_clk_enable(ATMEL_ID_EMAC);
  91 +
93 92 at91_macb_hw_init();
94 93 }
95 94 #endif
... ... @@ -244,12 +243,10 @@
244 243  
245 244 int board_early_init_f(void)
246 245 {
247   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
248   -
249   - /* enable all clocks */
250   - writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
251   - (1 << ATMEL_ID_PIOCDE) | (1 << ATMEL_ID_UHP),
252   - &pmc->pcer);
  246 + at91_periph_clk_enable(ATMEL_ID_PIOA);
  247 + at91_periph_clk_enable(ATMEL_ID_PIOB);
  248 + at91_periph_clk_enable(ATMEL_ID_PIOCDE);
  249 + at91_periph_clk_enable(ATMEL_ID_UHP);
253 250  
254 251 at91_seriald_hw_init();
255 252  
board/l+g/vinco/Kconfig
Diff comments   View file @ 20680b5
  1 +if TARGET_VINCO
  2 +
  3 +config SYS_BOARD
  4 + default "vinco"
  5 +
  6 +config SYS_VENDOR
  7 + default "l+g"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "vinco"
  11 +
  12 +endif
board/l+g/vinco/MAINTAINERS
Diff comments   View file @ 20680b5
  1 +VInCo Platform
  2 +M: Gregory CLEMENT <gregory.clement@free-electrons.com>
  3 +S: Maintained
  4 +F: board/l+g/vinco
  5 +F: include/configs/vinco.h
  6 +F: configs/vinco_defconfig
board/l+g/vinco/Makefile
Diff comments   View file @ 20680b5
  1 +obj-y += vinco.o
board/l+g/vinco/vinco.c
Diff comments   View file @ 20680b5
  1 +/*
  2 + * Board file for the VInCo platform
  3 + * Based on the the SAMA5-EK board file
  4 + * Configuration settings for the VInCo platform.
  5 + * Copyright (C) 2014 Atmel
  6 + * Bo Shen <voice.shen@atmel.com>
  7 + * Copyright (C) 2015 Free Electrons
  8 + * Gregory CLEMENT <gregory.clement@free-electrons.com>
  9 + *
  10 + * SPDX-License-Identifier: GPL-2.0+
  11 + */
  12 +
  13 +#include <common.h>
  14 +#include <asm/io.h>
  15 +#include <asm/arch/at91_common.h>
  16 +#include <asm/arch/at91_pmc.h>
  17 +#include <asm/arch/at91_rstc.h>
  18 +#include <asm/arch/atmel_mpddrc.h>
  19 +#include <asm/arch/atmel_usba_udc.h>
  20 +#include <asm/arch/gpio.h>
  21 +#include <asm/arch/clk.h>
  22 +#include <asm/arch/sama5d3_smc.h>
  23 +#include <asm/arch/sama5d4.h>
  24 +#include <atmel_hlcdc.h>
  25 +#include <atmel_mci.h>
  26 +#include <lcd.h>
  27 +#include <mmc.h>
  28 +#include <net.h>
  29 +#include <netdev.h>
  30 +#include <nand.h>
  31 +#include <spi.h>
  32 +#include <version.h>
  33 +
  34 +DECLARE_GLOBAL_DATA_PTR;
  35 +
  36 +#ifdef CONFIG_ATMEL_SPI
  37 +int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  38 +{
  39 + return bus == 0 && cs == 0;
  40 +}
  41 +
  42 +void spi_cs_activate(struct spi_slave *slave)
  43 +{
  44 + at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
  45 +}
  46 +
  47 +void spi_cs_deactivate(struct spi_slave *slave)
  48 +{
  49 + at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
  50 +}
  51 +
  52 +static void vinco_spi0_hw_init(void)
  53 +{
  54 + at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */
  55 + at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */
  56 + at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */
  57 +
  58 + at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */
  59 +
  60 + /* Enable clock */
  61 + at91_periph_clk_enable(ATMEL_ID_SPI0);
  62 +}
  63 +#endif /* CONFIG_ATMEL_SPI */
  64 +
  65 +
  66 +#ifdef CONFIG_CMD_USB
  67 +static void vinco_usb_hw_init(void)
  68 +{
  69 + at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
  70 + at91_set_pio_output(AT91_PIO_PORTE, 12, 0);
  71 + at91_set_pio_output(AT91_PIO_PORTE, 10, 0);
  72 +}
  73 +#endif
  74 +
  75 +
  76 +#ifdef CONFIG_GENERIC_ATMEL_MCI
  77 +void vinco_mci0_hw_init(void)
  78 +{
  79 + at91_set_b_periph(AT91_PIO_PORTC, 5, 1); /* MCI0 CDA */
  80 + at91_set_b_periph(AT91_PIO_PORTC, 6, 1); /* MCI0 DA0 */
  81 + at91_set_b_periph(AT91_PIO_PORTC, 7, 1); /* MCI0 DA1 */
  82 + at91_set_b_periph(AT91_PIO_PORTC, 8, 1); /* MCI0 DA2 */
  83 + at91_set_b_periph(AT91_PIO_PORTC, 9, 1); /* MCI0 DA3 */
  84 + at91_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI0 DA4 */
  85 + at91_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI0 DA5 */
  86 + at91_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI0 DA6 */
  87 + at91_set_b_periph(AT91_PIO_PORTC, 13, 1); /* MCI0 DA7 */
  88 + at91_set_b_periph(AT91_PIO_PORTC, 4, 0); /* MCI0 CLK */
  89 +
  90 + /*
  91 + * As the mci io internal pull down is too strong, so if the io needs
  92 + * external pull up, the pull up resistor will be very small, if so
  93 + * the power consumption will increase, so disable the interanl pull
  94 + * down to save the power.
  95 + */
  96 + at91_set_pio_pulldown(AT91_PIO_PORTC, 4, 0);
  97 + at91_set_pio_pulldown(AT91_PIO_PORTC, 5, 0);
  98 + at91_set_pio_pulldown(AT91_PIO_PORTC, 6, 0);
  99 + at91_set_pio_pulldown(AT91_PIO_PORTC, 7, 0);
  100 + at91_set_pio_pulldown(AT91_PIO_PORTC, 8, 0);
  101 + at91_set_pio_pulldown(AT91_PIO_PORTC, 9, 0);
  102 + at91_set_pio_pulldown(AT91_PIO_PORTC, 10, 0);
  103 + at91_set_pio_pulldown(AT91_PIO_PORTC, 11, 0);
  104 + at91_set_pio_pulldown(AT91_PIO_PORTC, 12, 0);
  105 + at91_set_pio_pulldown(AT91_PIO_PORTC, 13, 0);
  106 +
  107 + /* Enable clock */
  108 + at91_periph_clk_enable(ATMEL_ID_MCI0);
  109 +}
  110 +
  111 +int board_mmc_init(bd_t *bis)
  112 +{
  113 + /* Enable power for MCI0 interface */
  114 + at91_set_pio_output(AT91_PIO_PORTE, 7, 1);
  115 +
  116 + return atmel_mci_init((void *)ATMEL_BASE_MCI0);
  117 +}
  118 +#endif /* CONFIG_GENERIC_ATMEL_MCI */
  119 +
  120 +#ifdef CONFIG_MACB
  121 +void vinco_macb0_hw_init(void)
  122 +{
  123 + at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */
  124 + at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */
  125 + at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */
  126 + at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */
  127 + at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */
  128 + at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */
  129 + at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */
  130 + at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */
  131 + at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */
  132 + at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */
  133 +
  134 + /* Enable clock */
  135 + at91_periph_clk_enable(ATMEL_ID_GMAC0);
  136 +
  137 + /* Enable Phy*/
  138 + at91_set_pio_output(AT91_PIO_PORTE, 8, 1);
  139 +}
  140 +#endif
  141 +
  142 +static void vinco_serial3_hw_init(void)
  143 +{
  144 + at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */
  145 + at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */
  146 +
  147 + /* Enable clock */
  148 + at91_periph_clk_enable(ATMEL_ID_USART3);
  149 +}
  150 +
  151 +int board_early_init_f(void)
  152 +{
  153 + at91_periph_clk_enable(ATMEL_ID_PIOA);
  154 + at91_periph_clk_enable(ATMEL_ID_PIOB);
  155 + at91_periph_clk_enable(ATMEL_ID_PIOC);
  156 + at91_periph_clk_enable(ATMEL_ID_PIOD);
  157 + at91_periph_clk_enable(ATMEL_ID_PIOE);
  158 +
  159 + vinco_serial3_hw_init();
  160 +
  161 + return 0;
  162 +}
  163 +
  164 +int board_init(void)
  165 +{
  166 + /* adress of boot parameters */
  167 + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  168 +
  169 +#ifdef CONFIG_ATMEL_SPI
  170 + vinco_spi0_hw_init();
  171 +#endif
  172 +
  173 +#ifdef CONFIG_GENERIC_ATMEL_MCI
  174 + vinco_mci0_hw_init();
  175 +#endif
  176 +#ifdef CONFIG_MACB
  177 + vinco_macb0_hw_init();
  178 +#endif
  179 +#ifdef CONFIG_CMD_USB
  180 + vinco_usb_hw_init();
  181 +#endif
  182 +#ifdef CONFIG_USB_GADGET_ATMEL_USBA
  183 + at91_udp_hw_init();
  184 +#endif
  185 +
  186 + return 0;
  187 +}
  188 +
  189 +int dram_init(void)
  190 +{
  191 + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  192 + CONFIG_SYS_SDRAM_SIZE);
  193 + return 0;
  194 +}
  195 +
  196 +int board_eth_init(bd_t *bis)
  197 +{
  198 + int rc = 0;
  199 +
  200 +#ifdef CONFIG_MACB
  201 + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);
  202 +#endif
  203 +
  204 +#ifdef CONFIG_USB_GADGET_ATMEL_USBA
  205 + usba_udc_probe(&pdata);
  206 +#ifdef CONFIG_USB_ETH_RNDIS
  207 + usb_eth_initialize(bis);
  208 +#endif
  209 +#endif
  210 +
  211 + return rc;
  212 +}
board/mini-box/picosam9g45/led.c
Diff comments   View file @ 20680b5
... ... @@ -9,15 +9,12 @@
9 9 #include <common.h>
10 10 #include <asm/io.h>
11 11 #include <asm/arch/at91sam9g45.h>
12   -#include <asm/arch/at91_pmc.h>
  12 +#include <asm/arch/clk.h>
13 13 #include <asm/arch/gpio.h>
14 14  
15 15 void coloured_LED_init(void)
16 16 {
17   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
18   -
19   - /* Enable clock */
20   - writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
  17 + at91_periph_clk_enable(ATMEL_ID_PIODE);
21 18  
22 19 at91_set_gpio_output(CONFIG_GREEN_LED, 1);
23 20  
board/mini-box/picosam9g45/picosam9g45.c
Diff comments   View file @ 20680b5
... ... @@ -17,7 +17,6 @@
17 17 #include <asm/arch/at91sam9g45_matrix.h>
18 18 #include <asm/arch/at91sam9_smc.h>
19 19 #include <asm/arch/at91_common.h>
20   -#include <asm/arch/at91_pmc.h>
21 20 #include <asm/arch/gpio.h>
22 21 #include <asm/arch/clk.h>
23 22 #include <lcd.h>
24 23  
... ... @@ -80,15 +79,13 @@
80 79  
81 80 void mem_init(void)
82 81 {
83   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
84 82 struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
85 83 struct atmel_mpddrc_config ddr2;
86 84 unsigned long csa;
87 85  
88 86 ddr2_conf(&ddr2);
89 87  
90   - /* enable DDR2 clock */
91   - writel(AT91_PMC_DDR, &pmc->scer);
  88 + at91_system_clk_enable(AT91_PMC_DDR);
92 89  
93 90 /* Chip select 1 is for DDR2/SDRAM */
94 91 csa = readl(&mat->ebicsa);
95 92  
... ... @@ -105,10 +102,8 @@
105 102 #ifdef CONFIG_CMD_USB
106 103 static void picosam9g45_usb_hw_init(void)
107 104 {
108   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  105 + at91_periph_clk_enable(ATMEL_ID_PIODE);
109 106  
110   - writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
111   -
112 107 at91_set_gpio_output(AT91_PIN_PD1, 0);
113 108 at91_set_gpio_output(AT91_PIN_PD3, 0);
114 109 }
115 110  
... ... @@ -117,11 +112,9 @@
117 112 #ifdef CONFIG_MACB
118 113 static void picosam9g45_macb_hw_init(void)
119 114 {
120   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
121 115 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
122 116  
123   - /* Enable clock */
124   - writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
  117 + at91_periph_clk_enable(ATMEL_ID_EMAC);
125 118  
126 119 /*
127 120 * Disable pull-up on:
... ... @@ -181,8 +174,6 @@
181 174  
182 175 static void picosam9g45_lcd_hw_init(void)
183 176 {
184   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
185   -
186 177 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
187 178 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
188 179 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
... ... @@ -214,7 +205,7 @@
214 205 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
215 206 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
216 207  
217   - writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
  208 + at91_periph_clk_enable(ATMEL_ID_LCDC);
218 209  
219 210 gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
220 211 }
board/ronetix/pm9261/led.c
Diff comments   View file @ 20680b5
... ... @@ -9,15 +9,12 @@
9 9  
10 10 #include <common.h>
11 11 #include <asm/gpio.h>
12   -#include <asm/arch/at91_pmc.h>
  12 +#include <asm/arch/clk.h>
13 13 #include <asm/arch/gpio.h>
14 14  
15 15 void coloured_LED_init(void)
16 16 {
17   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
18   -
19   - /* Enable clock */
20   - writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
  17 + at91_periph_clk_enable(ATMEL_ID_PIOC);
21 18  
22 19 gpio_direction_output(CONFIG_RED_LED, 1);
23 20 gpio_direction_output(CONFIG_GREEN_LED, 1);
board/ronetix/pm9261/pm9261.c
Diff comments   View file @ 20680b5
... ... @@ -14,7 +14,6 @@
14 14 #include <asm/gpio.h>
15 15 #include <asm/arch/at91sam9_smc.h>
16 16 #include <asm/arch/at91_common.h>
17   -#include <asm/arch/at91_pmc.h>
18 17 #include <asm/arch/at91_rstc.h>
19 18 #include <asm/arch/at91_matrix.h>
20 19 #include <asm/arch/clk.h>
... ... @@ -41,7 +40,6 @@
41 40 unsigned long csa;
42 41 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
43 42 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
44   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
45 43  
46 44 /* Enable CS3 */
47 45 csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
... ... @@ -69,9 +67,8 @@
69 67 AT91_SMC_MODE_TDF_CYCLE(2),
70 68 &smc->cs[3].mode);
71 69  
72   - writel(1 << ATMEL_ID_PIOA |
73   - 1 << ATMEL_ID_PIOC,
74   - &pmc->pcer);
  70 + at91_periph_clk_enable(ATMEL_ID_PIOA);
  71 + at91_periph_clk_enable(ATMEL_ID_PIOC);
75 72  
76 73 /* Configure RDY/BSY */
77 74 gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
... ... @@ -89,7 +86,6 @@
89 86 static void pm9261_dm9000_hw_init(void)
90 87 {
91 88 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
92   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
93 89  
94 90 /* Configure SMC CS2 for DM9000 */
95 91 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
... ... @@ -110,7 +106,7 @@
110 106 &smc->cs[2].mode);
111 107  
112 108 /* Configure Interrupt pin as input, no pull-up */
113   - writel(1 << ATMEL_ID_PIOA, &pmc->pcer);
  109 + at91_periph_clk_enable(ATMEL_ID_PIOA);
114 110 at91_set_pio_input(AT91_PIO_PORTA, 24, 0);
115 111 }
116 112 #endif
... ... @@ -145,8 +141,6 @@
145 141  
146 142 static void pm9261_lcd_hw_init(void)
147 143 {
148   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
149   -
150 144 at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* LCDHSYNC */
151 145 at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* LCDDOTCK */
152 146 at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* LCDDEN */
... ... @@ -170,7 +164,7 @@
170 164 at91_set_b_periph(AT91_PIO_PORTB, 27, 0); /* LCDD22 */
171 165 at91_set_b_periph(AT91_PIO_PORTB, 28, 0); /* LCDD23 */
172 166  
173   - writel(1 << 17, &pmc->scer); /* LCD controller Clock, AT91SAM9261 only */
  167 + at91_system_clk_enable(AT91_PMC_HCK1);
174 168  
175 169 gd->fb_base = ATMEL_BASE_SRAM;
176 170 }
... ... @@ -224,12 +218,8 @@
224 218  
225 219 int board_early_init_f(void)
226 220 {
227   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
228   -
229   - /* Enable clocks for some PIOs */
230   - writel(1 << ATMEL_ID_PIOA |
231   - 1 << ATMEL_ID_PIOC,
232   - &pmc->pcer);
  221 + at91_periph_clk_enable(ATMEL_ID_PIOA);
  222 + at91_periph_clk_enable(ATMEL_ID_PIOC);
233 223  
234 224 at91_seriald_hw_init();
235 225  
board/ronetix/pm9263/led.c
Diff comments   View file @ 20680b5
... ... @@ -9,15 +9,12 @@
9 9  
10 10 #include <common.h>
11 11 #include <asm/gpio.h>
12   -#include <asm/arch/at91_pmc.h>
  12 +#include <asm/arch/clk.h>
13 13 #include <asm/arch/gpio.h>
14 14  
15 15 void coloured_LED_init(void)
16 16 {
17   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
18   -
19   - /* Enable clock */
20   - writel(1 << ATMEL_ID_PIOB, &pmc->pcer);
  17 + at91_periph_clk_enable(ATMEL_ID_PIOB);
21 18  
22 19 gpio_direction_output(CONFIG_RED_LED, 1);
23 20 gpio_direction_output(CONFIG_GREEN_LED, 1);
board/ronetix/pm9263/pm9263.c
Diff comments   View file @ 20680b5
... ... @@ -14,7 +14,6 @@
14 14 #include <asm/gpio.h>
15 15 #include <asm/arch/at91sam9_smc.h>
16 16 #include <asm/arch/at91_common.h>
17   -#include <asm/arch/at91_pmc.h>
18 17 #include <asm/arch/at91_rstc.h>
19 18 #include <asm/arch/at91_matrix.h>
20 19 #include <asm/arch/clk.h>
... ... @@ -78,8 +77,6 @@
78 77 #ifdef CONFIG_MACB
79 78 static void pm9263_macb_hw_init(void)
80 79 {
81   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
82   -
83 80 /*
84 81 * PB27 enables the 50MHz oscillator for Ethernet PHY
85 82 * 1 - enable
... ... @@ -88,8 +85,7 @@
88 85 at91_set_pio_output(AT91_PIO_PORTB, 27, 1);
89 86 at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */
90 87  
91   - /* Enable clock */
92   - writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
  88 + at91_periph_clk_enable(ATMEL_ID_EMAC);
93 89  
94 90 /*
95 91 * Disable pull-up on:
... ... @@ -231,8 +227,6 @@
231 227  
232 228 static void pm9263_lcd_hw_init(void)
233 229 {
234   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
235   -
236 230 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
237 231 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
238 232 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
... ... @@ -257,7 +251,7 @@
257 251 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
258 252 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
259 253  
260   - writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
  254 + at91_periph_clk_enable(ATMEL_ID_LCDC);
261 255  
262 256 /* Power Control */
263 257 at91_set_pio_output(AT91_PIO_PORTA, 22, 1);
... ... @@ -323,12 +317,9 @@
323 317  
324 318 int board_early_init_f(void)
325 319 {
326   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
327   -
328   - /* Enable clocks for all PIOs */
329   - writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
330   - (1 << ATMEL_ID_PIOCDE),
331   - &pmc->pcer);
  320 + at91_periph_clk_enable(ATMEL_ID_PIOA);
  321 + at91_periph_clk_enable(ATMEL_ID_PIOB);
  322 + at91_periph_clk_enable(ATMEL_ID_PIOCDE);
332 323  
333 324 at91_seriald_hw_init();
334 325  
board/ronetix/pm9g45/pm9g45.c
Diff comments   View file @ 20680b5
... ... @@ -17,7 +17,6 @@
17 17 #include <asm/gpio.h>
18 18 #include <asm/arch/at91sam9_smc.h>
19 19 #include <asm/arch/at91_common.h>
20   -#include <asm/arch/at91_pmc.h>
21 20 #include <asm/arch/at91_rstc.h>
22 21 #include <asm/arch/at91_matrix.h>
23 22 #include <asm/arch/gpio.h>
... ... @@ -39,7 +38,6 @@
39 38 unsigned long csa;
40 39 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
41 40 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
42   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
43 41  
44 42 /* Enable CS3 */
45 43 csa = readl(&matrix->ccr[6]) | AT91_MATRIX_CSA_EBI_CS3A;
... ... @@ -63,7 +61,7 @@
63 61 AT91_SMC_MODE_TDF_CYCLE(3),
64 62 &smc->cs[3].mode);
65 63  
66   - writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
  64 + at91_periph_clk_enable(ATMEL_ID_PIOC);
67 65  
68 66 #ifdef CONFIG_SYS_NAND_READY_PIN
69 67 /* Configure RDY/BSY */
... ... @@ -78,8 +76,6 @@
78 76 #ifdef CONFIG_MACB
79 77 static void pm9g45_macb_hw_init(void)
80 78 {
81   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
82   -
83 79 /*
84 80 * PD2 enables the 50MHz oscillator for Ethernet PHY
85 81 * 1 - enable
... ... @@ -88,8 +84,7 @@
88 84 at91_set_pio_output(AT91_PIO_PORTD, 2, 1);
89 85 at91_set_pio_value(AT91_PIO_PORTD, 2, 1); /* 1- enable, 0 - disable */
90 86  
91   - /* Enable clock */
92   - writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
  87 + at91_periph_clk_enable(ATMEL_ID_EMAC);
93 88  
94 89 /*
95 90 * Disable pull-up on:
... ... @@ -114,13 +109,10 @@
114 109  
115 110 int board_early_init_f(void)
116 111 {
117   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
118   -
119   - /* Enable clocks for all PIOs */
120   - writel((1 << ATMEL_ID_PIOA) |
121   - (1 << ATMEL_ID_PIOB) |
122   - (1 << ATMEL_ID_PIOC) |
123   - (1 << ATMEL_ID_PIODE), &pmc->pcer);
  112 + at91_periph_clk_enable(ATMEL_ID_PIOA);
  113 + at91_periph_clk_enable(ATMEL_ID_PIOB);
  114 + at91_periph_clk_enable(ATMEL_ID_PIOC);
  115 + at91_periph_clk_enable(ATMEL_ID_PIODE);
124 116  
125 117 at91_seriald_hw_init();
126 118  
board/siemens/corvus/board.c
Diff comments   View file @ 20680b5
... ... @@ -17,7 +17,6 @@
17 17 #include <asm/arch/at91sam9g45_matrix.h>
18 18 #include <asm/arch/at91sam9_smc.h>
19 19 #include <asm/arch/at91_common.h>
20   -#include <asm/arch/at91_pmc.h>
21 20 #include <asm/arch/at91_rstc.h>
22 21 #include <asm/arch/gpio.h>
23 22 #include <asm/arch/clk.h>
24 23  
... ... @@ -147,13 +146,11 @@
147 146  
148 147 void mem_init(void)
149 148 {
150   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
151 149 struct atmel_mpddrc_config ddr2;
152 150  
153 151 ddr2_conf(&ddr2);
154 152  
155   - /* enable DDR2 clock */
156   - writel(AT91_PMC_DDR, &pmc->scer);
  153 + at91_system_clk_enable(AT91_PMC_DDR);
157 154  
158 155 /* DDRAM2 Controller initialize */
159 156 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
160 157  
... ... @@ -210,10 +207,9 @@
210 207 /* from ./arch/arm/mach-at91/armv7/sama5d3_devices.c */
211 208 void at91_udp_hw_init(void)
212 209 {
213   - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
214   -
215 210 /* Enable UPLL clock */
216   - writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
  211 + at91_upll_clk_enable();
  212 +
217 213 /* Enable UDPHS clock */
218 214 at91_periph_clk_enable(ATMEL_ID_UDPHS);
219 215 }
board/siemens/smartweb/smartweb.c
Diff comments   View file @ 20680b5
... ... @@ -22,7 +22,6 @@
22 22 #include <asm/arch/at91sam9260_matrix.h>
23 23 #include <asm/arch/at91sam9_smc.h>
24 24 #include <asm/arch/at91_common.h>
25   -#include <asm/arch/at91_pmc.h>
26 25 #include <asm/arch/at91_spi.h>
27 26 #include <spi.h>
28 27 #include <asm/arch/clk.h>
29 28  
30 29  
... ... @@ -116,17 +115,13 @@
116 115  
117 116 void at91_udp_hw_init(void)
118 117 {
119   - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
120   -
121 118 /* Enable PLLB */
122   - writel(get_pllb_init(), &pmc->pllbr);
123   - while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
124   - ;
  119 + at91_pllb_clk_enable(get_pllb_init());
125 120  
126 121 /* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
127 122 at91_periph_clk_enable(ATMEL_ID_UDP);
128 123  
129   - writel(AT91SAM926x_PMC_UDP, &pmc->scer);
  124 + at91_system_clk_enable(AT91SAM926x_PMC_UDP);
130 125 }
131 126  
132 127 struct at91_udc_data board_udc_data = {
board/siemens/taurus/taurus.c
Diff comments   View file @ 20680b5
... ... @@ -18,7 +18,6 @@
18 18 #include <asm/arch/at91sam9260_matrix.h>
19 19 #include <asm/arch/at91sam9_smc.h>
20 20 #include <asm/arch/at91_common.h>
21   -#include <asm/arch/at91_pmc.h>
22 21 #include <asm/arch/at91_rstc.h>
23 22 #include <asm/arch/gpio.h>
24 23 #include <asm/arch/at91sam9_sdramc.h>
25 24  
26 25  
... ... @@ -290,17 +289,13 @@
290 289  
291 290 void at91_udp_hw_init(void)
292 291 {
293   - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
294   -
295 292 /* Enable PLLB */
296   - writel(get_pllb_init(), &pmc->pllbr);
297   - while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
298   - ;
  293 + at91_pllb_clk_enable(get_pllb_init());
299 294  
300 295 /* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
301 296 at91_periph_clk_enable(ATMEL_ID_UDP);
302 297  
303   - writel(AT91SAM926x_PMC_UDP, &pmc->scer);
  298 + at91_system_clk_enable(AT91SAM926x_PMC_UDP);
304 299 }
305 300  
306 301 struct at91_udc_data board_udc_data = {
configs/ma5d4evk_defconfig
Diff comments   View file @ 20680b5
  1 +CONFIG_ARM=y
  2 +CONFIG_ARCH_AT91=y
  3 +CONFIG_TARGET_MA5D4EVK=y
  4 +CONFIG_SPL=y
  5 +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4"
  6 +# CONFIG_CMD_IMI is not set
  7 +# CONFIG_CMD_IMLS is not set
  8 +# CONFIG_CMD_LOADS is not set
  9 +# CONFIG_CMD_FLASH is not set
  10 +# CONFIG_CMD_FPGA is not set
  11 +CONFIG_SPI_FLASH=y
configs/smartweb_defconfig
Diff comments   View file @ 20680b5
... ... @@ -3,5 +3,8 @@
3 3 CONFIG_TARGET_SMARTWEB=y
4 4 CONFIG_SPL=y
5 5 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
6   -CONFIG_SYS_PROMPT="U-Boot> "
  6 +CONFIG_SYS_PROMPT="U-Boot# "
  7 +CONFIG_AUTOBOOT_KEYED=y
  8 +CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
  9 +CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
configs/vinco_defconfig
Diff comments   View file @ 20680b5
  1 +CONFIG_ARM=y
  2 +CONFIG_ARCH_AT91=y
  3 +CONFIG_TARGET_VINCO=y
  4 +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
  5 +CONFIG_SYS_PROMPT="vinco => "
  6 +# CONFIG_CMD_IMI is not set
  7 +# CONFIG_CMD_IMLS is not set
  8 +# CONFIG_CMD_LOADS is not set
  9 +# CONFIG_CMD_FLASH is not set
  10 +# CONFIG_CMD_FPGA is not set
  11 +CONFIG_SPI_FLASH=y
  12 +CONFIG_NETDEVICES=y
  13 +CONFIG_ETH_DESIGNWARE=y
drivers/net/at91_emac.c
Diff comments   View file @ 20680b5
... ... @@ -12,7 +12,7 @@
12 12 #include <asm/io.h>
13 13 #include <asm/arch/hardware.h>
14 14 #include <asm/arch/at91_emac.h>
15   -#include <asm/arch/at91_pmc.h>
  15 +#include <asm/arch/clk.h>
16 16 #include <asm/arch/at91_pio.h>
17 17 #include <net.h>
18 18 #include <netdev.h>
... ... @@ -321,7 +321,6 @@
321 321 emac_device *dev;
322 322 at91_emac_t *emac;
323 323 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
324   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
325 324  
326 325 emac = (at91_emac_t *) netdev->iobase;
327 326 dev = (emac_device *) netdev->priv;
... ... @@ -347,7 +346,8 @@
347 346 writel(value, &pio->piob.pdr);
348 347 writel(value, &pio->piob.bsr);
349 348  
350   - writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
  349 + at91_periph_clk_enable(ATMEL_ID_EMAC);
  350 +
351 351 writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl);
352 352  
353 353 /* Init Ethernet buffers */
354 354  
... ... @@ -452,10 +452,10 @@
452 452 static int at91emac_write_hwaddr(struct eth_device *netdev)
453 453 {
454 454 at91_emac_t *emac;
455   - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
456 455 emac = (at91_emac_t *) netdev->iobase;
457 456  
458   - writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
  457 + at91_periph_clk_enable(ATMEL_ID_EMAC);
  458 +
459 459 debug_cond(DEBUG_AT91EMAC,
460 460 "init MAC-ADDR %02x:%02x:%02x:%02x:%02x:%02x\n",
461 461 netdev->enetaddr[5], netdev->enetaddr[4], netdev->enetaddr[3],
drivers/usb/host/ehci-atmel.c
Diff comments   View file @ 20680b5
... ... @@ -7,44 +7,21 @@
7 7 */
8 8  
9 9 #include <common.h>
10   -#include <watchdog.h>
11 10 #include <usb.h>
12 11 #include <asm/io.h>
13   -#include <asm/arch/hardware.h>
14   -#include <asm/arch/at91_pmc.h>
15 12 #include <asm/arch/clk.h>
16 13  
17 14 #include "ehci.h"
18 15  
19   -/* Enable UTMI PLL time out 500us
20   - * 10 times as datasheet specified
21   - */
22   -#define EN_UPLL_TIMEOUT 500UL
23   -
24 16 int ehci_hcd_init(int index, enum usb_init_type init,
25 17 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
26 18 {
27   - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
28   - ulong start_time, tmp_time;
29   -
30   - start_time = get_timer(0);
31 19 /* Enable UTMI PLL */
32   - writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
33   - while ((readl(&pmc->sr) & AT91_PMC_LOCKU) != AT91_PMC_LOCKU) {
34   - WATCHDOG_RESET();
35   - tmp_time = get_timer(0);
36   - if ((tmp_time - start_time) > EN_UPLL_TIMEOUT) {
37   - printf("ERROR: failed to enable UPLL\n");
38   - return -1;
39   - }
40   - }
  20 + if (at91_upll_clk_enable())
  21 + return -1;
41 22  
42 23 /* Enable USB Host clock */
43   -#ifdef CPU_HAS_PCR
44 24 at91_periph_clk_enable(ATMEL_ID_UHPHS);
45   -#else
46   - writel(1 << ATMEL_ID_UHPHS, &pmc->pcer);
47   -#endif
48 25  
49 26 *hccr = (struct ehci_hccr *)ATMEL_BASE_EHCI;
50 27 *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
51 28  
52 29  
53 30  
54 31  
... ... @@ -55,27 +32,12 @@
55 32  
56 33 int ehci_hcd_stop(int index)
57 34 {
58   - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
59   - ulong start_time, tmp_time;
60   -
61 35 /* Disable USB Host Clock */
62   -#ifdef CPU_HAS_PCR
63 36 at91_periph_clk_disable(ATMEL_ID_UHPHS);
64   -#else
65   - writel(1 << ATMEL_ID_UHPHS, &pmc->pcdr);
66   -#endif
67 37  
68   - start_time = get_timer(0);
69 38 /* Disable UTMI PLL */
70   - writel(readl(&pmc->uckr) & ~AT91_PMC_UPLLEN, &pmc->uckr);
71   - while ((readl(&pmc->sr) & AT91_PMC_LOCKU) == AT91_PMC_LOCKU) {
72   - WATCHDOG_RESET();
73   - tmp_time = get_timer(0);
74   - if ((tmp_time - start_time) > EN_UPLL_TIMEOUT) {
75   - printf("ERROR: failed to stop UPLL\n");
76   - return -1;
77   - }
78   - }
  39 + if (at91_upll_clk_disable())
  40 + return -1;
79 41  
80 42 return 0;
81 43 }
drivers/usb/host/ohci-at91.c
Diff comments   View file @ 20680b5
... ... @@ -9,45 +9,29 @@
9 9  
10 10 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
11 11  
12   -#include <asm/io.h>
13   -#include <asm/arch/hardware.h>
14   -#include <asm/arch/at91_pmc.h>
15 12 #include <asm/arch/clk.h>
16 13  
17 14 int usb_cpu_init(void)
18 15 {
19   - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
20   -
21 16 #ifdef CONFIG_USB_ATMEL_CLK_SEL_PLLB
22   - /* Enable PLLB */
23   - writel(get_pllb_init(), &pmc->pllbr);
24   - while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
25   - ;
  17 + if (at91_pllb_clk_enable(get_pllb_init()))
  18 + return -1;
  19 +
26 20 #ifdef CONFIG_AT91SAM9N12
27   - writel(AT91_PMC_USBS_USB_PLLB | AT91_PMC_USB_DIV_2, &pmc->usb);
  21 + at91_usb_clk_init(AT91_PMC_USBS_USB_PLLB | AT91_PMC_USB_DIV_2);
28 22 #endif
29 23 #elif defined(CONFIG_USB_ATMEL_CLK_SEL_UPLL)
30   - /* Enable UPLL */
31   - writel(readl(&pmc->uckr) | AT91_PMC_UPLLEN | AT91_PMC_BIASEN,
32   - &pmc->uckr);
33   - while ((readl(&pmc->sr) & AT91_PMC_LOCKU) != AT91_PMC_LOCKU)
34   - ;
  24 + if (at91_upll_clk_enable())
  25 + return -1;
35 26  
36   - /* Select PLLA as input clock of OHCI */
37   - writel(AT91_PMC_USBS_USB_UPLL | AT91_PMC_USBDIV_10, &pmc->usb);
  27 + at91_usb_clk_init(AT91_PMC_USBS_USB_UPLL | AT91_PMC_USBDIV_10);
38 28 #endif
39 29  
40   - /* Enable USB host clock. */
41   -#ifdef CPU_HAS_PCR
42 30 at91_periph_clk_enable(ATMEL_ID_UHP);
43   -#else
44   - writel(1 << ATMEL_ID_UHP, &pmc->pcer);
45   -#endif
46 31  
  32 + at91_system_clk_enable(ATMEL_PMC_UHP);
47 33 #if defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10)
48   - writel(ATMEL_PMC_UHP | AT91_PMC_HCK0, &pmc->scer);
49   -#else
50   - writel(ATMEL_PMC_UHP, &pmc->scer);
  34 + at91_system_clk_enable(AT91_PMC_HCK0);
51 35 #endif
52 36  
53 37 return 0;
54 38  
55 39  
56 40  
57 41  
58 42  
59 43  
... ... @@ -55,34 +39,24 @@
55 39  
56 40 int usb_cpu_stop(void)
57 41 {
58   - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
59   -
60   - /* Disable USB host clock. */
61   -#ifdef CPU_HAS_PCR
62 42 at91_periph_clk_disable(ATMEL_ID_UHP);
63   -#else
64   - writel(1 << ATMEL_ID_UHP, &pmc->pcdr);
65   -#endif
66 43  
  44 + at91_system_clk_disable(ATMEL_PMC_UHP);
67 45 #if defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10)
68   - writel(ATMEL_PMC_UHP | AT91_PMC_HCK0, &pmc->scdr);
69   -#else
70   - writel(ATMEL_PMC_UHP, &pmc->scdr);
  46 + at91_system_clk_disable(AT91_PMC_HCK0);
71 47 #endif
72 48  
73 49 #ifdef CONFIG_USB_ATMEL_CLK_SEL_PLLB
74 50 #ifdef CONFIG_AT91SAM9N12
75   - writel(0, &pmc->usb);
  51 + at91_usb_clk_init(0);
76 52 #endif
77   - /* Disable PLLB */
78   - writel(0, &pmc->pllbr);
79   - while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0)
80   - ;
  53 +
  54 + if (at91_pllb_clk_disable())
  55 + return -1;
  56 +
81 57 #elif defined(CONFIG_USB_ATMEL_CLK_SEL_UPLL)
82   - /* Disable UPLL */
83   - writel(readl(&pmc->uckr) & (~AT91_PMC_UPLLEN), &pmc->uckr);
84   - while ((readl(&pmc->sr) & AT91_PMC_LOCKU) == AT91_PMC_LOCKU)
85   - ;
  58 + if (at91_upll_clk_disable())
  59 + return -1;
86 60 #endif
87 61  
88 62 return 0;
include/configs/ma5d4evk.h
Diff comments   View file @ 20680b5
  1 +/*
  2 + * DENX MA5D4 configuration
  3 + * Copyright (C) 2015 Marek Vasut <marex@denx.de>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef __MA5D4EVK_CONFIG_H__
  9 +#define __MA5D4EVK_CONFIG_H__
  10 +
  11 +#define CONFIG_SYS_NO_FLASH
  12 +
  13 +#define CONFIG_FIT
  14 +
  15 +#define CONFIG_TIMESTAMP /* Print image info with timestamp */
  16 +
  17 +#include "at91-sama5_common.h"
  18 +#undef CONFIG_BOOTARGS
  19 +#define CONFIG_SYS_USE_SERIALFLASH 1
  20 +
  21 +/*
  22 + * U-Boot Commands
  23 + */
  24 +#define CONFIG_DOS_PARTITION
  25 +#define CONFIG_FAT_WRITE
  26 +/*#define CONFIG_LCD*/
  27 +
  28 +#define CONFIG_CMD_ASKENV
  29 +#define CONFIG_CMD_CACHE
  30 +#define CONFIG_CMD_DHCP
  31 +#define CONFIG_CMD_EXT4
  32 +#define CONFIG_CMD_EXT4_WRITE
  33 +#define CONFIG_CMD_FAT
  34 +#define CONFIG_CMD_FS_GENERIC
  35 +#define CONFIG_CMD_GREPENV
  36 +#define CONFIG_CMD_MII
  37 +#define CONFIG_CMD_MMC
  38 +#define CONFIG_CMD_PING
  39 +#define CONFIG_CMD_SF
  40 +#define CONFIG_CMD_USB
  41 +
  42 +/*
  43 + * Memory configurations
  44 + */
  45 +#define CONFIG_NR_DRAM_BANKS 1
  46 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
  47 +#define CONFIG_SYS_SDRAM_SIZE 0x10000000
  48 +
  49 +#ifdef CONFIG_SPL_BUILD
  50 +#define CONFIG_SYS_INIT_SP_ADDR 0x210000
  51 +#else
  52 +#define CONFIG_SYS_INIT_SP_ADDR \
  53 + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
  54 +#endif
  55 +
  56 +/*
  57 + * Environment
  58 + */
  59 +#define CONFIG_ENV_IS_IN_SPI_FLASH
  60 +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
  61 +#define CONFIG_ENV_OFFSET 0x8000
  62 +#define CONFIG_ENV_SIZE 0x4000
  63 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
  64 +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
  65 +#define CONFIG_ENV_SECT_SIZE 0x1000
  66 +
  67 +/*
  68 + * U-Boot general configurations
  69 + */
  70 +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
  71 +
  72 +/*
  73 + * Serial Driver
  74 + */
  75 +#define CONFIG_ATMEL_USART
  76 +#define CONFIG_USART_BASE ATMEL_BASE_USART0
  77 +#define CONFIG_USART_ID ATMEL_ID_USART0
  78 +
  79 +/*
  80 + * Ethernet
  81 + */
  82 +#ifdef CONFIG_CMD_NET
  83 +#define CONFIG_MACB
  84 +#define CONFIG_RMII
  85 +#define CONFIG_NET_RETRY_COUNT 20
  86 +#define CONFIG_MACB_SEARCH_PHY
  87 +#define CONFIG_ARP_TIMEOUT 200UL
  88 +#define CONFIG_IP_DEFRAG
  89 +#endif
  90 +
  91 +/*
  92 + * LCD
  93 + */
  94 +#ifdef CONFIG_LCD
  95 +#define CONFIG_CMD_BMP
  96 +#define CONFIG_BMP_16BPP
  97 +#define CONFIG_BMP_24BPP
  98 +#define CONFIG_BMP_32BPP
  99 +#define LCD_BPP LCD_COLOR16
  100 +#define LCD_OUTPUT_BPP 24
  101 +#define CONFIG_ATMEL_HLCD
  102 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV
  103 +#endif
  104 +
  105 +/*
  106 + * SD/MMC
  107 + */
  108 +#ifdef CONFIG_CMD_MMC
  109 +#define CONFIG_MMC
  110 +#define CONFIG_GENERIC_MMC
  111 +#define CONFIG_GENERIC_ATMEL_MCI
  112 +#endif
  113 +
  114 +/*
  115 + * SPI NOR (boot memory)
  116 + */
  117 +#ifdef CONFIG_CMD_SF
  118 +#define CONFIG_ATMEL_SPI
  119 +#define CONFIG_ATMEL_SPI0
  120 +#define CONFIG_SPI_FLASH_ATMEL
  121 +#define CONFIG_SF_DEFAULT_BUS 0
  122 +#define CONFIG_SF_DEFAULT_CS 0
  123 +#define CONFIG_SF_DEFAULT_SPEED 30000000
  124 +#endif
  125 +
  126 +/*
  127 + * USB
  128 + */
  129 +#ifdef CONFIG_CMD_USB
  130 +#define CONFIG_USB_EHCI
  131 +#define CONFIG_USB_EHCI_ATMEL
  132 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
  133 +#define CONFIG_USB_STORAGE
  134 +
  135 +/* USB device */
  136 +#define CONFIG_USB_GADGET
  137 +#define CONFIG_USB_GADGET_DUALSPEED
  138 +#define CONFIG_USB_GADGET_ATMEL_USBA
  139 +#define CONFIG_USB_ETHER
  140 +#define CONFIG_USB_ETH_RNDIS
  141 +#define CONFIG_USBNET_MANUFACTURER "DENX"
  142 +#endif
  143 +
  144 +/*
  145 + * Boot Linux
  146 + */
  147 +#define CONFIG_CMDLINE_TAG
  148 +#define CONFIG_INITRD_TAG
  149 +#define CONFIG_SETUP_MEMORY_TAGS
  150 +#define CONFIG_BOOTDELAY 3
  151 +#define CONFIG_BOOTFILE "fitImage"
  152 +#define CONFIG_BOOTARGS "console=ttyS3,115200"
  153 +#define CONFIG_LOADADDR 0x20800000
  154 +#define CONFIG_BOOTCOMMAND "run mmc_mmc"
  155 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  156 +#define CONFIG_OF_LIBFDT
  157 +
  158 +/*
  159 + * Extra Environments
  160 + */
  161 +#define CONFIG_PREBOOT "run try_bootscript"
  162 +#define CONFIG_HOSTNAME ma5d4evk
  163 +
  164 +#define CONFIG_EXTRA_ENV_SETTINGS \
  165 + "consdev=ttyS3\0" \
  166 + "baudrate=115200\0" \
  167 + "bootscript=boot.scr\0" \
  168 + "bootdev=/dev/mmcblk1p1\0" \
  169 + "bootpart=1:1\0" \
  170 + "rootdev=/dev/mmcblk1p2\0" \
  171 + "netdev=eth0\0" \
  172 + "kernel_addr_r=0x22000000\0" \
  173 + "update_spi_firmware_spl_addr=0x21000000\0" \
  174 + "update_spi_firmware_spl_filename=boot.bin\0" \
  175 + "update_spi_firmware_addr=0x22000000\0" \
  176 + "update_spi_firmware_filename=u-boot.img\0" \
  177 + "update_spi_firmware=" /* Update the SPI flash firmware */ \
  178 + "if sf probe ; then " \
  179 + "if tftp ${update_spi_firmware_spl_addr} " \
  180 + "${update_spi_firmware_spl_filename} ; then " \
  181 + "setenv update_spi_firmware_spl_filesize ${filesize} ; "\
  182 + "if tftp ${update_spi_firmware_addr} " \
  183 + "${update_spi_firmware_filename} ; then " \
  184 + "setenv update_spi_firmware_filesize ${filesize} ; " \
  185 + "sf update ${update_spi_firmware_spl_addr} 0x0 " \
  186 + "${update_spi_firmware_spl_filesize} ; " \
  187 + "sf update ${update_spi_firmware_addr} 0x10000 " \
  188 + "${update_spi_firmware_filesize} ; " \
  189 + "fi ; " \
  190 + "fi ; " \
  191 + "fi\0" \
  192 + "addcons=" \
  193 + "setenv bootargs ${bootargs} " \
  194 + "console=${consdev},${baudrate}\0" \
  195 + "addip=" \
  196 + "setenv bootargs ${bootargs} " \
  197 + "ip=${ipaddr}:${serverip}:${gatewayip}:" \
  198 + "${netmask}:${hostname}:${netdev}:off\0" \
  199 + "addmisc=" \
  200 + "setenv bootargs ${bootargs} ${miscargs}\0" \
  201 + "addargs=run addcons addmisc\0" \
  202 + "mmcload=" \
  203 + "mmc rescan ; " \
  204 + "load mmc ${bootpart} ${kernel_addr_r} ${bootfile}\0" \
  205 + "netload=" \
  206 + "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
  207 + "miscargs=nohlt panic=1\0" \
  208 + "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \
  209 + "nfsargs=" \
  210 + "setenv bootargs root=/dev/nfs rw " \
  211 + "nfsroot=${serverip}:${rootpath},v3,tcp\0" \
  212 + "mmc_mmc=" \
  213 + "run mmcload mmcargs addargs ; " \
  214 + "bootm ${kernel_addr_r}\0" \
  215 + "mmc_nfs=" \
  216 + "run mmcload nfsargs addip addargs ; " \
  217 + "bootm ${kernel_addr_r}\0" \
  218 + "net_mmc=" \
  219 + "run netload mmcargs addargs ; " \
  220 + "bootm ${kernel_addr_r}\0" \
  221 + "net_nfs=" \
  222 + "run netload nfsargs addip addargs ; " \
  223 + "bootm ${kernel_addr_r}\0" \
  224 + "try_bootscript=" \
  225 + "mmc rescan;" \
  226 + "if test -e mmc ${bootpart} ${bootscript} ; then " \
  227 + "if load mmc ${bootpart} ${kernel_addr_r} ${bootscript};"\
  228 + "then ; " \
  229 + "echo Running bootscript... ; " \
  230 + "source ${kernel_addr_r} ; " \
  231 + "fi ; " \
  232 + "fi\0"
  233 +/* SPL */
  234 +#define CONFIG_SPL_FRAMEWORK
  235 +#define CONFIG_SPL_TEXT_BASE 0x200000
  236 +#define CONFIG_SPL_MAX_SIZE 0x10000
  237 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000
  238 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  239 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
  240 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
  241 +
  242 +#define CONFIG_SPL_LIBCOMMON_SUPPORT
  243 +#define CONFIG_SPL_LIBGENERIC_SUPPORT
  244 +#define CONFIG_SPL_GPIO_SUPPORT
  245 +#define CONFIG_SPL_SERIAL_SUPPORT
  246 +
  247 +#define CONFIG_SPL_BOARD_INIT
  248 +#define CONFIG_SYS_MONITOR_LEN (512 << 10)
  249 +
  250 +#define CONFIG_SPL_SPI_SUPPORT
  251 +#define CONFIG_SPL_SPI_FLASH_SUPPORT
  252 +#define CONFIG_SPL_SPI_LOAD
  253 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
  254 +
  255 +#endif /* __MA5D4EVK_CONFIG_H__ */
include/configs/smartweb.h
Diff comments   View file @ 20680b5
... ... @@ -49,10 +49,18 @@
49 49 #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
50 50 #define CONFIG_DISPLAY_CPUINFO /* display CPU Info at startup */
51 51  
  52 +/* We set the max number of command args high to avoid HUSH bugs. */
  53 +#define CONFIG_SYS_MAXARGS 32
  54 +
52 55 /* setting board specific options */
53   -# define CONFIG_MACH_TYPE MACH_TYPE_SMARTWEB
54   -#define CONFIG_CMDLINE_EDITING
  56 +#define CONFIG_MACH_TYPE MACH_TYPE_SMARTWEB
55 57 #define CONFIG_AUTO_COMPLETE
  58 +#define CONFIG_ENV_OVERWRITE 1 /* Overwrite ethaddr / serial# */
  59 +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
  60 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  61 +#define CONFIG_AUTO_COMPLETE
  62 +#define CONFIG_SYS_AUTOLOAD "yes"
  63 +#define CONFIG_RESET_TO_RETRY
56 64  
57 65 /* The LED PINs */
58 66 #define CONFIG_RED_LED AT91_PIN_PA9
59 67  
... ... @@ -184,9 +192,7 @@
184 192 /* General Boot Parameter */
185 193 #define CONFIG_BOOTDELAY 3
186 194 #define CONFIG_BOOTCOMMAND "run flashboot"
187   -#define CONFIG_BOOT_RETRY_TIME 30
188 195 #define CONFIG_SYS_CBSIZE 512
189   -#define CONFIG_SYS_MAXARGS 16
190 196 #define CONFIG_SYS_PBSIZE \
191 197 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
192 198 #define CONFIG_SYS_LONGHELP
include/configs/vinco.h
Diff comments   View file @ 20680b5
  1 +/*
  2 + * Configuration settings for the VInCo platform.
  3 + *
  4 + * Based on the settings for the SAMA5-EK board
  5 + * Copyright (C) 2014 Atmel
  6 + * Bo Shen <voice.shen@atmel.com>
  7 + * Copyright (C) 2015 Free Electrons
  8 + * Gregory CLEMENT gregory.clement@free-electrons.com
  9 + *
  10 + * SPDX-License-Identifier: GPL-2.0+
  11 + */
  12 +
  13 +#ifndef __CONFIG_H
  14 +#define __CONFIG_H
  15 +
  16 +/* No NOR flash, this definition should be put before common header */
  17 +#define CONFIG_SYS_NO_FLASH
  18 +
  19 +#include "at91-sama5_common.h"
  20 +
  21 +/* The value in the common file is too far away for the VInCo platform */
  22 +#ifdef CONFIG_SYS_TEXT_BASE
  23 +#undef CONFIG_SYS_TEXT_BASE
  24 +#endif
  25 +#define CONFIG_SYS_TEXT_BASE 0x20f00000
  26 +
  27 +/* serial console */
  28 +#define CONFIG_ATMEL_USART
  29 +#define CONFIG_USART_BASE ATMEL_BASE_USART3
  30 +#define CONFIG_USART_ID ATMEL_ID_USART3
  31 +
  32 +/* SDRAM */
  33 +#define CONFIG_NR_DRAM_BANKS 1
  34 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
  35 +#define CONFIG_SYS_SDRAM_SIZE 0x4000000
  36 +
  37 +
  38 +#define CONFIG_SYS_INIT_SP_ADDR \
  39 + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
  40 +
  41 +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
  42 +
  43 +/* SerialFlash */
  44 +#define CONFIG_CMD_SF
  45 +
  46 +#ifdef CONFIG_CMD_SF
  47 +#define CONFIG_ATMEL_SPI
  48 +#define CONFIG_ATMEL_SPI0
  49 +#define CONFIG_SPI_FLASH_STMICRO
  50 +#define CONFIG_SF_DEFAULT_BUS 0
  51 +#define CONFIG_SF_DEFAULT_CS 0
  52 +#define CONFIG_SF_DEFAULT_SPEED 50000000
  53 +#define CONFIG_ENV_SPI_MAX_HZ 50000000
  54 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
  55 +#define CONFIG_ENV_SPI_MODE (SPI_MODE_0)
  56 +#endif
  57 +
  58 +
  59 +/* MMC */
  60 +#define CONFIG_CMD_MMC
  61 +
  62 +#ifdef CONFIG_CMD_MMC
  63 +#define CONFIG_SUPPORT_EMMC_BOOT
  64 +#define CONFIG_MMC
  65 +#define CONFIG_GENERIC_MMC
  66 +#define CONFIG_GENERIC_ATMEL_MCI
  67 +#define ATMEL_BASE_MMCI ATMEL_BASE_MCI1
  68 +#define CONFIG_SYS_MMC_CLK_OD 500000
  69 +
  70 +/* For generating MMC partitions */
  71 +#define CONFIG_PARTITION_UUIDS
  72 +#define CONFIG_RANDOM_UUID
  73 +#define CONFIG_EFI_PARTITION
  74 +#define CONFIG_CMD_GPT
  75 +
  76 +#endif
  77 +
  78 +/* USB */
  79 +#define CONFIG_CMD_USB
  80 +
  81 +#ifdef CONFIG_CMD_USB
  82 +#define CONFIG_USB_EHCI
  83 +#define CONFIG_USB_EHCI_ATMEL
  84 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
  85 +#define CONFIG_USB_STORAGE
  86 +#endif
  87 +
  88 +/* USB device */
  89 +#define CONFIG_USB_GADGET
  90 +#define CONFIG_USB_GADGET_DUALSPEED
  91 +#define CONFIG_USB_GADGET_ATMEL_USBA
  92 +#define CONFIG_USB_ETHER
  93 +#define CONFIG_USB_ETH_RNDIS
  94 +#define CONFIG_USBNET_MANUFACTURER "L+G VInCo"
  95 +
  96 +#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
  97 +#define CONFIG_CMD_FAT
  98 +#define CONFIG_DOS_PARTITION
  99 +#endif
  100 +
  101 +/* Ethernet Hardware */
  102 +#define CONFIG_CMD_MII
  103 +#define CONFIG_PHY_SMSC
  104 +#define CONFIG_MACB
  105 +#define CONFIG_RMII
  106 +#define CONFIG_NET_RETRY_COUNT 20
  107 +#define CONFIG_MACB_SEARCH_PHY
  108 +
  109 +
  110 +#define CONFIG_USB_HOST_ETHER
  111 +#define CONFIG_USB_ETHER_SMSC95XX
  112 +#define CONFIG_USB_ETHER_RNDIS
  113 +
  114 +
  115 +#ifdef CONFIG_SYS_USE_SERIALFLASH
  116 +/* bootstrap + u-boot + env + linux in serial flash */
  117 +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
  118 +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
  119 +/* Use our own mapping for the VInCo platform */
  120 +#undef CONFIG_ENV_OFFSET
  121 +#undef CONFIG_ENV_SIZE
  122 +
  123 +#define CONFIG_ENV_OFFSET 0x10000
  124 +#define CONFIG_ENV_SIZE 0x10000
  125 +
  126 +/* Update the bootcommand according to our mapping for the VInCo platform */
  127 +#undef CONFIG_BOOTCOMMAND
  128 +#define CONFIG_BOOTCOMMAND "mmc dev 0 0;" \
  129 + "mmc read ${loadaddr} ${k_offset} ${k_blksize};" \
  130 + "mmc read ${oftaddr} ${dtb_offset} ${dtb_blksize};" \
  131 + "bootz ${loadaddr} - ${oftaddr}"
  132 +
  133 +#undef CONFIG_BOOTARGS
  134 +#define CONFIG_BOOTARGS "console=ttyS0,115200 earlyprintk rw root=/dev/mmcblk0p2 rootfstype=ext4 rootwait quiet lpj=1990656"
  135 +
  136 +#define CONFIG_EXTRA_ENV_SETTINGS \
  137 + "kernel_start=0x20000\0" \
  138 + "kernel_size=0x800000\0" \
  139 + "mmcblksize=0x200\0" \
  140 + "oftaddr=0x21000000\0" \
  141 + "loadaddr=0x22000000\0" \
  142 + "update_uboot=tftp ${loadaddr} u-boot.bin;sf probe 0;" \
  143 + "sf erase 0x20000 0x4B000; sf write ${loadaddr} 0x20000 0x4B000\0" \
  144 + "create_partition=setexpr dtb_start ${kernel_start} + 0x400000;" \
  145 + "setexpr rootfs_start ${kernel_start} + ${kernel_size};" \
  146 + "setenv partitions 'name=kernel,size=${kernel_size}," \
  147 + "start=${kernel_start};name=rootfs,size=-';" \
  148 + "gpt write mmc 0 ${partitions} \0"\
  149 + "f2blk_size=setexpr fileblksize ${filesize} / ${mmcblksize};" \
  150 + "setexpr fileblksize ${fileblksize} + 1\0" \
  151 + "store_kernel=tftp ${loadaddr} zImage; run f2blk_size;" \
  152 + "setexpr k_blksize ${fileblksize};" \
  153 + "setexpr k_offset ${kernel_start} / ${mmcblksize};" \
  154 + "mmc write ${fileaddr} ${k_offset} ${fileblksize}\0" \
  155 + "store_dtb=tftp ${loadaddr} at91-vinco.dtb; run f2blk_size;" \
  156 + "setexpr dtb_blksize ${fileblksize};" \
  157 + "setexpr dtb_offset ${dtb_start} / ${mmcblksize};" \
  158 + "mmc write ${fileaddr} ${dtb_offset} ${fileblksize}\0" \
  159 + "store_rootfs=tftp ${loadaddr} vinco-gateway-image-vinco.ext4;" \
  160 + "setexpr rootfs_offset ${rootfs_start} / ${mmcblksize};" \
  161 + "mmc write ${fileaddr} ${rootfs_offset} ${fileblksize}\0" \
  162 + "bootdelay=0\0"
  163 +
  164 +#endif
  165 +#define CONFIG_ZERO_BOOTDELAY_CHECK
  166 +
  167 +#endif