Eric Lee / smarc-uboot

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Commit 207828e215f7e8331ea3c304b922de9d155fb68e

Authored by Hannes Petermaier
Committed by Tom Rini
1 parent 703a08f2b3
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

board/BuR: fix pinmux for MII Ethernet Interface 

The lines COL (collision detect) and CRS (carrier sense) needs to be connected
and muxed to the CPSW MAC for a proper function in half-duplex Mode of the
interface.

Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
Cc: Tom Rini <trini@ti.com>

Showing 2 changed files with 5 additions and 0 deletions Side-by-side Diff

... ... @@ -105,6 +105,8 @@
105 105 };
106 106  
107 107 static struct module_pin_mux mii1_pin_mux[] = {
  108 + {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */
  109 + {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */
108 110 {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
109 111 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
110 112 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
board/BuR/tseries/mux.c
Diff comments   View file @ 207828e
... ... @@ -64,6 +64,8 @@
64 64 };
65 65  
66 66 static struct module_pin_mux mii1_pin_mux[] = {
  67 + {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */
  68 + {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */
67 69 {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
68 70 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
69 71 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
... ... @@ -96,6 +98,7 @@
96 98 {OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* MII2_RXD1 */
97 99 {OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* MII2_RXD0 */
98 100 {OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */
  101 + {OFFSET(gpmc_wait0), (MODE(1) | RXACTIVE | PULLUP_EN)},
99 102 /*
100 103 * MII2_CRS is shared with
101 104 * NAND_WAIT0